CN210402135U - Voltage adjusting device, chip and electronic equipment - Google Patents
Voltage adjusting device, chip and electronic equipment Download PDFInfo
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- CN210402135U CN210402135U CN201921625443.4U CN201921625443U CN210402135U CN 210402135 U CN210402135 U CN 210402135U CN 201921625443 U CN201921625443 U CN 201921625443U CN 210402135 U CN210402135 U CN 210402135U
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Abstract
The utility model relates to a voltage adjusting device, chip and electronic equipment, the device includes input module, clamp module, first transistor, second transistor, control module and output module, the control module electricity connect in input module's first end reaches output module is used for: and under the condition that the difference value between the output voltage output by the output module and the input voltage is less than or equal to a preset value, outputting a Pulse Width Modulation (PWM) signal to the grid terminal of the second transistor, outputting the clamping signal to the grid terminal of the first transistor, and clamping the voltages of the grid terminals of the first transistor and the second transistor to a first voltage. The utility model discloses can make the energy loss on the first transistor at a fixed value, reduce, eliminate the wave form nature that the consumption changes along with the electric current even, can make voltage adjustment device's voltage regulation efficiency maintain at high level to reduce energy loss.
Description
Technical Field
The utility model relates to an integrated circuit technical field especially relates to a voltage adjusting device, chip and electronic equipment.
Background
The voltage regulation technology is generally applied to electronic equipment, and because the requirements of people are diversified, the rated working states of different types of electronic equipment are different, technicians need to adopt the voltage regulation technology to regulate the electric energy of the same type into the working voltage meeting the safe operation requirement of the electronic equipment so as to ensure that the electronic equipment can be always in a stable state. Can ensure through voltage adjustment circuit that electric power system can be compatible various types of electronic equipment's power supply demand, the electric energy after the adjustment is inserted to different electronic components to satisfy user's different circuit function demands, thereby the development of voltage adjustment technique has brought very big facility for electronic equipment's use, has saved electronic equipment's electric energy supply cost, makes things convenient for people's production life.
However, in the related art, when the voltage is adjusted, the power consumption is increased and the efficiency is low due to the mode switching.
SUMMERY OF THE UTILITY MODEL
Technical problem
In view of this, the present invention is to solve the technical problem of how to reduce or even eliminate the waviness of the power consumption changing with the current, so that the voltage adjusting efficiency of the voltage adjusting device is maintained at a high level, and the energy loss is reduced.
Solution scheme
In order to solve the above technical problem, according to the utility model discloses an embodiment provides a voltage adjustment device, the device includes input module, clamp module, first transistor, second transistor, control module and output module, wherein:
a first end of the input module is electrically connected to the first input end of the clamping module for receiving an input voltage, a second end of the input module is electrically connected to the second input end of the clamping module, the drain end of the second transistor and the drain end of the first transistor,
the grid end of the first transistor and the grid end of the second transistor are electrically connected with the control module, the source end of the first transistor is electrically connected with the output module, the source end of the second transistor is grounded,
the output end of the clamping module is electrically connected with the control module and used for outputting a clamping signal,
the control module is electrically connected to the first end of the input module and the output module, and is configured to:
and under the condition that the difference value between the output voltage output by the output module and the input voltage is less than or equal to a preset value, outputting a Pulse Width Modulation (PWM) signal to the grid terminal of the second transistor, outputting the clamping signal to the grid terminal of the first transistor, and clamping the voltages of the grid terminals of the first transistor and the second transistor to a first voltage.
In one possible implementation, the clamping module includes a clamping resistor, a current source, a first switch, a first capacitor, an error amplifier, and a buffer unit, where:
a first end of the clamping resistor is electrically connected to the second end of the input module, the gate terminal of the first transistor and the gate terminal of the second transistor, a second end of the clamping resistor is electrically connected to the positive terminal of the current source and the first end of the first switch,
the negative terminal of the current source is grounded,
the second end of the first switch is connected to the first end of the first capacitor and the negative electrode end of the error amplifier, the control end of the first switch is electrically connected to the control module,
the second terminal of the first capacitor is grounded,
the output end of the error amplifier is electrically connected with the input end of the buffer unit,
the output end of the buffer unit is electrically connected with the control module,
wherein the buffer unit includes a voltage follower.
In one possible implementation, the outputting the clamp signal to the gate terminal of the first transistor includes:
outputting a first switch control signal to control a conduction state of the first switch to output the clamp signal to a gate terminal of the first transistor,
the first voltage is a voltage generated by the current source on the clamping resistor, and the first switch control signal is an inverted signal of the PWM signal.
In one possible embodiment, the control module is further configured to:
and under the condition that the difference value between the output voltage and the input voltage is greater than a preset value, outputting the PWM signal to the grid terminal of the first transistor and the grid terminal of the second transistor.
In a possible embodiment, the control module includes a mode switching sub-module, a control sub-module and a duty cycle adjusting sub-module, an input terminal of the mode switching sub-module is configured to receive the input voltage and the output voltage, an output terminal of the mode switching sub-module is electrically connected to a first input terminal of the control sub-module, a second input terminal of the control sub-module is electrically connected to an output terminal of the duty cycle adjusting sub-module, and an input terminal of the duty cycle adjusting sub-module is configured to receive a feedback voltage of the output module, wherein,
the mode switching submodule is used for outputting a mode switching signal according to the magnitude relation of the input voltage and the output voltage;
the duty ratio adjusting submodule is used for adjusting the duty ratio of the PWM signal according to the feedback voltage;
the control sub-module is configured to:
outputting a PWM signal to gates of the first transistor and the second transistor according to the mode switching signal; or
Outputting a PWM signal to a gate of the second transistor and outputting the clamp signal to a gate of the first transistor according to the mode switching signal.
In one possible implementation, the control module further includes a switch submodule electrically connected to the clamping module, the control module, and the gate of the first transistor, and the control module is further configured to:
and controlling the conduction state of the switch submodule according to the mode switching signal so as to output the clamping signal to the grid electrode of the first transistor or output the PWM signal to the grid electrode of the first transistor.
In one possible embodiment, the input module comprises an inductor, and the output module comprises a first output resistor, a second output resistor, and an output capacitor, wherein,
the first end of the first output resistor is electrically connected to the source of the first transistor and the first end of the output capacitor for outputting the output voltage,
the second end of the first output resistor is electrically connected to the first end of the second output resistor,
the second end of the second output resistor and the second end of the output capacitor are grounded.
In order to solve the above technical problem, according to another embodiment of the present invention, there is provided a chip, including:
the voltage adjusting device.
In order to solve the above technical problem, according to another embodiment of the present invention, there is provided an electronic apparatus including:
the chip is described.
Advantageous effects
According to the above device, the present invention outputs the PWM signal to the gate terminal of the second transistor Q2 and outputs the clamp signal to the gate terminal of the first transistor Q1 when the difference between the output voltage outputted from the output module 40 and the input voltage is less than or equal to the predetermined value, so that the voltages of the gate terminals of the first transistor Q2 and the second transistor Q1 can be clamped to the first voltage, and thus, when the voltage regulator is switched from the boost mode (boost) to the diode (diode) mode, the energy loss of the first transistor Q1 is fixed, the waveform of the power consumption varying with the current is reduced or even eliminated, the voltage regulation efficiency of the voltage regulator can be maintained at a high level, and the energy loss is reduced.
Other features and aspects of the present invention will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present invention and, together with the description, serve to explain the principles of the invention.
Fig. 1 shows a schematic diagram of a voltage regulating device according to an embodiment of the present invention.
Fig. 2a shows a schematic diagram of a voltage regulating device according to an embodiment of the present invention.
Fig. 2b shows a schematic view of a buffer unit according to an embodiment of the present invention.
Fig. 3 shows a schematic diagram of voltage regulation with a voltage regulation device.
Fig. 4 shows an effect schematic diagram of voltage adjustment by using the voltage adjustment transpose of the present invention.
Detailed Description
Various exemplary embodiments, features and aspects of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present invention.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a voltage adjustment apparatus according to an embodiment of the disclosure.
As shown in fig. 1, the apparatus includes an input module 10, a clamping module 20, a first transistor Q1, a second transistor Q2, a control module 30, and an output module 40, wherein:
a first terminal of the input module 10 is electrically connected to the first input terminal of the clamping module 20 for receiving an input voltage Vin, a second terminal of the input module 10 is electrically connected to the second input terminal of the clamping module 20, the drain terminal of the second transistor Q2, and the drain terminal of the first transistor Q3,
the gate terminal of the first transistor Q1 and the gate terminal of the second transistor Q2 are electrically connected to the control module 30, the source terminal of the first transistor Q1 is electrically connected to the output module 40, the source terminal of the second transistor Q2 is grounded,
the output end of the clamping module 20 is electrically connected to the control module 30, and is used for outputting a clamping signal,
the control module 30 is electrically connected to the first end of the input module 10 and the output module 40, and is configured to:
when the difference between the output voltage outputted from the output module 40 and the input voltage is less than or equal to a predetermined value, a PWM signal is outputted to the gate terminal of the second transistor Q2, the clamping signal is outputted to the gate terminal of the first transistor Q1, and the voltages of the gate terminals of the first transistor Q2 and the second transistor Q1 are clamped to a first voltage.
According to the above apparatus, the present disclosure may output the pulse width modulation PWM signal to the gate terminal of the second transistor Q2 and output the clamp signal to the gate terminal of the first transistor Q1 when a difference between the output voltage output by the output module 40 and the input voltage is less than or equal to a preset value, and may clamp the voltages of the gate terminals of the first transistor Q2 and the second transistor Q1 to a first voltage, so that when the voltage adjustment apparatus is switched from the boost mode (boost) to the diode (diode) mode, the energy loss of the first transistor Q1 may be a fixed value and may not be changed with the change of the load current, and the voltage adjustment efficiency of the voltage adjustment apparatus may be maintained at a high level and the energy loss may be reduced.
In one possible implementation, the boost mode may be: the difference between the output voltage output by the output module 40 and the input voltage Vin is greater than the preset value.
In one possible embodiment, the diode mode may be: the difference between the output voltage output by the output module 40 and the input voltage is less than or equal to a preset value.
In the case that the voltage adjustment device operates in the diode mode, in the voltage adjustment device of the present disclosure, the voltage difference of the first transistor Q1 is insensitive to the current, the power consumption is less affected by the current, the waveform property varying with the current is reduced or even eliminated, high efficiency can be achieved under different load conditions, and the system stability is maintained.
In a possible embodiment, the predetermined value may be 0 to 500 mV.
Preferably, the preset value may be 100mV, 200mV, 300mV, or the like.
In a possible embodiment, the first voltage may be set according to needs, and the disclosure does not limit the value of the first voltage.
Referring to fig. 2a, fig. 2a is a schematic diagram illustrating a voltage adjustment apparatus according to an embodiment of the disclosure.
In one possible embodiment, the input module 10 may comprise an input inductance L.
It should be understood that the present disclosure has been described by taking the input module 10 as including the input inductor L as an example, but the present disclosure is not limited thereto, and in other embodiments, the input module 10 may include other components, for example, an input resistor or an input resistor network, and the input inductor L may be replaced by an input inductor network, and the present disclosure is not limited thereto.
In one possible implementation, as shown in fig. 2a, the clamping module 20 may include a clamping resistor R3, a current source I1, a first switch S1, a first capacitor C1, an error amplifier EA, and a buffer unit buffer, where:
a first end of the clamping resistor R3 is electrically connected to the second end of the input module 10, the gate terminal of the first transistor Q1, and the gate terminal of the second transistor Q2, a second end of the clamping resistor R3 is electrically connected to the positive terminal of the current source I1 and the first end of the first switch S1, the negative terminal of the current source I1 is grounded, the second end of the first switch S1 is connected to the first end of the first capacitor C1 and the negative terminal of the error amplifier EA, a control end of the first switch S1 is electrically connected to the control module 30, the second end of the first capacitor C1 is grounded, an output end of the error amplifier EA is electrically connected to the input end of the buffer unit buffer, and an output end of the buffer unit buffer is electrically connected to the control module 30.
Referring to fig. 2b, fig. 2b is a schematic diagram illustrating a buffer unit according to an embodiment of the disclosure.
In one possible embodiment, as shown in fig. 2b, the buffer unit may be a voltage follower.
In one example, the gain of the voltage follower is 1.
In one example, the buffering unit may include:
the current source Ib has a first end receiving the input voltage Vin, a second end electrically connected to the first end of the resistor Rbuf 1, the gate of the transistor nm3 and the gate of the transistor nm5,
the second end of the resistor Rbuf 1 is electrically connected to the drain of the transistor nm3, the gate of the transistor nm4 and the gate of the transistor nm6,
the gate of transistor nm3 was electrically connected to the gate of transistor nm5,
the source of transistor nm3 was electrically connected to the drain of transistor nm4,
the gate of transistor nm4 was electrically connected to the gate of transistor nm6,
the source of transistor nm5 is electrically connected to the drain of transistor nm6, the drain of transistor nm5 is electrically connected to the first terminal of resistor Rbuf 2, the gate of transistor pm2, the gate of transistor pm5, the gate of transistor pm6, the gate of transistor pm8,
a second terminal of resistor Rbuff2 is electrically coupled to the drain of transistor pm2, the gate of transistor pm1, and the gate of transistor pm7,
the source of transistor pm2 is electrically connected to the drain of transistor pm1,
the source of transistor pm1 is electrically connected to the source of transistor pm3, the source of transistor pm4, the source of transistor pm7, for receiving the input voltage Vin,
the transistors nm 3-12 form a current mirror, and the specific connection relationship between the transistors nm 7-12 is not described herein.
The gate of transistor nm1 is used for inputting clamping signals, the source of transistor nm1 is electrically connected to the drain of transistor nm7 and the source of transistor nm2, the drain of transistor nm1 is electrically connected to the drain of transistor pm3 and the source of transistor pm5,
the drain of transistor nm2 is electrically connected to the drain of transistor pm4 and the source of transistor pm6,
the gate of transistor pm3 and the gate of transistor pm4 are electrically connected to the drain of transistor pm5,
the drain of transistor pm6 is electrically connected to the gate of transistor pm9, the drain of transistor nm11 and the first terminal of capacitor Cd,
the sources of the transistors nm4, nm6, nm8, nm10 and nm12, the second end of the capacitor Cd and the drain of the transistor pm9 are grounded,
the drain of transistor pm7 is electrically connected to the source of transistor pm8,
the drain of transistor pm8, electrically connected to the source of transistor pm9 and the gate of transistor nm2, is used to output a clamping signal,
through the above buffering unit, the present disclosure may buffer the clamp signal and output the buffered clamp signal.
Of course, it should be understood that the above description of the buffer unit is exemplary, and in other embodiments, those skilled in the art may make changes and modifications as long as the buffer function can be realized.
The present disclosure does not limit the specific implementation of the buffer unit, and those skilled in the art can select the buffer unit according to actual needs.
It should be noted that the present disclosure does not limit the value of the first voltage, and one skilled in the art may select the value of the current source I1 and the value of the clamping resistor R3 as needed to determine the value of the first voltage.
In one possible implementation, the current source I1 may be a constant current source outputting a constant current.
In one possible implementation, as shown in fig. 2a, the error amplifier EA may be set to be in a virtual short mode, and when the first switch S1 is turned on, the voltages at the two input ends of the EA are the same (approximately the same), and both the input voltages may be Vin, in this case, the voltage at the first end of the clamping resistor R3 is Vin + △ V, where △ V — I1 × R3.
In this case, the gate voltage of the first transistor Q1 is automatically adjusted (negatively fed back) by a small loop to ensure that the energy consumption of the first transistor Q1 is Q ═ Ilin*VDS＝Ilin*(Vin+ΔV-Vout) Wherein, IlinIndicates the inductor current at that time, VDSThe voltage difference between the source terminal and the drain terminal of the first transistor is shown, and those skilled in the art can select an appropriate Δ V voltage as required to adaptively meet the efficiency requirement of the system.
In one possible implementation, the outputting the clamp signal to the gate terminal of the first transistor Q1 may include:
outputting a first switch control signal to control the conducting state of the first switch S1 to output the clamping signal to the gate terminal of the first transistor Q1, wherein the first voltage is the voltage generated by the current source I1 across the clamping resistor R3, and the first switch control signal is the inverted signal of the PWM signal.
In one possible embodiment, the control module 30 may be further configured to:
in case that a difference between the output voltage and the input voltage is greater than a preset value, the PWM signal is output to the gate terminal of the first transistor Q1 and the gate terminal of the second transistor Q2.
In this case, the voltage regulator operates in the boost mode, and the first transistor Q1 and the second transistor Q2 are both controlled by the PWM signal, so as to achieve the function of modulating the output voltage Vout by different duty ratios.
In one possible implementation, as shown in fig. 2a, the control module 30 may include a mode switching sub-module 310, a control sub-module 320, and a duty cycle adjustment sub-module 330.
In a possible implementation manner, the input terminal of the mode switching sub-module 310 may be configured to receive the input voltage Vin and the output voltage Vout, the output terminal of the mode switching sub-module 310 is electrically connected to the first input terminal of the control sub-module 320, the second input terminal of the control sub-module 320 is electrically connected to the output terminal of the duty ratio adjustment sub-module 330, the input terminal of the duty ratio adjustment sub-module 330 may be configured to receive the feedback voltage Vfb of the output module 40, wherein,
the mode switching sub-module 310 may be configured to output a mode switching signal according to a magnitude relationship between the input voltage and the output voltage;
the duty ratio adjusting submodule 330 may be configured to adjust a duty ratio of a PWM signal according to the feedback voltage;
the control sub-module 320 may be configured to:
outputting a PWM signal to gates of the first transistor Q1 and the second transistor Q2 according to the mode switching signal; or
A PWM signal is output to the gate of the second transistor Q2 according to the mode switching signal, and the clamping signal is output to the gate of the first transistor Q1.
In one possible embodiment, the mode switching sub-module 310 may include a comparator, a subtractor, and the like, and may input a difference between the output voltage Vout and the preset voltage Vdif to a positive terminal of the comparator, input the input voltage Vin to a negative terminal of the comparator, and output a mode switching signal according to a magnitude relationship therebetween.
The present disclosure does not limit the specific value of the preset voltage Vdif, and a person skilled in the art can set the preset voltage Vdif as needed.
The present disclosure does not limit the specific implementation of the duty cycle control sub-module 330, and a person skilled in the art may determine the implementation of the duty cycle control sub-module 330 as needed as long as it can implement the control interface for the duty cycle according to the feedback signal Vfb.
Likewise, the present disclosure is not limited to the specific implementation of the control sub-module 320.
Of course, the control submodule 320 may output a PWM signal according to the duty ratio adjustment signal and may output a control signal of each switch, and therefore, the control submodule 320 may be integrated with a PWM logic controller or the like.
In one possible implementation, as shown in fig. 2a, the control module 30 may further include a switch sub-module electrically connected to the clamping module 20, the control sub-module 320, and the gate of the first transistor Q1, and the control module 30 may further be configured to:
the on-state of the switching sub-module is controlled according to the mode switching signal to output the clamp signal to the gate of the first transistor Q1 or the PWM signal to the gate of the first transistor Q1.
In one possible embodiment, the switch sub-module may include a second switch S2 and a third switch S3.
A first terminal of the second switch S2 is electrically connected to the control sub-module 320 for receiving the PWM signal, and a second terminal of the second switch S2 is electrically connected to the gate of the first transistor Q1.
A first terminal of the third switch S3 is electrically connected to the output terminal of the buffer unit for receiving the clamping signal, and a second terminal of the third switch S3 is electrically connected to the gate of the first transistor Q1.
In one example, the control sub-module 320 may output a switching signal to control the second switch S2 to be turned on and the third switch S3 to be turned off in the boost mode, thereby outputting the PWM signal to the gate of the first transistor Q1.
In one example, the control sub-module 320 may output a switching signal to control the second switch S2 to be turned off and the third switch S3 to be turned on in the diode mode, thereby outputting a clamping signal to the gate of the first transistor Q1.
In one possible implementation, as shown in fig. 2a, the output module 40 may include a first output resistor R1, a second output resistor R2, and an output capacitor Cout, wherein,
a first end of the first output resistor R1 is electrically connected to the source of the first transistor Q1 and the first end of the output capacitor Cout for outputting the output voltage Vout,
a second end of the first output resistor R1 is electrically connected to the first end of the second output resistor R2, and a second end of the second output resistor R2 and a second end of the output capacitor Cout are grounded.
In one possible implementation, the feedback signal Vfb may be the voltage of the second output resistor R2.
Of course, the above description of the output module 40 is exemplary and should not be construed as limiting the present disclosure, and in other embodiments, the output module 40 may have other implementations, and the present disclosure is not limited thereto.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating voltage adjustment by the voltage adjustment device.
As shown in fig. 3, in the boost mode (diode _ mode is low), the control submodule 320 may output a high level to turn on the second switch S2, output a low level to turn off the third switch S3, receive the PWM signal at the gates of the first transistor Q1 and the second transistor Q2, turn on the first transistor Q1 and the second transistor Q2 in turn under the control of the PWM signal, the gate voltage Pgate of the first transistor varies with the PWM signal, and the voltage signal at the connection point SW of the first transistor and the second transistor is as shown in fig. 3.
In the diode mode (diode _ mode is high level), the control submodule can output low levelThe second switch S2 is turned off, the third switch S3 is turned on by outputting a high level, the grid electrode of the first transistor Q1 receives the clamping signal, the grid electrode voltage of the first transistor Q1 is maintained at a fixed value, and the voltage signal of the connecting point SW of the first transistor and the second transistor is firstly rushed to Vin + Vth + Ilin/gmAnd then reaches a stable value where Vth represents the threshold voltage of the first transistor Q1, IlinIndicates the inductor current at this time, gmRepresenting the equivalent conductance value of the Q1 tube.
In the voltage regulator of the present disclosure, the voltage difference at the SW point is not sensitive to the current, and Vth itself has a threshold voltage point of 700mV or more, so long as Δ V < V is ensuredthThe efficiency of the present disclosure under various load conditions can be guaranteed to be better than that of the conventional architecture.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating an effect of voltage adjustment by the voltage adjustment device of the present disclosure.
As shown in fig. 4, the voltage regulation efficiency can be improved by 3% to 8% compared with the related art by using the voltage regulation device of the present disclosure to regulate the voltage under the same output current (0.04mA to 1 mA).
Therefore, when the device works in the diode mode, the voltage of the SW point tends to a stable value, and compared with the SW point which changes along with the current in the related art, the power consumption can be reduced, and the efficiency of voltage adjustment is improved. Further, since the voltage at the connection point SW between the first transistor Q1 and the second transistor Q2 does not vary with the current, the device does not generate a large amount of heat when adjusting the voltage, and the device can be put in a stable state.
The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A voltage regulation device is characterized in that the device comprises an input module, a clamping module, a first transistor, a second transistor, a control module and an output module, wherein:
a first end of the input module is electrically connected to the first input end of the clamping module for receiving an input voltage, a second end of the input module is electrically connected to the second input end of the clamping module, the drain end of the second transistor and the drain end of the first transistor,
the grid end of the first transistor and the grid end of the second transistor are electrically connected with the control module, the source end of the first transistor is electrically connected with the output module, the source end of the second transistor is grounded,
the output end of the clamping module is electrically connected with the control module and used for outputting a clamping signal,
the control module is electrically connected to the first end of the input module and the output module, and is configured to:
and under the condition that the difference value between the output voltage output by the output module and the input voltage is less than or equal to a preset value, outputting a Pulse Width Modulation (PWM) signal to the grid terminal of the second transistor, outputting the clamping signal to the grid terminal of the first transistor, and clamping the voltages of the grid terminals of the first transistor and the second transistor to a first voltage.
2. The apparatus of claim 1, wherein the clamping module comprises a clamping resistor, a current source, a first switch, a first capacitor, an error amplifier, and a buffer unit, wherein:
a first end of the clamping resistor is electrically connected to the second end of the input module, the gate terminal of the first transistor and the gate terminal of the second transistor, a second end of the clamping resistor is electrically connected to the positive terminal of the current source and the first end of the first switch,
the negative terminal of the current source is grounded,
the second end of the first switch is connected to the first end of the first capacitor and the negative electrode end of the error amplifier, the control end of the first switch is electrically connected to the control module,
the second terminal of the first capacitor is grounded,
the output end of the error amplifier is electrically connected with the input end of the buffer unit,
the output end of the buffer unit is electrically connected with the control module,
wherein the buffer unit includes a voltage follower.
3. The apparatus of claim 2, wherein the outputting the clamp signal to a gate terminal of the first transistor comprises:
outputting a first switch control signal to control a conduction state of the first switch to output the clamp signal to a gate terminal of the first transistor,
the first voltage is a voltage generated by the current source on the clamping resistor, and the first switch control signal is an inverted signal of the PWM signal.
4. The apparatus of claim 2 or 3, wherein the control module is further configured to:
and under the condition that the difference value between the output voltage and the input voltage is greater than a preset value, outputting the PWM signal to the grid terminal of the first transistor and the grid terminal of the second transistor.
5. The apparatus of claim 1, wherein the control module comprises a mode switching sub-module, a control sub-module, and a duty cycle adjustment sub-module, an input of the mode switching sub-module is configured to receive the input voltage and the output voltage, an output of the mode switching sub-module is electrically connected to a first input of the control sub-module, a second input of the control sub-module is electrically connected to an output of the duty cycle adjustment sub-module, an input of the duty cycle adjustment sub-module is configured to receive a feedback voltage of the output module, wherein,
the mode switching submodule is used for outputting a mode switching signal according to the magnitude relation of the input voltage and the output voltage;
the duty ratio adjusting submodule is used for adjusting the duty ratio of the PWM signal according to the feedback voltage;
the control sub-module is configured to:
outputting a PWM signal to gates of the first transistor and the second transistor according to the mode switching signal; or
Outputting a PWM signal to a gate of the second transistor and outputting the clamp signal to a gate of the first transistor according to the mode switching signal.
6. The apparatus of claim 5, wherein the control module further comprises a switch sub-module electrically connected to the clamping module, the control module, and the gate of the first transistor, the control module further configured to:
and controlling the conduction state of the switch submodule according to the mode switching signal so as to output the clamping signal to the grid electrode of the first transistor or output the PWM signal to the grid electrode of the first transistor.
7. The apparatus of claim 1, wherein the input module comprises an inductor and the output module comprises a first output resistor, a second output resistor, and an output capacitor,
the first end of the first output resistor is electrically connected to the source of the first transistor and the first end of the output capacitor for outputting the output voltage,
the second end of the first output resistor is electrically connected to the first end of the second output resistor,
the second end of the second output resistor and the second end of the output capacitor are grounded.
8. A chip, wherein the chip comprises:
a voltage regulation device as claimed in any one of claims 1 to 7.
9. An electronic device, characterized in that the electronic device comprises:
the chip of claim 8.
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| CN201921625443.4U CN210402135U (en) | 2019-09-26 | 2019-09-26 | Voltage adjusting device, chip and electronic equipment |
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| CN201921625443.4U CN210402135U (en) | 2019-09-26 | 2019-09-26 | Voltage adjusting device, chip and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110597344A (en) * | 2019-09-26 | 2019-12-20 | 北京集创北方科技股份有限公司 | Voltage adjusting device, chip and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110597344A (en) * | 2019-09-26 | 2019-12-20 | 北京集创北方科技股份有限公司 | Voltage adjusting device, chip and electronic equipment |
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