CN210380682U - Secondary side synchronous rectification controller circuit capable of self-adapting to drive voltage adjustment cycle by cycle - Google Patents
Secondary side synchronous rectification controller circuit capable of self-adapting to drive voltage adjustment cycle by cycle Download PDFInfo
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Abstract
The utility model discloses a secondary limit synchronous rectification controller circuit of cycle-by-cycle self-adaptation driving voltage adjustment mainly is applied to among the switching power supply system of flyback type. The cycle-by-cycle timing module records the time of each switching cycle, and automatically estimates the starting time node of the first MOS tube in the next cycle according to the average time and the variation trend of the previous N cycles, so that the second MOS tube on the secondary side is accurately switched off before the first MOS tube is started; before the loop current of the secondary side is reduced to zero or the first MOS tube is conducted, the self-adaptive driving voltage adjusting module is used for reducing the amplitude of the driving voltage, and then the second MOS tube is quickly turned off, so that the risk that the primary side and the secondary side are conducted simultaneously can not be generated no matter what working mode the flyback switching power supply system is in, and meanwhile, the conversion efficiency of the system is improved to the maximum extent.
Description
Technical Field
The utility model relates to a secondary limit synchronous rectification circuit field of AC-DC, concretely relates to secondary limit synchronous rectification controller circuit of cycle-by-cycle self-adaptation driving voltage adjustment.
Background
At present, flyback AC-DC is widely applied to the field of low-power chargers and adapters. With the increase of battery capacity of handheld devices and the increase of complexity of electric devices, chargers and adapters with low power consumption and high power density become mainstream gradually, and the problem of heat dissipation becomes an urgent issue to be solved.
The existing synchronous rectification circuit can only be matched with one or more primary side controller architectures, and has the following modes: the first one is to use a zero current comparator to realize DCM and QR mode synchronous rectification, and the working block diagram is shown in fig. 1, the zero current comparator directly samples the voltage at two ends of the MOS transistor, and when the voltage (equivalent to loop current) on the MOS transistor gradually decreases to be close to about-15 mV, the MOS transistor is turned off, which is not the real zero current comparison, but the disadvantage is that the zero current comparator can only be used in DCM and QR flyback structures, and can not be applied to a primary side controller with a CCM working mode; the second method is to use an area method to realize DCM synchronous rectification, and a working block diagram is shown in fig. 2, which has the disadvantages that the method can only work in a controller architecture of a DCM mode, and cannot be applied to other types of primary side controller architectures, and due to the primary side DCM controller architecture, only the application with an output power section smaller than 15W can be satisfied, and meanwhile, different transformer and controller structures need to be peripherally arranged and matched in application, so that a user experience effect is poor; the third one is to use voltage waveform detection to realize the synchronous rectification of DCM, CCM, QR, the working block diagram is shown in fig. 3, the structure pre-judges the action of the primary side controller by detecting the voltage waveform of the Drain end of the MOS transistor, because the MOS transistor has a larger junction capacitance, the miller platform effect, the signal transmission delay of the synchronous rectification and other factors, the total delay time of the system has a certain discrete type, and the actual action time and the logic interpretation time have a longer delay, the moment when the primary side power MOS transistor and the secondary side power MOS transistor are simultaneously conducted exists in the heavy load or load dynamic change environment, the energy stored in the transformer can be released at the moment, and simultaneously, a higher flyback voltage spike voltage can be generated on the synchronously rectified MOS transistor, and the high voltage spike can easily break down the MOS transistor, resulting in the failure of the whole system.
SUMMERY OF THE UTILITY MODEL
To the shortcoming of above-mentioned prior art, the utility model provides a secondary limit synchronous rectification controller circuit of cycle-by-cycle self-adaptation driving voltage adjustment can effectively promote system conversion efficiency, reduces electrical power generating system's heat loss to can match all former limit controller frameworks, including control mode such as interrupted mode (DCM) quasi-resonance mode (QR), continuous mode (CCM), have more extensive suitability, possess characteristics such as high efficiency, high reliability, low-cost.
The purpose of the utility model and the technical problem thereof can be realized by adopting the following technical scheme.
According to the utility model provides a secondary side synchronous rectification controller circuit of cycle-by-cycle self-adaptation driving voltage adjustment, including primary controller, first MOS pipe, transformer, second MOS pipe, self-adaptation driving voltage adjustment module, cycle-by-cycle timing module, reference voltage module and output capacitance; the primary controller is connected with the first MOS tube, the first MOS tube is connected with the primary side of the transformer, the second MOS tube is connected between the low end of the secondary side of the transformer and an output ground end, the Drain end of the second MOS tube is connected with the low end of the secondary side of the transformer, and the Source end of the second MOS tube is connected with the ground end of the output end of the secondary side of the transformer; the output capacitor is connected between the Vout end of the output end of the secondary side of the transformer and the ground end; the input end of the self-adaptive driving voltage adjusting module is respectively connected with a Drain end of the second MOS tube, the output end of the cycle-by-cycle timing module and the output end of the reference voltage module, and the output end of the self-adaptive driving voltage adjusting module is connected with a Gate end of the second MOS tube; and the input end of the cycle-by-cycle timing module is connected with the Drain end of the second MOS tube.
The self-adaptive driving voltage adjusting module comprises a VDS feedback voltage detecting circuit, a sample-and-hold circuit, a threshold voltage selecting circuit, a driving voltage adjusting circuit and a driving circuit; the VDS feedback voltage detection circuit detects the voltage difference between a Drain end and a Source end after the second MOS tube is started, and feeds a voltage difference voltage signal between the Drain end and the Source end back to the driving voltage regulation circuit; the sampling and holding circuit is used for latching and holding the voltage difference between the Drain end and the Source end of the second MOS tube when an OE effective signal arrives; the threshold voltage selection circuit is used for selecting the reference voltage module to input reference voltage for the driving voltage regulation circuit before an OE effective signal arrives, and the reference voltage value is-30 mV; the threshold voltage selection circuit is used for selecting the voltage difference between the Drain end and the Source end of the second MOS transistor latched by the sampling and holding circuit in real time as the input voltage of the driving voltage regulation circuit when an OE effective signal is effective; the driving voltage regulating circuit regulates the amplitude of the output voltage; the driving circuit converts the input voltage signal into a signal capable of driving the second MOS tube to be turned on and turned off.
The cycle-by-cycle timing module comprises a current cycle counter circuit, a first N cycle counter cache circuits, a current cycle second MOS tube starting time detection circuit, a primary side next cycle first MOS tube starting time estimation circuit and a self-adaptive driving time calculation circuit.
The first N periods of the first MOS tube on-off time is recorded by the first N period counter cache circuits, and the first MOS tube on-off time estimation circuit at the next period of the primary side calculates the next on-off time of the first MOS tube according to the average time and the variation trend of the previous N periods; the self-adaptive driving time calculation circuit calculates the starting time of the second MOS tube, and starts to count down from the effective signal given by the second MOS tube starting time detection circuit in the current period, an OE signal is given to the self-adaptive driving voltage adjustment module when the counting down of the second MOS tube starting time is finished, the time difference from the effective OE signal to the starting of the first MOS tube is kept between 0.3us and 2us, and the self-adaptive driving voltage adjustment module automatically adjusts the driving voltage in the time period from 0.3us to 2us and finishes the switching-off action of the second MOS tube before the first MOS tube is started.
The self-adaptive driving voltage adjusting module receives a voltage signal of a Drain end of the second MOS transistor, a timing signal of the cycle-by-cycle timing module and a signal of the reference voltage module; before the timing signal of the cycle-by-cycle timing module reaches and the VDS voltage of the second MOS tube is equal to the reference voltage value, the voltage value given by the reference voltage module is adopted to carry out feedback adjustment of the self-adaptive driving voltage; and when the timing signal of the cycle-by-cycle timing module arrives and the self-adaptive driving voltage adjusting stage is not entered, the VDS voltage is adopted to carry out feedback adjustment on the self-adaptive driving voltage.
By the technical scheme, the utility model provides a secondary limit synchronous rectification controller circuit of cycle-by-cycle self-adaptation driving voltage adjustment. The method can widely support various primary side control architectures such as DCM, QR, CCM and the like. In the application of the DCM and QR controller architecture on the primary side, the stored energy of the transformer can be completely released to the secondary side of the transformer before the first MOS tube on the primary side is turned on each time, the current of the secondary side is reduced to zero when the second MOS tube is turned off, and the VDS of the second MOS tube is correspondingly reduced to zero, so that the output of the reference voltage module is selected by the threshold voltage selection circuit as the input of the driving voltage regulation circuit, and the self-adaptive driving voltage regulation function is realized; in the application of the CCM controller architecture, the energy stored in the transformer before the first MOS tube on the primary side is switched on each time is not completely released to the secondary side of the transformer, the current on the secondary side is not reduced to zero when the second MOS tube is switched off, the VDS voltage of the second MOS tube at the moment is still larger, and the VDS voltage value depends on the degree of the energy release stored in the transformer, so that the threshold voltage selection circuit selects a signal latched by the sampling and holding circuit when an OE signal is effective to be used as the input of the driving voltage regulation circuit, and the function of self-adaptive driving voltage regulation is also realized.
Drawings
Fig. 1-3 are schematic diagrams of exemplary synchronous rectification controller circuits.
Fig. 4 is a schematic structural diagram of a secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment according to the present invention.
Fig. 5 is a block diagram of an adaptive driving voltage adjusting module of a secondary side synchronous rectification controller circuit for adjusting a cycle-by-cycle adaptive driving voltage according to the present invention.
Fig. 6 is a block diagram of a cycle-by-cycle timing module of a secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment according to the present invention.
Fig. 7 is a timing diagram of the driving waveform of the secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment in CCM mode according to the present invention.
Fig. 8 is a timing diagram of driving waveforms of the secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment in DCM and QR modes.
Detailed Description
To further illustrate the secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment of the present invention, the following detailed description will be made on the specific implementation, structure, features and effects of the secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment according to the present invention, with reference to the accompanying drawings and preferred embodiments, in order to achieve the technical means and the effects achieved by the same.
Fig. 1 to 3 are schematic structural diagrams of exemplary synchronous rectification controller circuits.
In fig. 1, in order to implement DCM and QR mode synchronous rectification by using a zero current comparator, the zero current comparator directly samples voltages at two ends of an MOS transistor, and turns off the MOS transistor when the voltage (equivalent to a loop current) on the MOS transistor gradually decreases to approximately-15 mV, which is not a true zero current comparison, but has a disadvantage that the zero current comparator can only be used in DCM and QR flyback structures, and cannot be applied to a primary side controller having a CCM operation mode.
In fig. 2, in order to implement DCM synchronous rectification by using an area method, the method has a disadvantage that the method can only work in a controller architecture of a DCM mode, and cannot be applied to other types of primary side controller architectures, and due to the primary side DCM controller architecture, the method can only meet the application that the output power section is less than 15W, and meanwhile, different transformer and controller structures need to be peripherally arranged and matched in application, and the user experience effect is poor.
In fig. 3, in order to implement the synchronous rectification of DCM, CCM, and QR by applying voltage waveform detection, the structure pre-determines the action of the primary side controller by detecting the voltage waveform of the Drain end of the MOS transistor, because the MOS transistor has a large junction capacitance, the miller platform effect, the signal transmission delay of the synchronous rectification, and other factors, the total delay time of the system will be a certain discrete type, and the actual action time and the logic interpretation time will have a long delay, and at the moment when the primary side power MOS transistor and the secondary side power MOS transistor are simultaneously turned on in the heavy load or load dynamic change environment, the energy stored in the transformer will be released at this moment, and at the same time, a relatively high flyback voltage spike voltage will be generated on the synchronously rectified MOS transistor, and the high voltage spike will break down the MOS transistor easily, resulting in the failure of the whole system.
Referring to fig. 4 to 8, fig. 4 is a schematic structural diagram of a secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment according to the present invention; fig. 5 is an internal block diagram of the adaptive driving voltage adjusting module according to the present invention; fig. 6 is an internal block diagram of a cycle-by-cycle timing module according to the present invention; fig. 7 is a schematic diagram of waveforms and timing sequences of the secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment in CCM mode according to the present invention; fig. 8 is a schematic diagram of waveforms and timings of the secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment in DCM and QR modes according to the present invention.
In fig. 4, the present invention discloses a secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment, which comprises a primary controller, a first MOS transistor, a transformer, a second MOS transistor, an adaptive driving voltage adjustment module, a cycle-by-cycle timing module, a reference voltage module and an output capacitor; the primary controller is connected with the first MOS tube, the first MOS tube is connected with the primary side of the transformer, the second MOS tube is connected between the low end of the secondary side of the transformer and an output ground end, the Drain end of the second MOS tube is connected with the low end of the secondary side of the transformer, and the Source end of the second MOS tube is connected with the ground end of the output end of the secondary side of the transformer; the output capacitor is connected between the Vout end of the output end of the secondary side of the transformer and the ground end; the input end of the self-adaptive driving voltage adjusting module is respectively connected with a Drain end of the second MOS tube, the output end of the cycle-by-cycle timing module and the output end of the reference voltage module, and the output end of the self-adaptive driving voltage adjusting module is connected with a Gate end of the second MOS tube; and the input end of the cycle-by-cycle timing module is connected with the Drain end of the second MOS tube.
In an embodiment, the adaptive driving voltage adjustment module adjusts the driving voltage of the second MOS transistor, and an internal block diagram of the adaptive driving voltage adjustment module is shown in fig. 5, where the adaptive driving voltage adjustment module includes a VDS feedback voltage detection circuit, a sample-and-hold circuit, a threshold voltage selection circuit, a driving voltage adjustment circuit, and a driving circuit; the VDS feedback voltage detection circuit detects the voltage difference between a Drain end and a Source end after the second MOS tube is started, and feeds a voltage difference voltage signal between the Drain end and the Source end back to the driving voltage regulation circuit; the sampling and holding circuit is used for latching and holding the voltage difference between the Drain end and the Source end of the second MOS tube when an OE effective signal arrives; the threshold voltage selection circuit is used for selecting the reference voltage module to input reference voltage for the driving voltage regulation circuit before an OE effective signal arrives, and the reference voltage value is-30 mV; the threshold voltage selection circuit is used for selecting the voltage difference between the Drain end and the Source end of the second MOS transistor latched by the sampling and holding circuit in real time as the input voltage of the driving voltage regulation circuit when an OE effective signal is effective; the driving voltage regulating circuit regulates the amplitude of the output voltage; the driving circuit converts the input voltage signal into a signal capable of driving the second MOS tube to be turned on and turned off.
The VDS feedback voltage detection circuit sends a VDS voltage signal detected in real time to the driving voltage regulation circuit, the threshold voltage selection circuit sends a required voltage signal to the driving voltage regulation circuit, and the driving circuit receives an output signal of the driving voltage regulation circuit and drives the second MOS tube to perform switching and adjusting actions.
In one embodiment, the driving voltage regulating circuit, the driving circuit, the second MOS transistor and the VDS feedback voltage detecting circuit together form a negative feedback loop; after the first MOS transistor is turned off, the energy stored in the transformer is released through the secondary side, and before the second MOS transistor is not turned on, a current loop is formed through a body diode of the second MOS transistor, as shown in fig. 7 and 8, when the VDS voltage of the second MOS transistor reaches VON (typically-0.7V), the second MOS transistor is turned on, the second MOS transistor is completely turned on at time T1, the VDS voltage amplitude is reduced, at this time, the driving voltage of the second MOS transistor is the internal power voltage, and as the energy of the transformer is released, the current flowing through the second MOS transistor is gradually reduced, and the VDS voltage amplitude is also reduced; due to the adjustment of the negative feedback loop and the gradual decrease of the loop current, as depicted by the waveform at time T2 in fig. 7, when the VDS voltage of the second MOS transistor gradually decreases to be the same as the given reference input voltage, the loop automatically decreases the driving voltage so that the second MOS transistor enters the saturation region to maintain VDS substantially constant, as in the VREG voltage plateau region in the figure; when the loop current is further reduced, the VDS voltage amplitude approaches zero voltage, at the moment, the negative feedback loop can pull down the output voltage of the driving voltage regulating circuit, and the driving voltage regulating circuit switches off the second MOS tube.
The sampling holding circuit receives a VDS voltage signal output by the VDS feedback voltage detection circuit, latches the VDS voltage at the moment when an OE effective signal arrives, and sends the VDS voltage to the threshold voltage selection circuit; before the threshold voltage selection circuit receives an OE effective signal, a signal given by the selection reference voltage module is output to the driving voltage regulation circuit, and when the OE signal becomes effective, the threshold voltage selection circuit selects the VDS voltage latched by the sampling and holding circuit to output to the driving voltage regulation circuit.
In an embodiment, as shown in fig. 6, the cycle-by-cycle timing module includes a current cycle counter circuit, a first N cycle counter buffer circuit, a current cycle second MOS transistor turn-on time detection circuit, a primary side next cycle first MOS transistor turn-on time estimation circuit, and an adaptive driving time calculation circuit; the first N periods of the first MOS tube on-off time is recorded by the first N period counter cache circuit, and the first MOS tube on-off time estimation circuit of the next period of the primary side calculates the next on-off time of the first MOS tube according to the average time and the variation trend of the previous N periods; the self-adaptive driving time calculation circuit calculates the starting time of the second MOS tube, and starts to count down from the effective signal given by the second MOS tube starting time detection circuit in the current period, an OE signal is given to the self-adaptive driving voltage adjustment module when the counting down of the second MOS tube starting time is finished, the time difference from the effective OE signal to the starting of the first MOS tube is kept between 0.3us and 2us, and the self-adaptive driving voltage adjustment module automatically adjusts the driving voltage in the time period from 0.3us to 2us and finishes the switching-off action of the second MOS tube before the first MOS tube is started.
The current period counter records the switching period of the current period, the opening time and the closing time of the first MOS tube and the second MOS tube; the first N period counter cache modules record time information of the first N switching periods of the period; the self-adaptive driving time calculation circuit receives the starting time of the second MOS tube in the current period and the signal of the pre-estimation circuit of the starting time of the first MOS tube in the next period on the primary side, automatically calculates the self-adaptive driving voltage adjusting time of the second MOS tube, gives an indication signal from 0.3uS to 2uS (a typical value of 0.7uS) before the first MOS tube is started, and finishes the actions of adjusting the driving voltage and turning off the second MOS tube by the self-adaptive driving voltage adjusting circuit.
In one embodiment, as shown in fig. 7, when the primary side operates in the CCM mode, the cycle-by-cycle timing module estimates the variation trend and the turn-on time of the next cycle according to the average value and the variation trend of the switching time information of the previous N cycles, and gives the indication signal OE 0.3uS to 2uS (typical value 0.7uS) in advance. As shown in fig. 7, waveforms at times T2-T3, T5-T6; when the primary side operates in DCM and QR modes, as shown in fig. 8, the adaptive driving voltage regulation phases are T2 'to T3 times and T5' to T6 times. Wherein, M1 represents the first MOS transistor, and M2 represents the second MOS transistor.
In an embodiment, if the OE valid signal arrives and the VDS voltage of the second MOS transistor has not dropped to the preset value given by the reference voltage module, the threshold voltage selection circuit module selects the signal held by the sample-and-hold circuit at this time as the reference signal to output, and at this time, the VDS voltage of the second MOS transistor is maintained at the voltage signal amplitude of the sample-and-hold circuit by the negative feedback loop, where waveforms at times T2 to T3 and times T5 to T6 are shown in fig. 7; if the voltage of the VDS of the second MOS transistor has dropped to the voltage amplitude given by the reference voltage module when the OE valid signal arrives, the voltage of the VDS of the second MOS transistor will be maintained at the voltage amplitude given by the reference voltage module by the negative feedback circuit, as shown in waveforms T2 'to T3 and T5' to T6 in fig. 8.
The secondary side synchronous rectification controller with the cycle self-using driving voltage has the advantages that the function of the secondary side synchronous rectification controller with the cycle self-using driving voltage is realized, almost all primary side controller structures can be met through the cycle-by-cycle timing prejudgment and the self-adaptive driving voltage adjustment, and the negative feedback turn-off mode has wide applicability.
The utility model provides a secondary side synchronous rectification controller circuit with cycle-by-cycle self-adaptive driving voltage adjustment, wherein a self-adaptive driving voltage adjustment module automatically adjusts the driving voltage of a second MOS tube; the cycle-by-cycle timing module records the time information of each switching cycle, the starting time of the first MOS tube is automatically estimated by using the average value and the variation trend of the previous N cycles, the adaptive driving voltage regulation indicating signal of the second MOS tube in the current cycle is given out by advancing 0.3uS to 2uS (the typical value is 0.7uS), and the negative feedback loop automatically turns off the second MOS tube when the loop current is reduced and the VDS voltage amplitude is reduced to be lower than the preset reference input amplitude. The turn-off time of the second MOS tube can be pre-judged through cycle-by-cycle detection and drive regulation, the problem of full compatibility of working modes of different primary controllers of DCM, QR and CCM is solved, and the risk that a primary side and a secondary side are possibly conducted and damage a power supply system is effectively avoided.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above description, and although the present invention has been disclosed with the preferred embodiment, it is not limited to the present invention, and any skilled person in the art can make some modifications or equivalent variations within the technical scope of the present invention without departing from the technical scope of the present invention.
Claims (5)
1. The secondary side synchronous rectification controller circuit is characterized by comprising a primary controller, a first MOS (metal oxide semiconductor) tube, a transformer, a second MOS tube, a self-adaptive driving voltage adjusting module, a cycle-by-cycle timing module, a reference voltage module and an output capacitor; the primary controller is connected with the first MOS tube, the first MOS tube is connected with the primary side of the transformer, the second MOS tube is connected between the low end of the secondary side of the transformer and an output ground end, the Drain end of the second MOS tube is connected with the low end of the secondary side of the transformer, and the Source end of the second MOS tube is connected with the ground end of the output end of the secondary side of the transformer; the output capacitor is connected between the Vout end of the output end of the secondary side of the transformer and the ground end; the input end of the self-adaptive driving voltage adjusting module is respectively connected with a Drain end of the second MOS tube, the output end of the cycle-by-cycle timing module and the output end of the reference voltage module, and the output end of the self-adaptive driving voltage adjusting module is connected with a Gate end of the second MOS tube; and the input end of the cycle-by-cycle timing module is connected with the Drain end of the second MOS tube.
2. The cycle-by-cycle adaptive drive voltage adjusted secondary side synchronous rectification controller circuit of claim 1, wherein the adaptive drive voltage adjustment module comprises a VDS feedback voltage detection circuit, a sample-and-hold circuit, a threshold voltage selection circuit, a drive voltage regulation circuit and a drive circuit; the VDS feedback voltage detection circuit detects the voltage difference between a Drain end and a Source end after the second MOS tube is started, and feeds a voltage difference voltage signal between the Drain end and the Source end back to the driving voltage regulation circuit; the sampling and holding circuit is used for latching and holding the voltage difference between the Drain end and the Source end of the second MOS tube when an OE effective signal arrives; the threshold voltage selection circuit is used for selecting the reference voltage module to input reference voltage for the driving voltage regulation circuit before an OE effective signal arrives, and the reference voltage value is-30 mV; the threshold voltage selection circuit is used for selecting the voltage difference between the Drain end and the Source end of the second MOS transistor latched by the sampling and holding circuit in real time as the input voltage of the driving voltage regulation circuit when an OE effective signal is effective; the driving voltage regulating circuit regulates the amplitude of the output voltage; the driving circuit converts the input voltage signal into a signal capable of driving the second MOS tube to be turned on and turned off.
3. The secondary side synchronous rectification controller circuit for cycle-by-cycle adaptive driving voltage adjustment according to claim 1, wherein the cycle-by-cycle timing module comprises a current cycle counter circuit, a first N cycle counter buffer circuit, a current cycle second MOS transistor turn-on time detection circuit, a primary side next cycle first MOS transistor turn-on time estimation circuit and an adaptive driving time calculation circuit.
4. The secondary side synchronous rectification controller circuit with cycle-by-cycle adaptive drive voltage adjustment according to claim 3, wherein the first N cycle counter buffer circuits record the turn-on and turn-off times of the first MOS transistor of the previous N cycles, and the primary side next cycle first MOS transistor turn-on time estimation circuit calculates the next turn-on time of the first MOS transistor according to the average time and the variation trend of the previous N cycles; the self-adaptive driving time calculation circuit calculates the starting time of the second MOS tube, and starts to count down from an effective signal given by the second MOS tube starting time detection circuit in the current period, an OE signal is given to the self-adaptive driving voltage adjustment module when the counting down of the second MOS tube starting time is finished, the time difference from the effective OE signal to the starting of the first MOS tube is kept between 0.3us and 2us, and the self-adaptive driving voltage adjustment module automatically adjusts the driving voltage in the time period from 0.3us to 2us and finishes the switching-off action of the second MOS tube before the first MOS tube is started.
5. The secondary side synchronous rectification controller circuit with cycle-by-cycle adaptive driving voltage adjustment according to claim 1, wherein the adaptive driving voltage adjustment module receives a voltage signal at a Drain end of the second MOS transistor, a timing signal of the cycle-by-cycle timing module and a signal of the reference voltage module; before the timing signal of the cycle-by-cycle timing module reaches and the VDS voltage of the second MOS tube is equal to the reference voltage value, the voltage value given by the reference voltage module is adopted to carry out feedback adjustment of the self-adaptive driving voltage; and when the timing signal of the cycle-by-cycle timing module arrives and the self-adaptive driving voltage adjusting stage is not entered, the VDS voltage is adopted to carry out feedback adjustment on the self-adaptive driving voltage.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224619A (en) * | 2019-06-13 | 2019-09-10 | 无锡猎金半导体有限公司 | Secondary side synchronous rectification controller circuit capable of self-adapting to drive voltage adjustment cycle by cycle |
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Cited By (2)
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|---|---|---|---|---|
| CN110224619A (en) * | 2019-06-13 | 2019-09-10 | 无锡猎金半导体有限公司 | Secondary side synchronous rectification controller circuit capable of self-adapting to drive voltage adjustment cycle by cycle |
| CN110224619B (en) * | 2019-06-13 | 2024-06-04 | 江苏芯潭微电子有限公司 | Secondary side synchronous rectification controller circuit capable of adaptively driving voltage adjustment cycle by cycle |
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Address after: 214115 c1-6f, China Sensor Network International Innovation Park, 200 Linghu Avenue, Wuxi City, Jiangsu Province Patentee after: Jiangsu Xintan Microelectronics Co.,Ltd. Address before: 214135 b340, China Sensor Network International Innovation Park, 200 Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province Patentee before: WUXI LIEJIN SEMICONDUCTOR CO.,LTD. |
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