CN210351379U

CN210351379U - Discretization-free multi-screen splicing image processor

Info

Publication number: CN210351379U
Application number: CN201921723195.7U
Authority: CN
Inventors: 牛立国
Original assignee: Shenzhen Flowvia Technology Co ltd
Current assignee: Shenzhen Flowvia Technology Co ltd
Priority date: 2019-10-15
Filing date: 2019-10-15
Publication date: 2020-04-17
Anticipated expiration: 2029-10-15

Abstract

The utility model discloses a discretization-free multi-screen splicing image processor, which comprises a lower panel, a front panel, a left panel, a partition board A, a partition board B, a right panel, an upper panel and a rear panel, wherein the front panel and the rear panel are respectively arranged at the front and the rear of the upper part of the lower panel, the left panel, the partition board A, the partition board B and the right panel are sequentially arranged above the lower panel from left to right, the lower panel, the front panel, the left panel, the partition board A, the upper panel and the rear panel surround to form a heat dissipation cavity, the lower panel, the front panel, the partition board A, the partition board B, the upper panel and the rear panel surround to form a data processing cavity, the lower panel, the front panel, the partition board B, the right panel, the upper panel and the rear panel surround to form a power supply cavity, the hardware architecture design of the utility model adopts an FPGA architecture, no operating system, high starting speed and good heat dissipation effect, the operation is stable, and the long-time continuous operation is supported.

Description

Discretization-free multi-screen splicing image processor

Technical Field

The utility model relates to an image processor technical field specifically is a no discretization concatenation image processor of shielding more.

Background

The video splicing controller is a professional video processing and controlling device, and mainly has the functions of dividing a video signal into a plurality of display units, outputting the divided display unit signals to a plurality of display terminals, the method is characterized in that a plurality of display screens are spliced to form a complete image, the processing process is completely hardware, operations such as a computer and starting software are not needed, the method is very simple and convenient, a splicing controller is designed by adopting a pure hardware structure, no operating system is provided, the whole system runs in a completely closed mode, operations such as the computer and the starting software are not needed, the stability is greatly higher than that of a computer + board card mode based on a WINDOWS operating system and a traditional controller designed by an embedded system, the most advanced high-speed video processing chip in the world at present is adopted, and a plurality of paths of video VGA images are processed in real time by applying an advanced digital image processing algorithm, namely, the compressed images are displayed on a projector.

At present, different functional requirements cannot be met conveniently and quickly, the product has high failure rate, high maintenance time and cost, low starting speed, low stability, incapability of supporting long-time continuous operation and incapability of meeting the application requirements of various monitoring machine rooms, and the trouble of frequent halt, blue screen and virus appears. Poor heat dissipation effect and unstable operation.

The multi-screen splicing image processor is improved aiming at the defects of the existing device, and the non-discretization multi-screen splicing image processor is provided.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a do not have many screen splicing image processor of discretization to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme:

the utility model provides a many screen splicing image processor of no discretization, includes panel, front panel, left panel, division board A, division board B, right panel, top panel and rear panel down, panel top front and back do not is provided with front panel, rear panel, panel top left panel, division board A, division board B, right panel are installed in proper order from the left hand right side down, panel, front panel, left panel, division board A, top panel and rear panel surround down and form the heat dissipation chamber, panel, front panel, division board A, division board B, top panel and rear panel surround down and form the data processing chamber, panel, front panel, division board B, right panel, top panel and rear panel surround down and form the power supply chamber.

As a further aspect of the present invention: a plurality of supporting columns are installed on the lower end face of the lower panel, and buffer layers are arranged at the lower ends of the supporting columns.

As a further aspect of the present invention: the front panel is provided with a power interface and a switch button, and the front panel is provided with a plurality of uniformly distributed radiating net ports.

As a further aspect of the present invention: and two cooling fans are arranged on the left panel and are symmetrically arranged about the center line of the left panel.

As a further aspect of the present invention: the utility model discloses a data processing device, including data processing chamber, CPU, input integrated circuit board, output integrated circuit board all are provided with the several, input integrated circuit board, output integrated circuit board include HDMI integrated circuit board, DVI integrated circuit board, VGA integrated circuit board, CPU handles the integrated circuit board and includes the IP function of decoding, supports 4K video signal.

As a further aspect of the present invention: the switching power supply and the wire passing hole are arranged in the power supply cavity, the switching power supply is electrically connected with the power supply interface, and the switching power supply is electrically connected with the CPU processing board card, the input board card, the output board card and the cooling fan through the wire passing hole.

As a further aspect of the present invention: and a plurality of heat dissipation holes are formed in the partition board A, the partition board B and the right panel.

Compared with the prior art, the beneficial effects of the utility model are that: the CPU processing board card comprises an IP decoding function and supports 4K video signals, and the HDMI board card, the DVI board card and the VGA board card are respectively made into independent modules and assembled in a card inserting mode. Different quantity of cartridge, different kind module card, but convenient and fast ground satisfies different functional demands, greatly reduced the fault rate of product, practiced thrift maintenance duration and cost of maintenance, reduced the maintenance cost, the utility model discloses a hardware architecture design adopts the FPGA framework, and no operating system, the start-up rate is fast, and the radiating effect is good, and the operation is stable, supports long-time continuous operation, the utility model discloses every way signal all can realize striding polylith display screen to show, can enlarge to whole full screen display the most.

Drawings

Fig. 1 is a schematic axial side structure of the prior art.

Fig. 2 is a schematic diagram of the axial side structure of the present invention.

Fig. 3 is a schematic front view of the structure of the present invention.

Fig. 4 is a schematic side view of the present invention.

Wherein: the heat dissipation device comprises a lower panel 1, a support column 101, a front panel 2, a power interface 201, a switch button 202, a left panel 3, a heat dissipation fan 301, an isolation plate A4, an isolation plate B5, a right panel 6, an upper panel 7, a rear panel 8, a heat dissipation cavity 9, a data processing cavity 10, a CPU processing board 1001, an input board 1002, an output board 1003, a power cavity 11, a switch power 1101 and a wire passing hole 1102.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Example 1

Referring to fig. 1-4, in an embodiment of the present invention, a discretization-free multi-screen splicing image processor includes a lower panel 1, a front panel 2, a left panel 3, a partition a4, a partition B5, a right panel 6, an upper panel 7, and a rear panel 8, a front panel 2 and a rear panel 8 are respectively arranged at the front and the rear of the upper part of the lower panel 1, a left panel 3, a partition board A4, a partition board B5 and a right panel 6 are sequentially arranged from left to right above the lower panel 1, the lower panel 1, the front panel 2, the left panel 3, the isolation board A4, the upper panel 7 and the rear panel 8 surround to form a heat dissipation cavity 9, the lower panel 1, the front panel 2, the isolation plate A4, the isolation plate B5, the upper panel 7 and the rear panel 8 surround to form a data processing cavity 10, the lower panel 1, the front panel 2, the isolation board B5, the right panel 6, the upper panel 7 and the rear panel 8 surround to form a power supply cavity 11.

Several support columns 101 are installed to the terminal surface under panel 1 down, support column 101 lower extreme is provided with the buffer layer, the effectual buffering protection that carries on.

The front panel 2 is provided with a power interface 201 and a switch button 202, and the front panel 2 is provided with a plurality of uniformly distributed heat dissipation net openings for effectively dissipating heat.

The left panel 3 is provided with two cooling fans 301, and the two cooling fans 301 are symmetrically installed around the center line of the left panel 3.

Example 2

The data processing chamber 10 internally mounted has CPU processing integrated circuit board 1001, input integrated circuit board 1002, output integrated circuit board 1003 all are provided with the several, input integrated circuit board 1002, output integrated circuit board 1003 include HDMI integrated circuit board, DVI integrated circuit board, VGA integrated circuit board, CPU processing integrated circuit board 1001 includes the IP decoding function, supports 4K video signal.

The switching power supply 1101 and the wire passing hole 1102 are arranged in the power supply cavity 11, the switching power supply 1101 is electrically connected with the power supply interface 201, and the switching power supply 1101 passes through the wire passing hole 1102 and is electrically connected with the CPU processing board 1001, the input board 1002, the output board 1003 and the heat dissipation fan 301.

And a plurality of heat dissipation holes are formed in the isolation plate A4, the isolation plate B5 and the right panel 6, so that heat is effectively dissipated, and the operation stability of the device is improved.

The utility model discloses a theory of operation is: the during operation, the utility model discloses a modular design, data processing chamber 10 internally mounted have CPU to handle integrated circuit board 1001, input integrated circuit board 1002, output integrated circuit board 1003 all are provided with the several, input integrated circuit board 1002, output integrated circuit board 1003 include HDMI integrated circuit board, DVI integrated circuit board, VGA integrated circuit board, CPU handles integrated circuit board 1001 and includes the IP function of decoding, supports 4K video signal, and HDMI integrated circuit board, DVI integrated circuit board and VGA integrated circuit board make independent module separately respectively to adopt the form equipment of plug-in card. Different quantity of cartridge, different kind module card, but convenient and fast ground satisfies different functional demands, greatly reduced the fault rate of product, practiced thrift maintenance duration and cost of maintenance, reduced the maintenance cost, the utility model discloses a hardware architecture design adopts the FPGA framework, and no operating system, the start-up rate is fast, and the radiating effect is good, and the operation is stable, supports long-time continuous operation, the utility model discloses every way signal all can realize striding polylith display screen to show, can enlarge to whole full screen display the most.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A discretization-free multi-screen splicing image processor comprises a lower panel (1), a front panel (2), a left panel (3), a partition board A (4), a partition board B (5), a right panel (6), an upper panel (7) and a rear panel (8), and is characterized in that the front panel (2) and the rear panel (8) are respectively arranged at the front and the rear of the upper part of the lower panel (1), the left panel (3), the partition board A (4), the partition board B (5) and the right panel (6) are sequentially arranged above the lower panel (1) from left to right, a heat dissipation cavity (9) is formed by the surrounding of the lower panel (1), the front panel (2), the partition board A (4), the partition board B (5), the upper panel (7) and the rear panel (8), a data processing cavity (10) is formed by the surrounding of the lower panel (1), the front panel (2), the partition board A (4), the partition board B (5), the upper panel (7) and the rear panel (8), the power supply comprises a lower panel (1), a front panel (2), a separation plate B (5), a right panel (6), an upper panel (7) and a rear panel (8) which are encircled to form a power supply cavity (11).

2. The non-discretization multi-screen splicing image processor according to claim 1, wherein a plurality of supporting pillars (101) are installed on the lower end surface of the lower panel (1), and a buffer layer is disposed on the lower ends of the supporting pillars (101).

3. The non-discretization multi-screen splicing image processor according to claim 1, wherein a power interface (201) and a switch button (202) are installed on the front panel (2), and a plurality of heat dissipation mesh openings are uniformly distributed on the front panel (2).

4. The non-discretization multi-screen mosaic image processor of claim 1, wherein two cooling fans (301) are installed on the left panel (3), and the two cooling fans (301) are installed symmetrically with respect to a center line of the left panel (3).

5. The discretization-free multi-screen splicing image processor according to claim 4, wherein a CPU processing board card (1001), an input board card (1002) and an output board card (1003) are installed inside the data processing chamber (10), the input board card (1002) and the output board card (1003) are provided with a plurality of boards, the input board card (1002) and the output board card (1003) comprise an HDMI board card, a DVI board card and a VGA board card, and the CPU processing board card (1001) has an IP decoding function and supports 4K video signals.

6. The non-discretization multi-screen splicing image processor of claim 5, wherein a switch power supply (1101) and a wire through hole (1102) are installed inside the power supply cavity (11), the switch power supply (1101) is electrically connected with the power interface (201), and the switch power supply (1101) passes through the wire through hole (1102) to be electrically connected with the CPU processing board (1001), the input board (1002), the output board (1003) and the cooling fan (301).

7. The non-discretization multi-screen splicing image processor of claim 1, wherein a plurality of heat dissipation holes are disposed on each of the partition A (4), the partition B (5) and the right panel (6).