CN210294850U - Sampling circuit and electronic device - Google Patents
Sampling circuit and electronic device Download PDFInfo
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- CN210294850U CN210294850U CN201921545660.2U CN201921545660U CN210294850U CN 210294850 U CN210294850 U CN 210294850U CN 201921545660 U CN201921545660 U CN 201921545660U CN 210294850 U CN210294850 U CN 210294850U
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Abstract
The utility model discloses a sampling circuit and electronic equipment, the sampling circuit comprises a sampling signal generating circuit, a sampling signal amplifying circuit and a sampling signal output circuit; the input end of the sampling signal amplifying circuit is connected with the output end of the sampling signal generating circuit so as to receive a signal to be sampled, the power supply control end of the sampling signal amplifying circuit receives a pulse width modulation signal, and the output end of the sampling signal amplifying circuit is connected with the input end of the sampling signal output circuit. The technical scheme of the utility model, can reduce portable electronic equipment's consumption.
Description
Technical Field
The utility model relates to the field of electronic technology, in particular to sampling circuit and electronic equipment.
Background
The internal parts of the electronic products on the market comprise various sampling circuits, different analog signals are sampled through the internal sampling circuits, and then the next operation is executed according to the sampled data.
For some electronic products, the signals do not need to be collected in real time, and only need to be sampled once every certain time. Although some electronic products need to sample once every certain time, the related circuits of sampling still continue to work when they do not sample, which results in low energy utilization efficiency of electronic products, especially portable electronic products.
SUMMERY OF THE UTILITY MODEL
The utility model provides a sampling circuit and electronic equipment aims at improving portable electronic equipment's energy efficiency.
In order to achieve the above object, the present invention provides a sampling circuit, which comprises a sampling signal generating circuit, a sampling signal amplifying circuit and a sampling signal output circuit; the input end of the sampling signal amplifying circuit is connected with the output end of the sampling signal generating circuit so as to receive a signal to be sampled, the power supply control end of the sampling signal amplifying circuit receives a pulse width modulation signal, and the output end of the sampling signal amplifying circuit is connected with the input end of the sampling signal output circuit; wherein,
the sampling signal amplifying circuit is used for being started when the pulse width modulation signal is at a high level, amplifying the signal to be sampled and outputting the signal to be sampled to the sampling signal output circuit so that the sampling signal output circuit can sample the signal to be sampled;
the sampling signal amplifying circuit is also used for being closed when the pulse width modulation signal is at a low level so as to disconnect the electric connection between the sampling signal generating circuit and the sampling signal output circuit.
Optionally, the sampling signal amplifying circuit includes an operational amplifier and a voltage dividing circuit, a non-inverting input terminal of the operational amplifier is an input terminal of the sampling signal amplifying circuit, an inverting input terminal of the operational amplifier is connected to an output terminal of the operational amplifier, a positive power supply terminal of the operational amplifier receives the pulse width modulation signal, and a negative power supply terminal of the operational amplifier is grounded; the output end of the operational amplifier is connected with the input end of the voltage division circuit, and the output end of the voltage division circuit is the output end of the sampling signal amplifying circuit.
Optionally, the voltage dividing circuit includes a first resistor and a second resistor, a first end of the first resistor is an input end of the voltage dividing circuit, a second end of the first resistor is an output end of the voltage dividing circuit and is connected to a first end of the second resistor, and a second end of the second resistor is grounded.
Optionally, when the positive power supply terminal of the operational amplifier is at a high level, the operational amplifier is turned on; when the positive power supply terminal of the operational amplifier is at a low level, the operational amplifier is turned off.
Optionally, the model of the operational amplifier is SGM 8051.
Optionally, the sampling signal output circuit is an analog-to-digital converter.
Optionally, the sampling circuit further includes a controller, and an output end of the controller is connected to a power control end of the sampling signal amplifying circuit;
the controller is used for outputting the pulse width modulation signal.
Optionally, the sampling circuit further includes a first capacitor, one end of the first capacitor is connected to the output end of the controller, and the other end of the first capacitor is grounded.
Optionally, the sampling circuit further includes a second capacitor, one end of the second capacitor is connected to the output end of the sampling signal amplifying circuit, and the other end of the second capacitor is grounded.
In order to achieve the above object, the present invention further provides an electronic device, which includes the sampling circuit as described in any one of the above.
The technical scheme of the utility model, set up the sampling signal amplifier circuit between sampling signal generating circuit and sampling signal output circuit, this sampling signal amplifier circuit receives the control of pulse width modulation signal, when pulse width modulation signal is the high level, the sampling signal amplifier circuit is opened work, the signal of waiting to sample of sampling signal generating circuit output is amplified and is transmitted to the sampling signal output circuit, for sampling signal output circuit to sample; when the pulse width modulation signal is at a low level, the sampling signal amplifying circuit is closed to disconnect the connection between the sampling signal generating circuit and the sampling signal output circuit, and the power consumption of the circuit is reduced. When the electronic equipment does not need sampling, the sampling signal amplifying circuit is controlled to be closed, so that the sampling related circuit stops running, the power consumption of the electronic equipment is reduced, and the energy is saved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a block diagram of an embodiment of a sampling circuit according to the present invention;
fig. 2 is a block diagram of another embodiment of the sampling circuit of the present invention;
fig. 3 is a schematic circuit diagram of an embodiment of the sampling circuit of the present invention.
The reference numbers illustrate:
| 10 | sampling |
20 | Sampling |
| 30 | Sampling |
40 | |
| 201 | |
202 | Voltage divider circuit |
| OP | Operational amplifier | R1 | A first resistor |
| R2 | Second resistance | C1 | First capacitor |
| C2 | Second capacitor | GND | Ground terminal |
| PWM | Pulse width modulation signal |
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that, if directional indications (such as upper, lower, left, right, front and rear … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description relating to "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a sampling circuit.
Referring to fig. 1, the sampling circuit includes a sampling signal generation circuit 10, a sampling signal amplification circuit 20, and a sampling signal output circuit 30; the input end of the sampling signal amplifying circuit 20 is connected with the output end of the sampling signal generating circuit 10 to receive a signal to be sampled, the power supply control end of the sampling signal amplifying circuit 20 receives a pulse width modulation signal PWM, and the output end of the sampling signal amplifying circuit 20 is connected with the input end of the sampling signal output circuit 30.
In this embodiment, the sampling signal generating circuit 10 is configured to generate a signal to be sampled. The sampling signal generating circuit 10 may be a circuit including a sensor, a thermistor, or other components, such as a temperature sensor, a humidity sensor circuit, a voltage sensor, a current sensor, or a thermistor.
The sampling signal amplifying circuit 20 is configured to perform a corresponding operation according to the received PWM signal. The sampling signal amplifying circuit 20 may be implemented by a circuit composed of an operational amplifier, wherein when the power control terminal of the sampling signal amplifying circuit 20 is at a high level, the sampling signal amplifying circuit 20 starts to operate, and when the power control terminal of the sampling signal amplifying circuit 20 is at a low level, the sampling signal amplifying circuit 20 is turned off and stops operating.
The sampling signal output circuit 30 is configured to sample a signal to be sampled, and the sampling signal output circuit 30 may be an AD sampling circuit, such as an analog-to-digital converter.
Specifically, the power control end of the sampling signal amplifying circuit 20 receives an input PWM signal, and the PWM signal may be provided by a controller, such as a microprocessor, e.g., a single chip, a DSP, or an FPGA. When the PWM signal is at a high level, the power control terminal of the sampling signal amplifying circuit 20 is at an effective high level, and the sampling signal amplifying circuit 20 starts to operate to receive the signal to be sampled output by the sampling signal generating circuit 10. Because the sampling signal amplifying circuit 20 is realized by a circuit composed of an operational amplifier, and the operational amplifier has the characteristics of high input impedance and low output impedance, after the signal to be sampled is amplified by the sampling signal amplifying circuit 20, no obvious attenuation occurs, so that the signal to be sampled can be completely transmitted to the sampling signal output circuit 30, the signal to be sampled received by the sampling signal output circuit 30 is extremely close to the original signal to be sampled output by the sampling signal generating circuit 10, the signal to be sampled is sampled by the sampling signal output circuit 30, and one-time sampling is completed.
When the PWM signal is at a low level, i.e., when the power control terminal of the sampling signal amplifying circuit 20 is at an inactive low level, the sampling signal amplifying circuit 20 is turned off. When the sampling signal amplifying circuit 20 is turned off, the connection between the sampling signal generating circuit 10 and the sampling signal output circuit 30 is disconnected, and the sampling signal generating circuit 10 and the sampling signal output circuit 30 also stop operating, so that power consumption is no longer generated. The on-time and the off-time of the sampling signal amplifying circuit 20 can be adjusted by adjusting the duty ratio of the PWM signal. That is to say, the technical scheme of the utility model, to the electronic equipment that needs the timesharing to carry out the sampling, can be through setting up the PWM pulse width modulation signal of reasonable duty cycle to satisfy the sampling requirement of different electronic equipment, when electronic equipment needs the sampling promptly, control sampling signal amplifier circuit 20 and start, will wait that the sampling signal amplifies and output to sampling signal output circuit 30, for sampling signal output circuit 30 samples; when the electronic device does not need to sample, the sampling signal amplifying circuit 20 is controlled to be turned off so as to stop the operation of the sampling related circuit, thereby reducing the power consumption of the electronic device and saving energy.
The technical scheme of the utility model, set up sampling signal amplifier circuit 20 between sampling signal generating circuit 10 and sampling signal output circuit 30, this sampling signal amplifier circuit 20 receives PWM pulse width modulation signal's control, and when PWM pulse width modulation signal is the high level, sampling signal amplifier circuit 20 opens, and the signal of waiting to sample that will sample signal generating circuit 10 output is enlargied and is transmitted to sampling signal output circuit 30 samples; when the PWM signal is at a low level, the sampling signal amplifying circuit 20 is turned off to disconnect the connection between the sampling signal generating circuit 10 and the sampling signal output circuit 30, so that the sampling related circuit does not generate power consumption any more, thereby reducing the power consumption of the electronic device and saving energy.
In an embodiment, referring to fig. 2, the sampling signal amplifying circuit 20 includes an operational amplifier 201 and a voltage dividing circuit 202, a non-inverting input terminal of the operational amplifier 201 is an input terminal of the sampling signal amplifying circuit 20, an inverting input terminal of the operational amplifier 201 is connected to an output terminal of the operational amplifier 201, a positive power supply terminal of the operational amplifier 201 receives the PWM signal, and a negative power supply terminal of the operational amplifier 201 is grounded; the output end of the operational amplifier 201 is connected to the input end of the voltage dividing circuit 202, and the output end of the voltage dividing circuit 202 is the output end of the sampling signal amplifying circuit 20.
In this embodiment, the operational amplifier 201 may be an SGM8051 operational amplifier 201, and the voltage dividing circuit 202 may be implemented by serially connecting a plurality of resistors to divide voltage.
Specifically, the non-inverting input terminal of the operational amplifier 201 receives the signal to be sampled output by the sampling signal generating circuit 10, and the positive power supply terminal of the operational amplifier 201 receives the PWM pulse width modulation signal. When the PWM signal is at a high level, the positive power supply terminal of the operational amplifier 201 is at an effective high level, and the operational amplifier 201 starts to operate, amplify the signal to be sampled output by the sampling signal generating circuit 10 and output the amplified signal to the voltage dividing circuit 202. Because the operational amplifier 201 has the characteristics of high input impedance and low output impedance, the signal to be sampled does not undergo obvious attenuation after entering the operational amplifier 201, and the signal to be sampled can be completely transmitted to the voltage division circuit 202 and then reaches the sampling signal output circuit 30 after being divided by the voltage division circuit 202.
When the PWM signal is at a low level, the positive power supply terminal of the operational amplifier 201 is at an inactive low level, and the operational amplifier 201 is turned off, so that the connection between the sampling signal generating circuit 10 and the sampling signal output circuit 30 is disconnected, and the sampling signal generating circuit 10 and the sampling signal output circuit 30 stop operating. The arrangement is such that when the operational amplifier 201 stops operating, the related circuits for sampling also stop operating, no power consumption is generated, and the power consumption of the electronic device is reduced accordingly.
In an embodiment, referring to fig. 3, based on the above embodiment, the voltage divider circuit 202 includes a first resistor R1 and a second resistor R2, a first end of the first resistor R1 is an input end of the voltage divider circuit 202, a second end of the first resistor R1 is an output end of the voltage divider circuit 202 and is connected to a first end of the second resistor R2, and a second end of the second resistor R2 is grounded.
The first resistor R1 and the second resistor R2 adopt serial voltage division to divide the signal to be sampled output by the operational amplifier 201. By setting the voltage dividing circuit 202 to ensure that the signal amplitude of the signal to be sampled arriving at the sampling signal output circuit 30 is lower than the maximum signal amplitude that the sampling signal output circuit 30 can sample, it is ensured that the sampling signal output circuit 30 can sample successfully.
Optionally, the resistances of the first resistor R1 and the second resistor R2 may be 1K.
Fig. 2 is a block diagram of another embodiment of the sampling circuit of the present invention.
In an embodiment, the sampling circuit further includes a controller 40, and an output terminal of the controller 40 is connected to the power control terminal of the sampling signal amplifying circuit 20.
In this embodiment, the controller 40 may be a microprocessor such as a single chip, a DSP, an FPGA, or the like, and the controller 40 is configured to output a pulse width modulation signal to the operational amplifier 201 of the sampling signal amplifying circuit 20 to control the operational amplifier 201 to start and stop operating. Because the operational amplifier 201 needs a very small current, about 1mA current can be operated, and the controller 40 can output 5mA to 10mA current, the controller 40 can be used for controlling the operational amplifier 201 to be started and closed, and can also be used as a power supply of the operational amplifier 201, so that the circuit structure is simplified, and the circuit cost is reduced.
In an embodiment, referring to fig. 3, based on the above embodiment, the sampling circuit further includes a first capacitor C1, one end of the first capacitor C1 is connected to the output terminal of the controller 40, and the other end of the first capacitor C1 is grounded.
The first capacitor C1 is used for filtering the ac signal output by the controller 40 and retaining the dc signal. Optionally, the first capacitor C1 is 0.1 uF.
In an embodiment, referring to fig. 3, based on the above embodiment, the sampling circuit further includes a second capacitor C2, one end of the second capacitor C2 is connected to the output terminal of the sampled signal amplifying circuit 20, and the other end of the second capacitor C2 is grounded.
And the second capacitor C2 is used for filtering noise and interference in the signal to be sampled. Optionally, the second capacitor C2 is 0.01 uF.
The utility model also provides an electronic device, the electronic device includes the sampling circuit as described above, and the detailed structure of the sampling circuit can refer to the above-mentioned embodiment, and is not repeated here; it can be understood that, because the utility model discloses used above-mentioned sampling circuit among the electronic equipment, consequently, the utility model discloses electronic equipment's embodiment includes all technical scheme of the whole embodiments of above-mentioned sampling circuit, and the technological effect that reaches is also identical, no longer gives unnecessary details here. The electronic equipment can be television, tablet personal computer, mobile phone and other electronic equipment.
The above is only the optional embodiment of the present invention, and not the scope of the present invention is limited thereby, all the equivalent structure changes made by the contents of the specification and the drawings are utilized under the inventive concept of the present invention, or the direct/indirect application in other related technical fields is included in the patent protection scope of the present invention.
Claims (10)
1. The sampling circuit is characterized by comprising a sampling signal generating circuit, a sampling signal amplifying circuit and a sampling signal output circuit; the input end of the sampling signal amplifying circuit is connected with the output end of the sampling signal generating circuit so as to receive a signal to be sampled, the power supply control end of the sampling signal amplifying circuit receives a pulse width modulation signal, and the output end of the sampling signal amplifying circuit is connected with the input end of the sampling signal output circuit; wherein,
the sampling signal amplifying circuit is used for being started when the pulse width modulation signal is at a high level, amplifying the signal to be sampled and outputting the signal to be sampled to the sampling signal output circuit so that the sampling signal output circuit can sample the signal to be sampled;
the sampling signal amplifying circuit is also used for being closed when the pulse width modulation signal is at a low level so as to disconnect the electric connection between the sampling signal generating circuit and the sampling signal output circuit.
2. The sampling circuit according to claim 1, wherein the sampling signal amplifying circuit comprises an operational amplifier and a voltage dividing circuit, wherein a non-inverting input terminal of the operational amplifier is an input terminal of the sampling signal amplifying circuit, an inverting input terminal of the operational amplifier is connected to an output terminal of the operational amplifier, a positive power supply terminal of the operational amplifier receives the pulse width modulation signal, and a negative power supply terminal of the operational amplifier is grounded; the output end of the operational amplifier is connected with the input end of the voltage division circuit, and the output end of the voltage division circuit is the output end of the sampling signal amplifying circuit.
3. The sampling circuit of claim 2, wherein the voltage divider circuit comprises a first resistor and a second resistor, a first terminal of the first resistor is an input terminal of the voltage divider circuit, a second terminal of the first resistor is an output terminal of the voltage divider circuit and is connected to a first terminal of the second resistor, and a second terminal of the second resistor is connected to ground.
4. The sampling circuit of claim 2, wherein the operational amplifier is turned on when the positive supply terminal of the operational amplifier is high; when the positive power supply terminal of the operational amplifier is at a low level, the operational amplifier is turned off.
5. The sampling circuit of claim 2, wherein the operational amplifier is of the type SGM 8051.
6. The sampling circuit of claim 1, wherein the sampled signal output circuit is an analog-to-digital converter.
7. The sampling circuit of any of claims 1 to 6, further comprising a controller, an output of the controller being connected to a power supply control terminal of the sampled signal amplification circuit;
the controller is used for outputting the pulse width modulation signal.
8. The sampling circuit of claim 7, further comprising a first capacitor, one end of the first capacitor being connected to the output of the controller, the other end of the first capacitor being connected to ground.
9. The sampling circuit of claim 8, further comprising a second capacitor, one end of the second capacitor being connected to the output of the sampled signal amplification circuit, the other end of the second capacitor being connected to ground.
10. An electronic device, characterized in that the electronic device comprises a sampling circuit according to any of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921545660.2U CN210294850U (en) | 2019-09-17 | 2019-09-17 | Sampling circuit and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921545660.2U CN210294850U (en) | 2019-09-17 | 2019-09-17 | Sampling circuit and electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210294850U true CN210294850U (en) | 2020-04-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921545660.2U Active CN210294850U (en) | 2019-09-17 | 2019-09-17 | Sampling circuit and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210294850U (en) |
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- 2019-09-17 CN CN201921545660.2U patent/CN210294850U/en active Active
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