CN210294384U - Common-mode magnetic interference resistant differential complementary hall current sensor chip - Google Patents
Common-mode magnetic interference resistant differential complementary hall current sensor chip Download PDFInfo
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- CN210294384U CN210294384U CN201921115214.8U CN201921115214U CN210294384U CN 210294384 U CN210294384 U CN 210294384U CN 201921115214 U CN201921115214 U CN 201921115214U CN 210294384 U CN210294384 U CN 210294384U
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Abstract
The utility model discloses an anti common mode magnetic interference difference complementary type hall current sensor chip, the chip includes: 2 Hall amplifying circuits, a first amplifier and a second amplifier; the 2 Hall amplifying circuits are respectively a first Hall amplifying circuit and a second Hall amplifying circuit; each of the 2 hall amplification circuits includes: the circuit comprises a Hall sensor, a preamplifier and a dynamic offset elimination circuit; the technical effects that the magnetic interference is effectively filtered, and the current sensor chip is not interfered by external magnetic interference signals any more are achieved.
Description
Technical Field
The utility model relates to a current sensor chip field specifically relates to an anti common mode magnetic interference difference complementary type hall current sensor chip.
Background
The isolation type hall current sensor adopts a hall principle to sense a magnetic field generated by electrifying a copper coil so as to measure and calculate the current of the coil, a hall induction point and a hall channel are generally adopted in the traditional scheme, but the scheme is interfered by an external magnetic signal, and the output voltage is subjected to an interference magnetic field to generate errors.
SUMMERY OF THE UTILITY MODEL
The utility model provides an anti common mode magnetic interference difference complementary type hall current sensor chip has solved not enough that the hall current sensor of current isolated exists, has realized effective filtering magnetic interference, and the current sensor chip no longer receives the technological effect of external magnetic interference signal's interference.
In order to realize the above utility model purpose, this application provides an anti common mode magnetic interference difference complementary type hall current sensor chip, the chip includes:
2 Hall amplifying circuits, a first amplifier and a second amplifier; the 2 Hall amplifying circuits are respectively a first Hall amplifying circuit and a second Hall amplifying circuit; each of the 2 hall amplification circuits includes: the circuit comprises a Hall sensor, a preamplifier and a dynamic offset elimination circuit;
the positive input end of the Hall sensor is connected with the VCC end of the chip, and the negative input end of the Hall sensor is connected with the VSS end of the chip; the positive output end of the Hall sensor is connected with the positive input end of the preamplifier, and the negative output end of the Hall sensor is connected with the negative input end of the preamplifier; the positive output end of the preamplifier is connected with the positive input end of the dynamic offset cancellation circuit, and the negative output end of the preamplifier is connected with the negative input end of the dynamic offset cancellation circuit; the positive output end of the dynamic offset cancellation circuit in the first Hall amplification circuit and the positive output end of the dynamic offset cancellation circuit in the second Hall amplification circuit are respectively connected with the positive input end of the first amplifier; the negative output end of the dynamic offset cancellation circuit in the first Hall amplification circuit and the negative output end of the dynamic offset cancellation circuit in the second Hall amplification circuit are respectively connected with the positive input end of the second amplifier; the negative input end of the first amplifier is connected with the negative input end of the second amplifier; the output end of the first amplifier is connected with the OUTP end of the chip; the output end of the second amplifier is connected with the OUTN end of the chip. The chip comprises a chip body, a chip module and a chip module, wherein the circuit and the module in the chip are all the existing, and the chip is protected by the application in terms of a composition structure and a connection relation.
Furthermore, the positive output end of the dynamic offset canceling circuit in the first hall amplifying circuit and the positive output end of the dynamic offset canceling circuit in the second hall amplifying circuit are respectively connected with the first resistor and then are connected with the positive input end of the first amplifier.
Furthermore, the negative output end of the dynamic offset canceling circuit in the first hall amplifying circuit and the negative output end of the dynamic offset canceling circuit in the second hall amplifying circuit are respectively connected with the second resistor and then are connected with the positive input end of the second amplifier.
Furthermore, the negative input end of the first amplifier is connected with the negative input end of the second amplifier after being connected with the third resistor.
Further, a fourth resistor is connected between the output end of the first amplifier and the negative input end of the first amplifier.
Furthermore, a fifth resistor is connected between the output end of the second amplifier and the negative input end of the second amplifier. .
Furthermore, the chip further comprises a temperature compensation circuit, an oscillator circuit and a sensitivity trimming circuit, wherein the temperature compensation circuit is connected with the preamplifier, the sensitivity trimming circuit is connected with the preamplifier, and the oscillator circuit is connected with the temperature compensation circuit.
Furthermore, the Hall sensor is integrated in the chip through an integrated wire, and the integrated wire is serially welded in a path to be detected of the chip.
Further, the chip has 2 hall sensing channels.
Furthermore, the magnetic induction gains of the 2 hall induction channels are the same in size, and the common mode gains are opposite in direction.
One or more technical solutions provided by the present application have at least the following technical effects or advantages:
the chip in this application adopts the magnetism gain the same, and two opposite passageways of gain sample copper coil's two opposite polarity's position respectively, can effectively filter magnetic interference, and the current sensor chip no longer receives external magnetic interference signal's interference like this.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention;
fig. 1 is a schematic structural diagram of a differential complementary hall current sensor chip with anti-common-mode magnetic interference in the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention more clearly understood, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflicting with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and the scope of the present invention is not limited by the specific embodiments disclosed below.
Referring to fig. 1, the present application provides a common-mode magnetic interference resistant differential complementary hall current sensor chip, including:
2 Hall amplifying circuits, a first amplifier and a second amplifier; the 2 Hall amplifying circuits are respectively a first Hall amplifying circuit and a second Hall amplifying circuit; each of the 2 hall amplification circuits includes: the circuit comprises a Hall sensor, a preamplifier and a dynamic offset elimination circuit;
the positive input end of the Hall sensor is connected with the VCC end of the chip, and the negative input end of the Hall sensor is connected with the VSS end of the chip; the positive output end of the Hall sensor is connected with the positive input end of the preamplifier, and the negative output end of the Hall sensor is connected with the negative input end of the preamplifier; the positive output end of the preamplifier is connected with the positive input end of the dynamic offset cancellation circuit, and the negative output end of the preamplifier is connected with the negative input end of the dynamic offset cancellation circuit; the positive output end of the dynamic offset cancellation circuit in the first Hall amplification circuit and the positive output end of the dynamic offset cancellation circuit in the second Hall amplification circuit are respectively connected with the positive input end of the first amplifier; the negative output end of the dynamic offset cancellation circuit in the first Hall amplification circuit and the negative output end of the dynamic offset cancellation circuit in the second Hall amplification circuit are respectively connected with the positive input end of the second amplifier; the negative input end of the first amplifier is connected with the negative input end of the second amplifier; the output end of the first amplifier is connected with the OUTP end of the chip; the output end of the second amplifier is connected with the OUTN end of the chip.
The chip further comprises a temperature compensation circuit, an oscillator circuit and a sensitivity trimming circuit, wherein the temperature compensation circuit is connected with the preamplifier, the sensitivity trimming circuit is connected with the preamplifier, and the oscillator circuit is connected with the temperature compensation circuit. The circuit and the module in the chip are all present, and the protection of the application is the composition structure and the connection relation of the chip. The temperature compensation circuit as in the present application may be a temperature compensation circuit in the following published patents: CN108933517A, CN205958115U, CN201266119Y, etc.; the sensitivity trimming circuit, i.e., the trimming circuit, may be a trimming circuit in the following patent publications: CN107565939A, CN104656006B, CN204304976U, etc.; the oscillator circuit may be an oscillator circuit in the following publications: CN109245724A, CN106330145A, CN106953598A, CN103297000B, etc.; the dynamic offset cancellation circuit may be one of the following patent publications: CN101782634B, CN109341730A, CN102013883A, etc.
In the embodiment of the present application, the positive output terminal of the dynamic offset canceling circuit in the first hall amplifying circuit and the positive output terminal of the dynamic offset canceling circuit in the second hall amplifying circuit are respectively connected to the first resistor 5 and then are both connected to the positive input terminal of the first amplifier. The negative output end of the dynamic offset canceling circuit in the first hall amplifying circuit and the negative output end of the dynamic offset canceling circuit in the second hall amplifying circuit are respectively connected with the second resistor 6 and then are connected with the positive input end of the second amplifier. The negative input of the first amplifier is connected to the third resistor 7 and then to the negative input of the second amplifier. A fourth resistor 8 is connected between the output end of the first amplifier and the negative input end of the first amplifier. A fifth resistor 9 is connected between the output end of the second amplifier and the negative input end of the second amplifier.
The invention relates to a common-mode magnetic interference resistant differential complementary hall current sensor chip structure. In particular to a current sensor channel formed by two hall signal amplifier channels with the same gain and the opposite direction. The invention relates to a current sensor with double hall channels based on the hall magnetic induction principle. The traditional current sensor only has one hall induction point and is used for inducing a conductor, a chip tube core in the current sensor integrates two hall sensor parts and two corresponding hall signal amplification units, and the two signal amplification units superpose signals on an output channel in a resistor series connection mode. The current sensor is integrated in a chip through an integrated wire, the integrated wire is connected in series and welded in a path to be detected, and the chip calculates the value of current to be detected by sensing a magnetic field generated by the integrated wire. The magnetic induction gains of the two channels are the same, and the common mode gains are opposite. The common mode magnetic interference signal is cancelled. After the integrated copper conductor passage passes through the current to be measured, the polarities of magnetic fields manufactured on hall magnetic induction points of the two chips are opposite, so that output signals can be superposed. The chip is thus immune to external magnetic interference signals. The two hall induction channels obtain average voltage in a resistance voltage division mode to perform logic operation of common mode signal amplitude subtraction or differential mode signal amplitude addition.
While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A common-mode magnetic interference resistant differential complementary hall current sensor chip, the chip comprising:
2 Hall amplifying circuits, a first amplifier and a second amplifier; the 2 Hall amplifying circuits are respectively a first Hall amplifying circuit and a second Hall amplifying circuit; each of the 2 hall amplification circuits includes: the circuit comprises a Hall sensor, a preamplifier and a dynamic offset elimination circuit;
the positive input end of the Hall sensor is connected with the VCC end of the chip, and the negative input end of the Hall sensor is connected with the VSS end of the chip; the positive output end of the Hall sensor is connected with the positive input end of the preamplifier, and the negative output end of the Hall sensor is connected with the negative input end of the preamplifier; the positive output end of the preamplifier is connected with the positive input end of the dynamic offset cancellation circuit, and the negative output end of the preamplifier is connected with the negative input end of the dynamic offset cancellation circuit; the positive output end of the dynamic offset cancellation circuit in the first Hall amplification circuit and the positive output end of the dynamic offset cancellation circuit in the second Hall amplification circuit are respectively connected with the positive input end of the first amplifier; the negative output end of the dynamic offset cancellation circuit in the first Hall amplification circuit and the negative output end of the dynamic offset cancellation circuit in the second Hall amplification circuit are respectively connected with the positive input end of the second amplifier; the negative input end of the first amplifier is connected with the negative input end of the second amplifier; the output end of the first amplifier is connected with the OUTP end of the chip; the output end of the second amplifier is connected with the OUTN end of the chip.
2. The chip of claim 1, wherein a positive output terminal of the dynamic offset cancellation circuit in the first hall amplifier circuit and a positive output terminal of the dynamic offset cancellation circuit in the second hall amplifier circuit are respectively connected to the first resistor and then connected to a positive input terminal of the first amplifier.
3. The chip of claim 1, wherein a negative output terminal of the dynamic offset cancellation circuit in the first hall amplifier circuit and a negative output terminal of the dynamic offset cancellation circuit in the second hall amplifier circuit are respectively connected to the second resistor and then connected to a positive input terminal of the second amplifier.
4. The chip of claim 1, wherein the negative input terminal of the first amplifier is connected to the negative input terminal of the second amplifier after being connected to the third resistor.
5. The chip of claim 1, wherein a fourth resistor is connected between the output terminal of the first amplifier and the negative input terminal of the first amplifier.
6. The chip of claim 1, wherein a fifth resistor is connected between the output terminal of the second amplifier and the negative input terminal of the second amplifier.
7. The chip of claim 1, further comprising a temperature compensation circuit, an oscillator circuit, and a sensitivity trimming circuit, wherein the temperature compensation circuit is connected to the preamplifier, the sensitivity trimming circuit is connected to the preamplifier, and the oscillator circuit is connected to the temperature compensation circuit.
8. The chip of claim 1, wherein the Hall sensor is integrated in the chip through an integrated wire, and the integrated wire is serially soldered in a to-be-tested path of the chip.
9. The chip of claim 1, wherein the chip has 2 hall sensing channels.
10. The chip of claim 9, wherein the magnetic induction gains of the 2 hall sensing channels are the same, and the common mode gains are opposite in direction.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2019202850615 | 2019-03-06 | ||
| CN201920285061 | 2019-03-06 |
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| CN210294384U true CN210294384U (en) | 2020-04-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112834812A (en) * | 2021-01-06 | 2021-05-25 | 南京能晶电子科技有限公司 | Hall current sensor chip with strong anti-interference capability |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112834812A (en) * | 2021-01-06 | 2021-05-25 | 南京能晶电子科技有限公司 | Hall current sensor chip with strong anti-interference capability |
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