CN210274007U

CN210274007U - Leapfrog type rapid ring oscillator circuit

Info

Publication number: CN210274007U
Application number: CN201921494704.3U
Authority: CN
Inventors: 不公告发明人
Original assignee: Foshan Zhongxinbang Electronic Co Ltd
Current assignee: Foshan Zhongxinbang Electronic Co Ltd
Priority date: 2019-09-07
Filing date: 2019-09-07
Publication date: 2020-04-07
Anticipated expiration: 2029-09-07

Abstract

The utility model discloses a frog-leaping type rapid ring oscillator circuit, which comprises a plurality of delay amplifier units, and the ring oscillator circuit also comprises a first differential input end P + and P-, a second differential input end S + and S-and a differential output end Mn + and Mn-which are arranged on each delay amplifier unit; the ring oscillator circuit in the scheme adopts 2 (corresponding to single-ended input) or 2 pairs (corresponding to differential input) of delay amplifiers, the connection mode is usually connected step by step, and the leapfrog type cross-stage connection is realized through 1 or 1 pair of added inputs, so that positive feedback is introduced, the time delay of the whole link is shortened, the level inversion of the delay amplifiers is accelerated, and the oscillation frequency is improved.

Description

Leapfrog type rapid ring oscillator circuit

Technical Field

The utility model relates to a semiconductor integrated circuit technical field, concretely relates to quick ring oscillator circuit of leapfrog formula.

Background

A PLL (phase locked loop) circuit provides clocks for a plurality of communication chips, a multi-stage ring oscillator is a core circuit of the PLL, a conventional multi-stage ring oscillator is formed by cascading a plurality of delay amplifiers, and the conventional design usually focuses on characteristics such as adjustment accuracy (for example, publication No. CN 105811969 a), temperature compensation (for example, publication No. CN 105811925 a), and the like, but the speed of such a cascaded ring oscillator is limited by the delay of a single delay amplifier.

The existing ring oscillators have the speed limit caused by the delay of a single delay amplifier, and have the speed bottleneck under the same CMOS semiconductor process.

Disclosure of Invention

To the defect that exists among the prior art, the utility model aims to provide a quick ring oscillator circuit of leapfrog formula, this ring oscillator circuit is through increasing the input and adopting the cascade mode of leapfrog formula to the delay amplifier unit among the ring oscillator, has improved the time delay of link, has improved ring oscillator's oscillating frequency.

In order to achieve the above object, the utility model adopts the following technical scheme:

a frog-leap type fast ring oscillator circuit comprises a plurality of delay amplifier units, and further comprises first differential input ends P + and P-, second differential input ends S + and S-and differential output ends Mn + and Mn-arranged in each delay amplifier unit, wherein the differential output ends Mn + and Mn-of the previous stage of delay amplifier unit are connected with the first differential input ends P + and P-of the adjacent next stage of delay amplifier unit, the second differential input ends S + and S-of each stage of delay amplifier unit are respectively connected with the differential output ends Mn + and Mn-of the previous two stages of delay amplifier unit, and n is a positive integer greater than 1.

Further, the delay amplifier unit is internally provided with a pair of PMOS (P-channel metal oxide semiconductor) tube devices for receiving signals of the second differential input ends S + and S-.

Further, the delay amplifier unit is internally provided with a pair of NMOS (N-channel metal oxide semiconductor) tube devices for receiving signals of the first differential input end P + and the P & lt- & gt.

Further, the delay amplifier unit has a pair of NMOS device transistors therein for receiving the Mn + and Mn-signals at the differential output terminals.

Further, a pair of NMOS transistor elements for receiving the differential output Mn + and Mn-signals are in a quadrature arrangement.

Compared with the prior art, the scheme has the beneficial technical effects that: the ring oscillator circuit in the scheme adopts 2 (corresponding to single-ended input) or 2 pairs (corresponding to differential input) of delay amplifiers, the connection mode is usually connected step by step, and the leapfrog type cross-stage connection is realized through 1 or 1 pair of added inputs, so that positive feedback is introduced, the time delay of the whole link is shortened, the level inversion of the delay amplifiers is accelerated, and the oscillation frequency is improved.

Drawings

Fig. 1 is a schematic structural diagram of a frog-leap type fast ring oscillator in this embodiment.

Fig. 2 is a schematic circuit diagram of a single delay amplifying unit (An in fig. 1) in the present embodiment.

Detailed Description

The present invention will be described in further detail with reference to the drawings and the following detailed description.

The technical scheme aims at solving the problems that the speed of the existing ring oscillator is limited by the delay of a single delay amplifier and the speed bottleneck exists under the same CMOS semiconductor process, and further provides the frog-leap type rapid ring oscillator circuit.

Referring to fig. 1 to 2, the frog-jump fast ring oscillator circuit in the present embodiment comprises a plurality of delay amplifier units, and further comprises first differential input terminals P + and P-, second differential input terminals S + and S-, and differential output terminals Mn + and Mn-arranged in each delay amplifier unit, wherein the differential output terminals Mn + and Mn-of the delay amplifier unit of the previous stage are connected to the first differential input terminals P + and P-of the delay amplifier unit of the next stage, and the second differential input terminals S + and S-of each delay amplifier unit of the next stage are connected to the differential output terminals Mn + and Mn-of the delay amplifier unit of the previous stage, respectively, wherein n is a positive integer > 1.

Specifically, referring to fig. 1, a1, a2 … An are delay amplifier units, P + and P-are first differential inputs, S + and S-are second differential inputs, M1+ and M1-, M2+ and M2- … Mn + and Mn-correspond to the differential outputs of the delay amplifier units a1, a2 … An; furthermore, the second differential inputs S + and S-of each stage of delay amplifier cell will be connected to the inputs of the differential outputs Mn + and Mn-of the second stage of delay amplifier cell preceding it, e.g. the second differential inputs S + and S-of delay amplifier cell A3, which are connected to the differential outputs M1+ and M1-of the second stage of delay amplifier cell A1 preceding it, and so on. The cascade mode is the frog-leap cascade mode, and the cascade mode can accelerate the level inversion of the delay amplifier An, reduce the delay and improve the oscillation frequency of the oscillator by introducing forward feedback.

Referring now to fig. 2, An exemplary circuit diagram of the delay amplifier unit An of fig. 1 is shown, wherein MP1 and MP2 are PMOS devices for receiving input signals at the second differential inputs S + and S-, MN1 and MN2 are NMOS devices for receiving input signals at the first differential inputs P + and P-, MN3 and MN4 are NMOS devices in quadrature connection, and M + and M-are differential outputs.

In summary, the scheme improves the delay of the link and increases the oscillation frequency of the ring oscillator by adding the input to the delay amplifier unit in the ring oscillator and adopting the leapfrog type cascade mode.

It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalent technologies, the present invention is also intended to include such modifications and variations.

Claims

1. A frog-leap fast ring oscillator circuit, said ring oscillator circuit comprising a plurality of delay amplifier cells, characterized by: the ring oscillator circuit further comprises first differential input terminals P + and P-, second differential input terminals S + and S-, and differential output terminals Mn + and Mn-arranged in each of the delay amplifier units, wherein the differential output terminals Mn + and Mn-of the delay amplifier unit of a previous stage are connected to the first differential input terminals P + and P-of the delay amplifier unit of an adjacent subsequent stage, the second differential input terminals S + and S-of the delay amplifier unit of each stage are respectively connected to the differential output terminals Mn + and Mn-of the delay amplifier units of the previous two stages, and n is a positive integer > 1.

2. A frog-leap fast ring oscillator circuit according to claim 1, further comprising: the delay amplifier unit is internally provided with a pair of PMOS (P-channel metal oxide semiconductor) tube devices for receiving signals of the second differential input ends S + and S-.

3. A frog-leap fast ring oscillator circuit according to claim 2, further comprising: the delay amplifier unit is internally provided with a pair of NMOS (N-channel metal oxide semiconductor) tube devices for receiving signals of a first differential input end P + and a first differential input end P-.

4. A frog-leap fast ring oscillator circuit according to claim 3, further comprising: the delay amplifier unit has a pair of NMOS device transistors therein for receiving Mn + and Mn-signals at the differential output terminals.

5. A frog-leap fast ring oscillator circuit according to claim 4, further comprising: a pair of NMOS transistors for receiving the differential output Mn + and Mn-signals are in a quadrature arrangement.