CN210273868U - Power amplifier, transmitter and wireless power transmission system - Google Patents

Abstract

The present disclosure provides a power amplifier, a transmitter and a wireless power transmission system, wherein the power amplifier includes: the device comprises a boosting unit, a driving unit connected with the boosting unit and a full-bridge unit connected with the driving unit; wherein the full bridge cell includes: a first NMOS, a second NMOS, a third NMOS, and a fourth NMOS; the source electrodes of the first NMOS and the second NMOS are connected, and the source electrodes are grounded together; the drain electrodes of the third NMOS and the fourth NMOS are connected, and the drain electrodes are connected with VIN together; the drain of the first NMOS is connected with the source of the third NMOS, and the drain of the second NMOS is connected with the source of the fourth NMOS. The power amplifier, the transmitter and the wireless power transmission system improve conversion efficiency and stability and reduce cost.

Description

Power amplifier, transmitter and wireless power transmission system

Technical Field

The present disclosure relates to the field of wireless power transmission technologies, and in particular, to a power amplifier, a transmitter, and a wireless power transmission system suitable for wireless charging.

Background

In modern society, various electronic devices are used more and more, and the range and the number of the electronic devices are increasing. These electronic devices basically require a power source, and various electric devices such as a generator, a power source, a receiver, and a power converter are required for supplying power. The power converter generally includes DC-DC, DC-AC, AC-DC, and AC-DC converters.

At present, in fields such as the internet of things, smart phones, tablet computers, smart watches, bluetooth headsets, wearable devices, such as IT devices, are increasing in number, so the demand for wireless charging technology is more urgent than in the past. As shown in fig. 1, a wireless charging or wireless power transfer system, a transmitter and a receiver of which are physically separated and transfer AC power using a coil or an inductor. Therefore, the DC-AC converter is a key component of the transmitter and the AC-DC converter is a key component of the receiver.

In a wireless charging system, power transfer efficiency of a transmitter and a receiver is very important, and a main factor determining the efficiency is conversion efficiency of a power amplifier (DC-AC converter) and a rectifier (AC-DC converter).

As shown in fig. 2, after VIN is added to a pulse wave, the current on the coil is changed by the switching action of the switching tube M1, so that the dc power is converted into an electromagnetic wave to be emitted, the current on the coil is changed twice in one period, and the current is changed to 0 to Ipp, according to a power calculation formula:

due to the structural limitation of the existing power amplifier, the power conversion efficiency is low under the condition of the same changing current. Therefore, a power amplifier with high conversion efficiency and good stability is needed.

SUMMERY OF THE UTILITY MODEL

Technical problem to be solved

In view of the above problems, it is a primary object of the present disclosure to provide a power amplifier, a transmitter and a wireless power transmission system, so as to solve at least one of the above problems.

(II) technical scheme

In order to achieve the above object, as one aspect of the present disclosure, there is provided a power amplifier including: the device comprises a boosting unit, a driving unit connected with the boosting unit and a full-bridge unit connected with the driving unit; wherein the full bridge cell includes: a first NMOS, a second NMOS, a third NMOS, and a fourth NMOS; the source electrodes of the first NMOS and the second NMOS are connected, and the source electrodes are grounded together; the drain electrode of the third NMOS is connected with the drain electrode of the fourth NMOS; the drain of the first NMOS is connected with the source of the third NMOS, and the drain of the second NMOS is connected with the source of the fourth NMOS.

In some embodiments, the driving unit includes a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit; the first drive circuit is connected with the grid electrode of the first NMOS, the second drive circuit is connected with the grid electrode of the second NMOS, the third drive circuit is connected with the grid electrode of the third NMOS, and the fourth drive circuit is connected with the grid electrode of the fourth NMOS.

In some embodiments, the boosting unit includes a first boosting circuit and a second boosting circuit; the first booster circuit is connected with the third driving circuit, and the second booster circuit is connected with the fourth driving circuit.

In some embodiments, the power amplifier further comprises:

a first low-voltage ESD, the first end of which is connected with the first end of the first drive circuit, and the second end of which is grounded;

a second low-voltage ESD, a first end of which is connected with a second end of the second drive circuit, and a second end of which is grounded;

a first end of the first high-voltage ESD is connected with a first end of the first booster circuit, and a second end of the first high-voltage ESD is grounded;

a first end of the second high-voltage ESD is connected with a second end of the second booster circuit, and the second end is grounded;

a first end of the first capacitor is connected with the drain electrode of the first NMOS, and a second end of the first capacitor is connected with a third end of the first booster circuit; and

and a first end of the second capacitor is connected with the drain electrode of the second NMOS, and a second end of the second capacitor is connected with a third end of the second booster circuit.

In some embodiments, the second terminal of the first driving circuit is connected to the gate of the first NMOS;

the first end of the second driving circuit is connected with the grid electrode of the second NMOS;

the first end of the third driving circuit is connected with the second end of the first boosting circuit, the second end of the third driving circuit is connected with the grid electrode of the third NMOS, and the third end of the third driving circuit is connected with the third end of the first boosting circuit;

the first end of the fourth driving circuit is connected with the grid electrode of the fourth NMOS, the second end of the fourth driving circuit is connected with the first end of the second booster circuit, and the third end of the fourth driving circuit is connected with the third end of the second booster circuit.

In some embodiments, the fourth terminal of the third driving circuit is connected to the source of the third NMOS, and the fourth terminal of the fourth driving circuit is connected to the source of the fourth NMOS.

In some embodiments, the third and fourth driving circuits include a clamping circuit including a zener diode and an ESD protection circuit.

In some embodiments, the ESD protection circuit comprises:

a resistor, a first end of which is connected with a first end of the Zener diode;

a first end of the capacitor is connected with the second end of the resistor, and a second end of the capacitor is connected with the second end of the Zener diode;

a buffer, a first end of which is connected with a first end of the Zener diode, a second end of which is connected with a second end of the Zener diode, and a third end of which is connected with a second end of the resistor; and

and the grid electrode of the NMOS is connected with the fourth end of the buffer, the drain electrode of the NMOS is connected with the first end of the Zener diode, and the source electrode of the NMOS is connected with the second end of the Zener diode.

According to another aspect of the present disclosure, there is also provided a transmitter including the power amplifier.

According to yet another aspect of the present disclosure, there is also provided a wireless power transmission system including the transmitter and further including a receiver for receiving a signal transmitted by the transmitter.

(III) advantageous effects

According to the technical scheme, the power amplifier, the transmitter and the wireless power transmission system have at least one of the following beneficial effects:

(1) the power amplifier, the transmitter and the wireless power transmission system utilize the booster circuit, the full-bridge structure and the driving circuit, so that the conversion efficiency is improved, the stability is improved and the cost is reduced.

(2) The drive circuit utilizes the Zener diode and the clamp circuit to reduce the area of the drive circuit while satisfying the stability performance of the circuit.

Drawings

Fig. 1 is a schematic structural diagram of a conventional wireless power transmission system.

Fig. 2 is a schematic diagram of a conventional power amplifier.

Fig. 3 is a schematic diagram of a power amplifier (power amplifier) according to an embodiment of the disclosure.

Fig. 4 is a signal diagram of a power amplifier according to an embodiment of the disclosure.

Fig. 5 is a state diagram of a switching element of a power amplifier according to an embodiment of the disclosure.

Fig. 6 (a) is a schematic structure of a conventional high-order driving circuit; fig. 6 (b) is a schematic structural diagram of a high-side driving circuit according to an embodiment of the disclosure.

Fig. 7 is a schematic diagram of another structure of a power amplifier according to an embodiment of the disclosure.

< description of symbols >

101. 201-first driver circuit, 102, 202-second driver circuit, 103, 203-third driver circuit, 104, 204-fourth driver circuit, 105, 205-first booster circuit, 106, 206-second booster circuit, 107, 207-first low voltage ESD, 108, 208-second low voltage ESD, 109, 209-first high voltage ESD, 110, 210-second high voltage ESD, S-control signal, B-buffer, C, C1, C2-capacitance, R-resistance, HVD-high voltage device, LVD-low voltage device.

Detailed Description

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

The present disclosure provides a power amplifier comprising: the device comprises a boosting unit, a driving unit connected with the boosting unit and a full-bridge unit connected with the driving unit; wherein the full bridge cell includes: a first NMOS, a second NMOS, a third NMOS, and a fourth NMOS; the source electrodes of the first NMOS and the second NMOS are connected, and the source electrodes are grounded together; the drain electrodes of the third NMOS and the fourth NMOS are connected, and the drain electrodes are connected with VIN together; the drain of the first NMOS is connected with the source of the third NMOS, and the drain of the second NMOS is connected with the source of the fourth NMOS. The power amplifier disclosed by the invention utilizes the booster circuit, the full-bridge structure and the driving circuit, so that the conversion efficiency is improved, the stability is improved and the cost is reduced.

In one embodiment, as shown in fig. 3, the power amplifier structure includes:

a first drive circuit (Driver) 101;

a first low voltage ESD (LV ESD)107, a first end of which is connected with the first end of the first driving circuit, and a second end of which is grounded;

a first NMOS M1, having a gate connected to the second end of the first driving circuit and a source grounded;

a second NMOS M2, the source of which is connected to the source of the first NMOS M1, and the source of which is commonly grounded with the source of the first NMOS;

a second driving circuit 102, a first end of which is connected to the gate of the second NMOS M2;

a second low voltage ESD (LV ESD)108, a first end of which is connected with a second end of the second driving circuit, and a second end of which is grounded;

a third NMOS M3, having its source connected to the drain of the first NMOS M1;

a first Boost circuit (Boost circuit) 105;

a first high voltage ESD (HV ESD)109 having a first terminal connected to the first terminal of the first boost circuit and a second terminal connected to ground;

a third driving circuit 103, a first end of which is connected to the second end of the first boosting circuit, a second end of which is connected to the gate of the third NMOS, and a third end of which is connected to the third end of the boosting circuit;

a first capacitor C1, a first end of which is connected to the drain of the first NMOS M1, and a second end of which is connected to the third end of the first boost circuit;

a fourth NMOS M4 having its drain connected to the drain of the third NMOS M3, its source connected to the drain of the second NMOS M2, and the drain of the fourth NMOS M4 and the drain of the third NMOS M3 commonly access a voltage VIN;

a fourth driving circuit 104, a first end of which is connected to the gate of the fourth NMOS M4;

a second Boost circuit (Boost circuit)106, a first terminal of which is connected to the second terminal of the fourth driving circuit, and a third terminal of which is connected to the third terminal of the fourth driving circuit;

a second high voltage ESD110 having a first end connected to the second end of the second boost circuit and a second end grounded;

and a first end of the second capacitor is connected with the drain of the second NMOS M2, and a second end of the second capacitor is connected with a third end of the second booster circuit.

The boost circuit, the high-voltage ESD and the low-voltage ESD of the present embodiment can be implemented by the existing boost circuit, the high-voltage ESD and the low-voltage ESD, and are not particularly limited.

Fig. 3 shows a power amplifier in a wireless charging transmitter. The control signal is switched by using the transistors M1 to M4 to change the current in the coil, thereby transmitting the function as an electromagnetic wave. In the case of a wireless charging system, generally, the alternating current power supply is composed of an inductance coil and a capacitance. The diode connected in parallel with each of the transistors M1 to M4 represents a parasitic diode of the ldmos. Typically, LDNMOS are used for high voltage applications, and LDNMOS include parasitic diodes in the transistor structure.

Fig. 4 and 5 show the main signals and the operating principle of the power amplifier. The states in fig. 4 correspond to the states labeled in fig. 5 one by one. In fig. 5, the thick solid arrow represents that the current is in a steady state, the thin solid arrow represents that the current is in an establishing state, and the dotted arrow represents that the current is in a reducing state.

Referring to fig. 4 and 5, in the phase Φ 0, M2 and M3 form a current path, during which the voltage across the inductor is stable; in the phase phi 1, the current paths of M2 and M3 are gradually closed, and the voltage at two ends of the inductor changes; in a phi 2 stage, current paths of M2 and M3 are closed, and the voltage at two ends of the inductor is stable; in a phi 3 stage, current paths of M1 and M4 are gradually opened, and voltages at two ends of the inductor change; in a phi 4 stage, current paths of M1 and M4 are stable, and voltages at two ends of the inductor are stable; in a phi 5 stage, the current paths of M1 and M4 are gradually closed, and the voltage at two ends of the inductor changes; in a phi 6 stage, the current paths of M1 and M4 are closed, and the voltage at two ends of the inductor is stable; in the phase phi 7, the current paths of M2 and M3 are gradually opened, and the voltage across the inductor changes.

FIG. 4 shows the voltage variation at key points of the circuit, wherein SW1 is the M3 source signal and SW2 is the M4 source signal; TG1 is a signal of a first terminal of a first driving circuit in the power amplifier, TG2 is a signal of a second terminal of a second driving circuit in the power amplifier, TG3 is a signal of a first terminal of a first boosting circuit in the power amplifier, TG4 is a signal of a second terminal of a second boosting circuit in the power amplifier; g1 is a signal of the second terminal of the first driving circuit and the gate of the first NMOS, G2 is a signal of the first terminal of the second driving circuit and the gate of the second NMOS, G3 is a signal of the second terminal of the third driving circuit and the gate of the third NMOS, and G4 is a signal of the first terminal of the fourth driving circuit and the gate of the fourth NMOS; because G3 and G4 are output after the boost of TG3 and TG4, M3 and M4 switching tubes can be used with M1 and M2 switching tubes, so that the current flowing through the inductor is IPP-IPP, and the conversion efficiency of the power amplifier is improved.

In addition, in the conventional power amplifier, a high voltage device hvd (high voltage device) is required to be used for designing a driving circuit for driving a high voltage, as shown in fig. 6 (a), but since the high voltage device has a large area and a complex parasitic model, it is disadvantageous to improve the efficiency of the power amplifier and reduce the chip area. The disclosed high-side driving circuit (third driving circuit, fourth driving circuit) is designed by using a low voltage device lvd (low voltage device), but the problem with the low voltage device is that if the original structure is adopted, since BST (BST1, BST2) can reach 20V at most, a breakdown effect may occur, and the stability of the circuit and the ESD protection capability may be affected, so that a clamp circuit is added in the disclosed driving circuit, so that the voltage difference between BST and SW (SW1 or SW2) is stabilized at 5V, thereby reducing the area of the driving circuit while satisfying the stability performance of the circuit, as shown in (b) of fig. 6.

In another embodiment, different from the previous embodiment, the third driving circuit and the fourth driving circuit adopt the circuit structure shown in fig. 6 (b), the fourth terminal of the third driving circuit is connected to the source (SW1) of the third NMOS M3, and the fourth terminal of the fourth driving circuit is connected to the source (SW2) of the fourth NMOS M4. The first NMOS M1 and the second NMOS M2 do not need high voltage, and the first driving circuit and the second driving circuit adopt common driving circuit structures. Specifically, the third driving circuit and the fourth driving circuit include a clamping circuit, the clamping circuit includes a zener diode and an ESD protection circuit, specifically, a first terminal of the zener diode is connected to the BST, and a second terminal of the zener diode is connected to the SW (SW1 or SW2), and the ESD protection circuit includes: a resistor R having a first end connected to a first end of the Zener diode; a first end of the capacitor C is connected with the second end of the resistor, and a second end of the capacitor C is connected with the second end of the Zener diode; a first end of the buffer B is connected with a first end of the Zener diode, a second end of the buffer B is connected with a second end of the Zener diode, and a third end of the buffer B is connected with a second end of the resistor; and the NMOSM is connected with the fourth end of the buffer through the grid electrode, the drain electrode and the second end of the Zener diode, and the source electrode is connected with the first end of the Zener diode. The buffer can adopt the existing buffer structure, for example, two inverters are adopted to form the buffer. When the BST changes too fast, the ESD protection circuit discharges the BST point, and the Zener diode stabilizes the voltage difference between the BST and the SW (SW1 or SW2) at 5V. Therefore, the circuit can fully meet the stability of low-voltage devices operating under high-voltage conditions.

The present disclosure can be successfully applied in wireless charging system chips with overall efficiency above 90%.

The present disclosure also provides a transmitter comprising the above power amplifier.

In addition, the present disclosure also provides a wireless power transmission system, which includes the transmitter and a receiver for receiving the signal transmitted by the transmitter.

Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.

It should be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, mentioned in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

Furthermore, the word "comprising" or "comprises" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (10)

1. A power amplifier, comprising: the device comprises a boosting unit, a driving unit connected with the boosting unit and a full-bridge unit connected with the driving unit; wherein the full bridge cell includes: a first NMOS, a second NMOS, a third NMOS, and a fourth NMOS; the source electrodes of the first NMOS and the second NMOS are connected, and the source electrodes are grounded together; the drain electrode of the third NMOS is connected with the drain electrode of the fourth NMOS; the drain of the first NMOS is connected with the source of the third NMOS, and the drain of the second NMOS is connected with the source of the fourth NMOS.

2. The power amplifier of claim 1, wherein the driving unit comprises a first driving circuit, a second driving circuit, a third driving circuit and a fourth driving circuit; the first drive circuit is connected with the grid electrode of the first NMOS, the second drive circuit is connected with the grid electrode of the second NMOS, the third drive circuit is connected with the grid electrode of the third NMOS, and the fourth drive circuit is connected with the grid electrode of the fourth NMOS.

3. The power amplifier according to claim 2, wherein the boosting unit includes a first boosting circuit and a second boosting circuit; the first booster circuit is connected with the third driving circuit, and the second booster circuit is connected with the fourth driving circuit.

4. The power amplifier of claim 3, further comprising:

a first low-voltage ESD, the first end of which is connected with the first end of the first drive circuit, and the second end of which is grounded;

a second low-voltage ESD, a first end of which is connected with a second end of the second drive circuit, and a second end of which is grounded;

a first end of the first high-voltage ESD is connected with a first end of the first booster circuit, and a second end of the first high-voltage ESD is grounded;

a first end of the second high-voltage ESD is connected with a second end of the second booster circuit, and the second end is grounded;

a first end of the first capacitor is connected with the drain electrode of the first NMOS, and a second end of the first capacitor is connected with a third end of the first booster circuit; and

and a first end of the second capacitor is connected with the drain electrode of the second NMOS, and a second end of the second capacitor is connected with a third end of the second booster circuit.

5. The power amplifier of claim 4,

the second end of the first driving circuit is connected with the grid electrode of the first NMOS;

the first end of the second driving circuit is connected with the grid electrode of the second NMOS;

the first end of the third driving circuit is connected with the second end of the first boosting circuit, the second end of the third driving circuit is connected with the grid electrode of the third NMOS, and the third end of the third driving circuit is connected with the third end of the first boosting circuit;

the first end of the fourth driving circuit is connected with the grid electrode of the fourth NMOS, the second end of the fourth driving circuit is connected with the first end of the second booster circuit, and the third end of the fourth driving circuit is connected with the third end of the second booster circuit.

6. The power amplifier of claim 5, wherein the fourth terminal of the third driver circuit is connected to the source of the third NMOS and the fourth terminal of the fourth driver circuit is connected to the source of the fourth NMOS.

7. The power amplifier of claim 6, wherein the third and fourth driver circuits comprise a clamp circuit comprising a zener diode and an ESD protection circuit.

8. The power amplifier of claim 7, wherein the ESD protection circuit comprises:

a resistor, a first end of which is connected with a first end of the Zener diode;

a first end of the capacitor is connected with the second end of the resistor, and a second end of the capacitor is connected with the second end of the Zener diode;

a buffer, a first end of which is connected with a first end of the Zener diode, a second end of which is connected with a second end of the Zener diode, and a third end of which is connected with a second end of the resistor; and

and the grid electrode of the NMOS is connected with the fourth end of the buffer, the drain electrode of the NMOS is connected with the first end of the Zener diode, and the source electrode of the NMOS is connected with the second end of the Zener diode.

9. A transmitter, characterized in that it comprises a power amplifier according to any one of claims 1 to 8.

10. A wireless power transfer system comprising the transmitter of claim 9, and further comprising a receiver for receiving signals transmitted by the transmitter.

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