CN210272339U - Pad structure and semiconductor device - Google Patents

Pad structure and semiconductor device Download PDF

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Publication number
CN210272339U
CN210272339U CN201921673256.3U CN201921673256U CN210272339U CN 210272339 U CN210272339 U CN 210272339U CN 201921673256 U CN201921673256 U CN 201921673256U CN 210272339 U CN210272339 U CN 210272339U
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Prior art keywords
pad body
protective layer
pad
trench
groove
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CN201921673256.3U
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Chinese (zh)
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吴秉桓
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

The utility model relates to a semiconductor manufacturing technology field especially relates to a pad structure and semiconductor device. The pad structure includes: the bonding pad comprises a bonding pad body, a bonding pad body and a bonding pad, wherein the bonding pad body comprises an upper surface and a lower surface which are oppositely distributed, and the lower surface is used for being electrically connected with an internal circuit of a chip; the groove extends from the upper surface to the inside of the bonding pad body and divides the bonding pad body into a testing area and a welding area; and the protective layer at least covers the bottom wall of the groove. The utility model discloses having separated test area territory and welding area territory, having avoided the problem of the easy failure of encapsulation line because of probe test leads to, it is right to have avoided external environment simultaneously test area territory with the damage of the chip between the welding area territory has improved semiconductor device's yield and stability of performance.

Description

Pad structure and semiconductor device
Technical Field
The utility model relates to a semiconductor manufacturing technology field especially relates to a pad structure and semiconductor device.
Background
In a back-end packaging process of a semiconductor device such as a Dynamic Random Access Memory (DRAM), a pad structure is usually formed on a surface of a semiconductor chip for performing a probe test and a packaging connection (bonding). However, in the process of performing a probe test, due to the contact between the probe and the pad structure, the surface of the pad structure may be scratched or fine dust may be introduced on the surface of the pad structure, so that when a subsequent package is performed, a metal circuit is easily pulled, and a wire bonding is then dropped, which affects the yield of the semiconductor device, or even results in the rejection of the semiconductor device.
Therefore, how to reduce the influence of the probe test on the package wiring and improve the yield of the semiconductor device is a technical problem to be solved at present.
SUMMERY OF THE UTILITY MODEL
The utility model provides a pad structure and semiconductor device for solve current semiconductor device and easily appear in the encapsulation processing procedure with the problem of outside wiring connection failure, with the yield that improves semiconductor device, improve semiconductor device's stability of performance.
In order to solve the above problem, the utility model provides a pad structure, include:
the bonding pad comprises a bonding pad body, a bonding pad body and a bonding pad, wherein the bonding pad body comprises an upper surface and a lower surface which are oppositely distributed, and the lower surface is used for being electrically connected with an internal circuit of a chip;
the groove extends from the upper surface to the inside of the bonding pad body and divides the bonding pad body into a testing area and a welding area;
and the protective layer at least covers the bottom wall of the groove.
Optionally, the trench penetrates through the pad body, and the protective layer is used for covering the surface of the chip at the bottom of the trench;
on the upper surface, a gap is formed between the edge of the groove and the edge of the pad body so as to realize the electric connection between the testing area and the welding area on the upper surface.
Optionally, the depth of the groove is smaller than the thickness of the pad body, and the protective layer covers the surface of the pad body at the bottom of the groove.
Optionally, the protective layer includes:
a first protective layer at least covering the bottom wall of the groove;
and a second protective layer covering the first protective layer.
Optionally, the protective layer covers the bottom wall and the side wall of the trench.
Optionally, on the upper surface, the trench extends along a first direction by a length of 30 μm to 80 μm and along a second direction perpendicular to the first direction by a width of 0.5 μm to 20 μm.
In order to solve the above problem, the utility model also provides a semiconductor device, include:
a chip;
in the pad structure of any one of the above claims, the lower surface of the pad body is electrically connected to the internal circuit of the chip.
Optionally, the protective layer covers at least the bottom wall of the trench and the surface of the chip except the surface on which the pad structure is formed.
The utility model provides a pad structure and semiconductor device, through forming the slot on the pad body, on the one hand, separated test area and welding area, avoided the problem that the encapsulation line is easy to fail because of the probe test, improved semiconductor device's yield; on the other hand, the protective layer is formed to cover the bottom wall of the groove, so that the surface of the chip between the test area and the welding area is covered, the damage of the external environment to the chip between the test area and the welding area is avoided, and the yield and the performance stability of the semiconductor device are further improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a pad structure according to a first embodiment of the present invention;
fig. 2 is a schematic top view of a pad structure according to a first embodiment of the present invention;
fig. 3 is a flow chart of a method for forming a pad structure according to a first embodiment of the present invention;
fig. 4A-4F are schematic diagrams of the main process cross-sections of a first embodiment of the present invention in the formation of a pad structure and a semiconductor device;
fig. 5 is a flow chart of a method of forming a semiconductor device according to a first embodiment of the present invention;
fig. 6 is a schematic cross-sectional view of a pad structure according to a second embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of a pad structure and a semiconductor device according to the present invention with reference to the accompanying drawings.
First embodiment
This embodiment provides a pad structure, and fig. 1 is the utility model discloses a pad structure's cross-sectional schematic diagram among the first embodiment, and fig. 2 is the utility model discloses pad structure's structural schematic that overlooks among the first embodiment. As shown in fig. 1 and fig. 2, the pad structure provided by the present embodiment includes:
a pad body 20 including an upper surface and a lower surface which are oppositely distributed, the lower surface being used for electrically connecting with the internal circuit 101 of the chip 10;
a groove 13 extending from the upper surface toward the inside of the pad body 20, dividing the pad body 20 into a test area 12 and a bonding area 11;
and the protective layer at least covers the bottom wall of the groove 13.
Specifically, the material of the pad body 20 is a conductive material, such as a metal material. When the material of the pad body 20 is a metal material, the metal material may be any single metal material of copper, aluminum, and tungsten, or an alloy material formed of two or more metals. The pad body 20 may be rectangular in shape, and for example, the ratio of the length of the pad body in the X-axis direction to the width of the pad body in the Y-axis direction may be (1:1) to (2: 1). The groove 13 extends from the upper surface of the pad body 20 to the inside of the pad body 20 along the Z-axis direction, so that the pad body 20 is divided into the test area 12 and the soldering area 11, and the test area 12 and the soldering area 11 are distributed on two opposite sides of the groove 13 along the X-axis direction. The surface of the test area 12 is provided with a probe mark for performing probe test; the soldering region 11 is used for electrical connection with an external line 14 (e.g. gold wire). When the probe 15 is used for testing the test region 12, the probe 15 can also fall into the groove 13, and the side wall of the groove 13 can also block the probe 15 from damaging the welding region 11; the protective layer in the trench 13 can also prevent damage to the chip, for example, to avoid the problem of cracks on the chip surface due to the probe directly penetrating the chip surface. The relative area size of the soldering region 11 and the testing region 12 can be set by those skilled in the art according to actual needs, for example, according to the requirement of probe testing and the requirement of wire bonding for connection with an external circuit, which is not limited in this embodiment.
In this embodiment, the test area 12 is separated from the bonding area 11, so as to avoid the damage (e.g., scratch caused by the probe 15, generated dust) caused by the probe test from adversely affecting the subsequent wire bonding (e.g., wire bonding falling off), and the protective layer covers the bottom wall surface of the trench 13, so as to avoid the exposure of the chip 10 between the bonding area 11 and the test area 12 due to the arrangement of the trench 13, thereby ensuring the performance stability of the semiconductor device having the pad structure. In this embodiment, the protective layer may cover only the bottom wall of the trench 13, and may also cover the bottom wall and a part of the side wall of the trench 13 at the same time. In this embodiment, the top surface of the protective layer is located below the top surface of the trench 13 or is flush with the top surface of the trench 13, i.e., the height of the protective layer is less than or equal to the depth of the trench 13.
In other specific embodiments, the top surface of the protection layer is located above the top surface of the trench, that is, the height of the protection layer is greater than the depth of the trench, at this time, the protection layer is independent from the upper surface of the pad body, that is, the protection layer does not cover the upper surface of the pad body, and a gap exists between the edge of the protection layer and each of the test region 12 and the soldering region 11.
The depth of the groove 13 along the Z-axis direction can be set by those skilled in the art according to actual needs, for example, according to the thickness of the pad body 20, requirements for subsequent connection with external lines, and the like. Optionally, the depth of the trench 13 is 100nm to 2 μm. For example, in one embodiment, the depth of the trench 13 may be 100nm to 200nm, 200nm to 400nm, or 400nm to 800 nm; in another embodiment, the depth of the trench 13 may be 900nm to 1.5 μm, or 1.5 μm to 2 μm.
The specific shape of the groove 13 is not limited in this embodiment, and those skilled in the art can select the shape according to actual needs. In order to simplify the formation process of the pad structure, the cross-sectional shape of the trench 13 along a direction parallel to the upper surface may be rectangular, circular or elliptical.
Optionally, the groove 13 penetrates through the pad body 20, and the protective layer is used for covering the surface of the chip 10 at the bottom of the groove 13;
on the upper surface, there is a gap between the edge of the groove 13 and the edge of the pad body 20 to achieve electrical connection between the test region 12 and the soldering region 11 on the upper surface.
Specifically, the groove 13 penetrates the pad body 20 in the Z-axis direction (a direction perpendicular to the pad body 20), that is, the depth of the groove 13 is the same as the thickness of the pad body 20. The surface of the chip 10 between the test area 12 and the bonding area 11 is exposed from the groove 13, and the protection layer covers the surface of the chip 10 exposed between the bonding area 11 and the test area 12. As shown in fig. 2, a gap 21 with a width D is formed between the edge of the groove 13 and the edge of the pad body 20, forming a narrow neck region for connecting the soldering region 11 and the testing region 12, thereby further reducing the resistance inside the pad structure.
In this embodiment, the protection layer may be a single layer or a multi-layer stacked structure. In order to simplify the forming process of the pad structure and improve the shielding effect on the surface of the chip 10 between the testing region 12 and the bonding region 11, optionally, the protective layer includes:
a first protective layer 16 covering at least the bottom wall of the trench 13;
and a second protective layer 17 covering the first protective layer 16.
Optionally, the protective layer covers the bottom wall and the side walls of the trench 13.
Specifically, the first protection layer 16 covers the sidewalls and the bottom wall of the trench 13, and the second protection layer 17 covers the surface of the first protection layer 16. The material of the first protection layer 16 and the material of the second protection layer 17 preferably have a high etching selectivity ratio, for example, the etching selectivity ratio is greater than or equal to 3, so as to simplify the forming process of the pad structure.
Optionally, on the upper surface, the trench 13 has a length of 30 μm to 80 μm extending in a first direction and a width of 0.5 μm to 20 μm in a second direction perpendicular to the first direction.
For example, the Y-axis direction is a first direction, and the X-axis direction is a second direction. The groove 13 is rectangular, and the length L of the groove 13 in the Y-axis direction may be 30 to 80 μm and the width W in the X-axis direction may be 0.5 to 20 μm.
Furthermore, the present embodiment further provides a method for forming a pad structure, fig. 3 is a flow chart of a method for forming a pad structure according to the first embodiment of the present invention, fig. 4A to 4F are schematic diagrams of a main process cross section of the first embodiment of the present invention in a process of forming a pad structure, and fig. 1 and fig. 2 can be referred to as schematic diagrams of a pad structure formed according to the present embodiment. As shown in fig. 1 to 3 and fig. 4A to 4F, the method for forming a pad structure according to this embodiment includes the following steps:
step S31, forming a pad body 20, where the pad body 20 includes an upper surface and a lower surface that are distributed oppositely, and the lower surface is used to be electrically connected to the internal circuit 101 of the chip 10;
step S32, forming a groove 13 on the upper surface of the pad body 20, where the groove 13 extends from the upper surface to the inside of the pad body 20, and divides the pad body 20 into a testing area 12 and a soldering area 11, as shown in fig. 4C.
Optionally, the method further comprises the following steps:
providing a pad base layer 40;
forming a photoresist layer 41 on the surface of the pad base layer 40, wherein the photoresist layer 41 has an opening 411 exposing the pad base layer 40, as shown in fig. 4A;
the pad base layer 40 is etched to simultaneously form the pad body 20 and the trench 13, as shown in fig. 4C.
Specifically, the pad base layer 40 may be formed by depositing a conductive material on a surface of the chip 10 by using a physical vapor deposition process or an atomic layer deposition process. The conductive material may be a metal material, such as a single metal material of any one of copper, aluminum, and tungsten, or an alloy material formed of two or more kinds. After forming the pad base layer 40 covering the surface of the chip 10, a pad area is defined on the surface of the pad base layer 40, and the photoresist layer 41 covering the pad area is formed, wherein the photoresist layer 41 has an opening 411 exposing the pad base layer 40. Next, the pad base layer 40 not covered by the photoresist layer 41 is etched by using a dry etching process, and the pad body 20 and the trench 13 are simultaneously formed, as shown in fig. 4B. Then, the photoresist layer 41 is removed to form the structure shown in fig. 4C.
Step S33 is to form a protective layer covering at least the bottom wall of the trench 13.
Optionally, the specific step of forming the protective layer at least covering the bottom wall of the trench 13 includes:
forming a first protective layer 16, wherein the first protective layer 16 covers the side wall and the upper surface of the pad body 20 and the inner wall of the trench 13, as shown in fig. 4D;
forming a second protective layer 17, wherein the second protective layer 17 covers the first protective layer 16 on the sidewall surface of the pad body 20 and on the bottom wall surface of the trench 13, as shown in fig. 4E;
the first protective layer 16 is etched using the second protective layer 17 as a mask, and the first protective layer 16 and the second protective layer 17 both remaining in the trench 13 collectively serve as the protective layer, as shown in fig. 4F.
Optionally, the groove 13 penetrates through the pad body 20, and the protective layer is used for covering the surface of the chip 10 at the bottom of the groove 13;
on the upper surface, there is a gap 21 between the edge of the groove 13 and the edge of the pad body 20 to achieve electrical connection between the test region 12 and the soldering region 11 on the upper surface.
Specifically, after the pad structure is formed, a passivation material is deposited on the surface of the pad body 20 (including the upper surface and the sidewall of the pad body 20) and the inner wall of the trench 13, so as to form a first protection layer 16 as shown in fig. 4D; then, depositing an insulating material on the surface of the first protection layer 16 covering the side wall of the pad body 20 and the bottom wall of the trench 13 to form the second protection layer 17; then, the first protective layer 16 is etched by using the second protective layer 17 as a mask, the first protective layer 16 on the upper surface of the pad body 20 is removed, and the first protective layer 16 remaining in the trench 13 and the second protective layer 17 located in the trench 13 are collectively used as the protective layer. In order to remove the first protection layer 42 covering the upper surface of the pad body 20 sufficiently, the passivation material and the insulating material should have a high etching selectivity, for example, an etching selectivity greater than or equal to 3.
In the present embodiment, after the first protective layer 16 is etched by using the second protective layer 17 as a mask, the remaining first protective layer 16 does not cover the upper surface of the pad body 20 at all. In other specific embodiments, the first protection layer 16 remaining after etching may also cover an edge region of the upper surface of the testing region 12 on a side away from the trench 13, and an edge region of the upper surface of the soldering region 11 on a side away from the trench 13.
The depth of the trench 13 formed can be controlled by adjusting the amount of etching gas and the etching time by those skilled in the art. Optionally, the depth of the trench 13 is 100nm to 2 μm.
Optionally, on the upper surface, the trench 13 has a length of 30 μm to 80 μm extending in a first direction and a width of 0.5 μm to 20 μm in a second direction perpendicular to the first direction.
The specific shape of the groove 13 is not limited in this embodiment, and those skilled in the art can select the shape according to actual needs. In order to simplify the formation process of the pad structure, the cross-sectional shape of the trench 13 along a direction parallel to the upper surface may be rectangular, circular or elliptical.
Furthermore, the present embodiment mode provides a semiconductor device, and the structure of the semiconductor device provided by the present embodiment mode can be referred to fig. 1 and fig. 2. As shown in fig. 1 and 2, the semiconductor device according to this embodiment includes:
a chip 10;
in the pad structure of any one of the above embodiments, the lower surface of the pad body 20 is electrically connected to the internal circuit 101 of the chip 10.
Optionally, the protective layer covers at least the bottom wall of the trench 13 and the surface of the chip 10 except the surface where the pad structure is formed.
Furthermore, the present embodiment further provides a method for forming a semiconductor device, fig. 5 is a flowchart of a method for forming a semiconductor device according to the first embodiment of the present invention, fig. 4A to 4F are schematic diagrams of main process cross-sections of the first embodiment of the present invention in a process of forming a semiconductor device, and fig. 1 and fig. 2 show structures of a semiconductor device formed according to the present embodiment. As shown in fig. 1, fig. 2, fig. 4A to fig. 4F, and fig. 5, the method for forming a semiconductor device according to the present embodiment includes the steps of:
step S51, providing the chip 10;
step S52, forming a pad structure on the surface of the chip 10 by using any one of the above-mentioned methods for forming a pad structure, wherein the lower surface of the pad body 20 is electrically connected to the internal circuit 101 of the chip 10.
Optionally, the protective layer covers at least the bottom wall of the trench 13 and the surface of the chip 10 except the surface where the pad structure is formed.
According to the pad structure and the semiconductor device provided by the embodiment of the invention, the groove is formed on the pad body, so that on one hand, a test area and a welding area are separated, the problem that a packaging connection line is easy to fail due to probe test is avoided, and the yield of the semiconductor device is improved; on the other hand, the protective layer is formed to cover the bottom wall of the groove, so that the surface of the chip between the test area and the welding area is covered, the damage of the external environment to the chip between the test area and the welding area is avoided, and the yield and the performance stability of the semiconductor device are further improved.
Second embodiment
This embodiment provides a pad structure and a method for forming the same, a semiconductor device and a method for forming the same, and fig. 6 is a schematic cross-sectional view of a pad structure according to a second embodiment of the present invention. The same parts as those in the first embodiment will not be described again, and the differences from the first embodiment will be mainly described below. As shown in fig. 6, the pad structure provided by the present embodiment includes:
a pad body including an upper surface and a lower surface which are oppositely distributed, the lower surface being used for electrically connecting with the internal circuit 601 of the chip 60;
a groove 63 extending from the upper surface toward the inside of the pad body, dividing the pad body into a test area 62 and a bonding area 61;
and the protective layer at least covers the bottom wall of the groove 63.
Optionally, the depth of the groove 63 is smaller than the thickness of the pad body, and the protective layer covers the surface of the pad body at the bottom of the groove 13.
In the present embodiment, the depth of the groove 63 along the Z-axis direction is smaller than the thickness of the pad body, that is, the groove 13 does not penetrate through the pad body, so that the testing region 62 and the soldering region 61 are electrically connected through the pad body located at the bottom of the groove 63, thereby avoiding an additional resistance generated inside the pad structure due to a complete partition between the soldering region 61 and the testing region 62, and ensuring the performance stability of the semiconductor device having the pad structure.
Since the groove 63 does not penetrate the pad body, an edge of the groove 63 may coincide with an edge of the pad body, that is, a length of the groove 63 in the Y-axis direction may be equal to a width of the pad body in the Y-axis direction.
In other embodiments, in order to further reduce the resistance inside the pad structure, a gap is provided between the edge of the groove 63 and the edge of the pad body on the upper surface, so as to electrically connect the testing region 12 and the soldering region 11 on the upper surface.
Optionally, the protective layer includes:
a first protective layer 66 covering at least the bottom wall of the trench 63;
and a second protective layer 67 covering the first protective layer 66.
In the semiconductor device having the pad structure provided in this embodiment, the lower surface of the pad body is electrically connected to the internal circuit 601 of the chip 60, and the protective layer covers the surface of the pad body at the bottom of the trench 13.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims (8)

1. A pad structure, comprising:
the bonding pad comprises a bonding pad body, a bonding pad body and a bonding pad, wherein the bonding pad body comprises an upper surface and a lower surface which are oppositely distributed, and the lower surface is used for being electrically connected with an internal circuit of a chip;
the groove extends from the upper surface to the inside of the bonding pad body and divides the bonding pad body into a testing area and a welding area;
and the protective layer at least covers the bottom wall of the groove.
2. The pad structure of claim 1, wherein the trench extends through the pad body, and the protective layer covers the surface of the chip at the bottom of the trench;
on the upper surface, a gap is formed between the edge of the groove and the edge of the pad body so as to realize the electric connection between the testing area and the welding area on the upper surface.
3. The pad structure of claim 1, wherein the depth of the trench is less than the thickness of the pad body, and the protective layer covers the surface of the pad body at the bottom of the trench.
4. The pad structure of claim 1, wherein the protective layer comprises:
a first protective layer at least covering the bottom wall of the groove;
and a second protective layer covering the first protective layer.
5. The pad structure of claim 1, wherein the protective layer covers a bottom wall and sidewalls of the trench.
6. The pad structure according to claim 1, wherein the trench extends on the upper surface in a first direction with a length of 30 μm to 80 μm and a width in a second direction perpendicular to the first direction with a width of 0.5 μm to 20 μm.
7. A semiconductor device, comprising:
a chip;
a pad structure according to any of claims 1-6, the lower surface of the pad body being electrically connected to internal circuitry of the chip.
8. The semiconductor device according to claim 7, wherein the protective layer covers at least a bottom wall of the trench and the chip surface except for the pad structure formed.
CN201921673256.3U 2019-09-30 2019-09-30 Pad structure and semiconductor device Active CN210272339U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201921673256.3U CN210272339U (en) 2019-09-30 2019-09-30 Pad structure and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201921673256.3U CN210272339U (en) 2019-09-30 2019-09-30 Pad structure and semiconductor device

Publications (1)

Publication Number Publication Date
CN210272339U true CN210272339U (en) 2020-04-07

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Country Status (1)

Country Link
CN (1) CN210272339U (en)

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