CN210272311U - Cipher chip - Google Patents

Abstract

The utility model discloses a password chip, photoetching structure are formed by photoetching technology, and can make the figure in the territory take place the distortion because optics proximity effect in photoetching technology. Because the shape of the photoetching structure obtained by photoetching the preset layout can be distorted, the distortion has strong randomness, and the shape and the parasitic capacitance value of the photoetching structure photoetched by the same preset layout are different. The physical unclonable function circuit can generate keys corresponding to parasitic capacitance values of the photoetching structures, when the password chip is attacked in an invasive manner, the photoetching structure located on the top metal layer is damaged and cannot be recovered through other means, so that the keys output by the physical unclonable function circuit are wrong, a decryption module cannot decrypt ciphertext stored in the storage module, and the safety of information stored in the storage module is effectively protected.

Description

Cipher chip

Technical Field

The utility model relates to an integrated circuit technical field especially relates to a password chip.

Background

With the continuous progress of society and the continuous development of science and technology, the integrated circuit technology has been greatly developed, and the variety of corresponding chips is more and more. The cryptographic chip is a device capable of independently generating a key and encrypting and decrypting, and is generally used for storing some sensitive information, mainly for protecting business privacy and data security.

In the prior art, the password chip is protected against invasive attack by using technologies such as an active shielding layer and the like. The active shielding layer can only detect the on-off of signals, and under the condition that an attacker bridges signal lines in the active shielding layer, the attack is difficult to detect. Therefore, how to provide a cryptographic chip with good protection performance is an urgent problem to be solved by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a password chip can be when receiving imperial intrusive formula attack, effectively protects the information of storage.

In order to solve the above technical problem, the present invention provides a cryptographic chip, which includes a functional layer and a top metal layer located on the functional layer;

the top metal layer is provided with at least one photoetching structure, the photoetching structure comprises a first conductor and a second conductor which are distributed along the horizontal direction and are mutually isolated, and the first conductor and the second conductor are both formed by photoetching through a preset layout;

the preset layout comprises a first shielding graph corresponding to the first conductor and a second shielding graph corresponding to the second conductor; the first shielding graph comprises at least one shielding finger extending along a preset direction;

the functional layer is provided with a decryption module and a storage module, and a physical unclonable function circuit comprising the photoetching structure is used for generating a secret key; the decryption module is used for receiving the secret key and the ciphertext stored in the storage module, and decrypting the ciphertext through the secret key to decrypt a plaintext.

Optionally, the first mask pattern includes a plurality of mask fingers, and the length values of the mask fingers are all the same.

Optionally, a gap is formed between the first shielding pattern and the second shielding pattern, and the width values of any position of the gap are the same.

Optionally, the second shielding pattern annularly surrounds the first shielding pattern, the first shielding pattern includes a shielding block and at least two shielding fingers extending in different directions, and the shielding fingers and the shielding block are in contact with each other.

Optionally, the first shielding pattern includes four shielding fingers, and the first shielding pattern is cross-shaped.

Optionally, the first shielding pattern includes a shielding block and at least two shielding fingers extending along the same direction, and the shielding fingers and the shielding block are in contact with each other.

Optionally, the second shielding pattern and the first shielding pattern form an interdigital pattern.

Optionally, the decryption module is further configured to receive a plaintext, and encrypt the plaintext according to the key to obtain a ciphertext, so that the ciphertext is encrypted and stored in the storage module.

Optionally, the physical unclonable function circuit further includes an operational amplifier, the top metal layer is provided with at least four photo-etching structures, the photo-etching structures are divided into a first photo-etching structure and a second photo-etching structure, and the first photo-etching structure and the second photo-etching structure are connected in series to form a connection point between the first photo-etching structure and the second photo-etching structure; one input end of the operational amplifier is connected with one of the connection points, and the other input end of the operational amplifier is connected with the other of the connection points.

Optionally, the operational amplifier is located in the functional layer.

The utility model provides a password chip, which comprises a functional layer and a top metal layer positioned on the functional layer; the top metal layer is provided with at least one photoetching structure, the photoetching structure comprises a first conductor and a second conductor which are distributed along the horizontal direction and are mutually isolated, and the first conductor and the second conductor are both formed by photoetching through a preset layout; the preset layout comprises a first shielding graph corresponding to the first conductor and a second shielding graph corresponding to the second conductor; the first shielding graph comprises at least one shielding finger extending along a preset direction; the functional layer is provided with a decryption module and a storage module, and a physical unclonable function circuit comprising a photoetching structure is used for generating a secret key; the decryption module is used for receiving the secret key and the ciphertext stored in the storage module, and decrypting the ciphertext through the secret key to decrypt a plaintext.

Therefore, the utility model provides an among the cipher chip, because the photoetching structure forms by the photoetching technology, and because the figure that optics proximity effect can make in the territory takes place the distortion in the photoetching technology. Since the first shielding pattern has shielding fingers extending along the preset direction, the shape of the photoetching structure obtained by photoetching the preset layout can be distorted. The distortions are strongly random under the influence of random disturbance in the preparation process, so that the shapes of the photoetching structures photoetched by the same preset layout are different, and the parasitic capacitance values of the corresponding photoetching structures are different. The physically unclonable function circuit may generate a key corresponding to the parasitic capacitance values of the respective photo-etched structures, and the key may be completely random and unique. When the cryptographic chip is attacked in an invasive manner, the photoetching structure located on the top metal layer is damaged and cannot be recovered through other means, so that a key output by the physical unclonable function circuit is wrong, a ciphertext stored in the storage module cannot be decrypted by the decryption module, and the safety of information stored in the storage module is effectively protected.

Drawings

In order to clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a block diagram of a cryptographic chip according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of the photolithography structure of FIG. 1;

fig. 3 is a schematic structural diagram of a preset layout according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a first specific preset layout provided in an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a second specific preset layout provided in an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a third specific preset layout provided in the embodiment of the present invention;

fig. 7 is a circuit diagram of a specific physically unclonable function circuit according to an embodiment of the present invention.

In the figure: 1. the top metal layer, 2 functional layers, 3 photoetching structures, 31 first conductors, 32 second conductors, 33 first photoetching structures, 34 second photoetching structures, 35 series photoetching structures, 4 physical unclonable function circuits, 5 decryption modules, 6 storage modules, 71 first shielding patterns, 711 shielding fingers, 712 shielding blocks, 72 second shielding patterns and 8 operational amplifiers.

Detailed Description

The core of the utility model is to provide a password chip. In the prior art, the password chip is protected against invasive attack by using technologies such as an active shielding layer and the like. The active shielding layer can only detect the on-off of signals, and under the condition that an attacker bridges signal lines in the active shielding layer, the attack is difficult to detect.

And the utility model provides an among the crypto chip, because the photoetching structure forms by the photoetching technology, and because the figure that optics proximity effect can make in the territory takes place the distortion in the photoetching technology. Since the first shielding pattern has shielding fingers extending along the preset direction, the shape of the photoetching structure obtained by photoetching the preset layout can be distorted. The distortions are strongly random under the influence of random disturbance in the preparation process, so that the shapes of the photoetching structures photoetched by the same preset layout are different, and the parasitic capacitance values of the corresponding photoetching structures are different. The physically unclonable function circuit may generate a key corresponding to the parasitic capacitance values of the respective photo-etched structures, and the key may be completely random and unique. When the cryptographic chip is attacked in an invasive manner, the photoetching structure located on the top metal layer is damaged and cannot be recovered through other means, so that a key output by the physical unclonable function circuit is wrong, a ciphertext stored in the storage module cannot be decrypted by the decryption module, and the safety of information stored in the storage module is effectively protected.

In order to make the technical field better understand the solution of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings and the detailed description. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, fig. 2 and fig. 3, fig. 1 is a block diagram of a cryptographic chip according to an embodiment of the present invention; FIG. 2 is a schematic structural diagram of the photolithography structure of FIG. 1; fig. 3 is a schematic structural diagram of a preset layout provided in an embodiment of the present invention.

Referring to fig. 1, in the embodiment of the present invention, the cryptographic chip includes a functional layer 2 and a top metal layer 1 located on the functional layer 2; the top metal layer 1 is provided with at least one photoetching structure 3, the photoetching structure 3 comprises a first conductor 31 and a second conductor 32 which are distributed along the horizontal direction and are mutually isolated, and the first conductor 31 and the second conductor 32 are both formed by photoetching through a preset layout; the preset layout comprises a first shielding pattern 71 corresponding to the first conductor 31 and a second shielding pattern 72 corresponding to the second conductor 32; the first shielding pattern 71 includes at least one shielding finger 711 extending in a predetermined direction; the functional layer 2 is provided with a decryption module 5 and a storage module 6, and a physical unclonable function circuit 4 comprising the photoetching structure 3 is used for generating a secret key; the decryption module 5 is configured to receive the secret key and the ciphertext stored in the storage module 6, and decrypt the ciphertext with the secret key to decrypt a plaintext.

In general, a cryptographic chip includes a plurality of metal layers, metal lines for electrically connecting different circuits are usually disposed in the metal layers, and the metal layer located at the uppermost layer of the whole cryptographic chip is usually the top metal layer 1. In the embodiment of the present invention, the top metal layer 1 is located on the functional layer 2, and the functional layer 2 is used to realize the main functions of the cryptographic chip, such as storing information. When the cryptographic chip is attacked in an intrusive mode, namely, the chip is damaged by external force, the top metal layer 1 is usually damaged, and then the functional layer 2 storing information is invaded to illegally obtain information. For the specific material of the top metal layer 1, reference may be made to the prior art, and further description is omitted here.

Referring to fig. 2 and 3, in the embodiment of the present invention, the top metal layer 1 is provided with at least one photo-etching structure 3, the photo-etching structure 3 includes a first conductor 31 and a second conductor 32 distributed along the horizontal direction and isolated from each other, and the first conductor 31 and the second conductor 32 are formed by photo-etching a preset layout.

The first conductor 31 and the second conductor 32 need to be isolated from each other, so that a parasitic capacitance is generated between the first conductor 31 and the second conductor 32. The material of the first conductor 31 and the second conductor 32 is usually metal, and is the same as the material of the top metal layer 1. The specific material of the first conductor 31 and the second conductor 32 is determined according to the specific situation, and is not particularly limited in the embodiment of the present invention.

The first conductor 31 and the second conductor 32, i.e. the photo-etching structure 3, are formed by etching the top metal layer 1 through a predetermined layout by applying a photo-etching process. The photo-etching structure 3 can be understood as a capacitor, and specific contents related to the photo-etching process can refer to the prior art, which is not described herein again. When the photoetching process is applied, due to the optical proximity effect and the random disturbance of the process in the preparation process, the appearances of the photoetching structures 3 prepared by the same preset layout are different, so that the parasitic capacitance values of the photoetching structures 3 are different. It should be noted that, in the actual process, the shape of the photo-etching structure 3 prepared by using the preset layout shown in fig. 3 may still have a certain difference from that of fig. 2, and in the embodiment of the present invention, the influence of the optical proximity effect on the shape of the photo-etching structure 3 can be seen by comparing fig. 2 with fig. 3.

Referring to fig. 3, the preset layout includes a first shielding pattern 71 corresponding to the first conductor 31 and a second shielding pattern 72 corresponding to the second conductor 32; the first shielding pattern 71 includes at least one shielding finger 711 extending in a predetermined direction. It should be noted that, in general, the first shielding pattern 71 needs to have a shielding block 712 in addition to the shielding finger 711, and the shielding finger 711 contacts with the shielding block 712, so that the shielding finger 711 extends out of the shielding block 712 in the horizontal direction to form at least a convex structure to form a corner in the preset layout. It should be noted that, in the embodiment of the present invention, if the first shielding pattern 71 is only a rectangle, it is not generally considered to have the protruding structure of the shielding finger 711.

In the embodiment of the present invention, the specific shape of the second shielding pattern 72 is not particularly limited, and the second shielding pattern 72 may not have the structure of the shielding finger 711, that is, the second shielding pattern 72 may only be a rectangle. It should be noted that a gap is required between the first shielding pattern 71 and the second shielding pattern 72 to ensure that the first conductor 31 and the second conductor 32 are isolated from each other to form a parasitic capacitance. The detailed features of the first shielding pattern 71 and the second shielding pattern 72 will be described in detail in the following embodiments, and will not be described herein.

Preferably, in the embodiment of the present invention, the first shielding pattern 71 may be provided with a plurality of shielding fingers 711, and the length values of the plurality of shielding fingers 711 may be the same for facilitating the fabrication of the preset layout and reducing the interference caused by the design.

Preferably, in order to increase the number of corners between the first and second mask patterns 71 and 72, the width of the gap between the first and second mask patterns 71 and 72 may be the same. Due to the existence of the shielding fingers 711, when the width values of any position of the gap between the first shielding pattern 71 and the second shielding pattern 72 are the same, the second shielding pattern 72 can also have corners corresponding to the shielding fingers 711, so that the number of the corners in the preset layout is effectively increased, and the process sensitivity of the preset layout is further effectively increased.

It should be noted that, in general, in order to ensure that the preset layout has an obvious optical proximity effect in the photolithography process, the length value of the shielding finger 711 generally needs to be greater than the width value of the gap, so as to ensure that the first shielding pattern 71 has an obvious protrusion in a horizontal square, so that the preset layout has an obvious optical proximity effect, and at this time, the preset layout is a process-sensitive layout. It should be noted that, in order to ensure that the predetermined layout can generate different integrated circuit photolithography structures 3 according to the optical proximity effect, the length of the shielding finger 711 and the width of the gap need to be greater than the minimum size of the photolithography process used.

In the embodiment of the present invention, a physical unclonable function circuit 4(PUF) is provided in the cryptographic chip, the core of the physical unclonable function circuit 4 is the above-mentioned photoetching structure 3, and the physical unclonable function circuit 4 can generate digitized identification data based on the parasitic capacitance value of the above-mentioned photoetching structure 3. Because the parasitic capacitance value of the photoetching structure 3 has strong randomness, the identification data output by the physical unclonable function circuit 4 in different cipher chips is completely random and can be used as a secret key. The specific structure of the physically unclonable function circuit 4 will be described in detail in the following embodiments, and will not be described herein.

The functional layer 2 is provided with a decryption module 5 and a storage module 6, wherein the storage module 6 stores a ciphertext, namely encrypted sensitive information; the decryption module 5 may obtain the key generated by the physical unclonable function circuit 4 and the ciphertext stored by the storage module 6 at the same time, and decrypt the ciphertext through the key to decrypt the plaintext corresponding to the ciphertext. It should be noted that, when only the ciphertext stored in the storage module 6 is obtained, the plaintext cannot be parsed from the ciphertext because there is no key. When the attack is invaded, the structure of the photoetching structure 3 is damaged, so that the key is changed or even loses efficacy, and further, the ciphertext cannot be decrypted into the plaintext, so that the safety of the information stored in the storage module 6 is protected. For the specific structure of each of the decryption module 5 and the storage module 6, reference may be made to the prior art, and details thereof are not repeated here. Accordingly, reference may also be made to the prior art regarding the material of the functional layer 2, and details thereof are not repeated herein.

In general, the decryption module 5 may be further configured to receive a plaintext, and encrypt the plaintext according to the key, so as to encrypt the plaintext into a ciphertext, and store the ciphertext in the storage module 6. That is, the decryption module 5 usually has an encryption function, the decryption module 5 usually is an encryption/decryption module 5, and when receiving a certain plaintext, the decryption module 5 may encrypt the plaintext according to a key output by the physical unclonable function circuit 4 to obtain a ciphertext, and send the ciphertext to the storage module 6 for storage.

The embodiment of the utility model provides an among the crypto chip, because photoetching structure 3 forms by the photoetching technology, and because the figure that optics proximity effect can make in the territory takes place the distortion in the photoetching technology. Since the first mask pattern 71 has the mask fingers 711 extending in the predetermined direction, the shape of the photo-etched structure 3 obtained by photo-etching using the predetermined layout may be distorted. The distortions are strongly random under the influence of random disturbance in the preparation process, so that the shapes of the photoetching structures 3 photoetched by the same preset layout are different, and the parasitic capacitance values of the corresponding photoetching structures 3 are different. The physically unclonable function circuit 4 may generate a key corresponding to the parasitic capacitance values of the respective photo-etched structures 3, and the key is completely random and unique. When the cryptographic chip is attacked in an intrusive manner, the photoetching structure 3 located in the top metal layer 1 is damaged and cannot be recovered through other means, so that a secret key output by the physical unclonable function circuit 4 is wrong, a ciphertext stored in the storage module 6 cannot be decrypted by the decryption module 5, and the safety of information stored in the storage module 6 is effectively protected.

The specific structure of the photolithography structure 3 in the cryptographic chip provided by the present invention will be described in detail in the following embodiments of the present invention.

Referring to fig. 4, fig. 5 and fig. 6, fig. 4 is a schematic structural diagram of a first specific preset layout according to an embodiment of the present invention; fig. 5 is a schematic structural diagram of a second specific preset layout provided in an embodiment of the present invention; fig. 6 is a schematic structural diagram of a third specific preset layout provided in an embodiment of the present invention.

Be different from above-mentioned utility model embodiment, the embodiment of the utility model provides a on the basis of above-mentioned utility model embodiment, further to photoetching structure 3's in the password chip structure, especially preparation photoetching structure 3 required structure of predetermineeing the territory specifically prescribes a limit to. The rest of the contents have been described in detail in the above embodiments, and are not described again here.

The embodiment of the utility model provides an in, provide three kinds altogether and predetermine the structure of territory, these three kinds are predetermine territory structure and all can be guaranteed to predetermine the territory and be the sensitive territory of technology, can prepare out the different integrated circuit photoetching structure 3 of parasitic capacitance value according to this predetermine the territory.

First, referring to fig. 4, the second shielding pattern 72 annularly surrounds the first shielding pattern 71, the first shielding pattern 71 includes a shielding block 712 and at least two shielding fingers 711 extending in different directions, and the shielding fingers 711 and the shielding block 712 contact each other.

The second shielding pattern 72 needs to surround the first shielding pattern 71 in a ring shape, and the first shielding pattern 71 needs to include at least two shielding fingers 711 extending from the shielding block 712 to the second shielding pattern 72 in different directions, and the shielding fingers 711 and the shielding block 712 need to contact each other. Specifically, since the angles in the layout for setting the integrated circuit at the present stage can only be set to 45 °, 90 °, 135 °, and 180 °, the preset layout of the structure is usually in an axisymmetric structure. In order to ensure that the preset layout of the structure can generate sufficient optical proximity effect in the using process, the first shielding pattern 71 is generally in a cross shape, and in this case, the first shielding pattern 71 includes four shielding fingers 711, and one end of each of the four shielding fingers 711 contacts with a shielding block 712 between the four shielding fingers 711, so as to jointly form the first shielding pattern 71 of the cross-shaped structure. At this time, the first and second shielding patterns 71 and 72 together form a pattern having a central symmetrical structure.

Secondly, referring to fig. 5, the preset layout of the structure is substantially similar to the preset layout shown in the figure, and the first shielding pattern 71 in the preset layout is also cross-shaped, except that in the preset layout structure, the width of the shielding finger 711 in the first shielding pattern 71 is smaller than the length of the side length of the shielding block 712. The shielding block 712 is generally square, and at this time, the shielding fingers 711 protrude from four corners of the shielding block 712, so that compared with fig. 4, more corners are added to the preset layout formed by the first shielding pattern 71 and the second shielding pattern 72, so as to increase the influence of random disturbance in the manufacturing process on the morphology of the integrated circuit photo-etching structure 3 finally manufactured by the photo-etching process.

Third, referring to fig. 6, the first shielding pattern 71 includes a shielding block 712 and at least two shielding fingers 711 extending in the same direction, and the shielding fingers 711 and the shielding block 712 contact each other. The shielding blocks 712 of the first shielding pattern 71 are substantially rectangular, and the shielding fingers 711 are parallel to each other and have a certain distance therebetween, and normally, the shielding fingers 711 are parallel to each other along the long sides of the shielding blocks 712. Specifically, in order to ensure that there are sufficient corners between the first shielding pattern 71 and the second shielding pattern 72, the second shielding pattern 72 may have a structure similar to that of the first shielding pattern 71 and also have shielding fingers 711 extending in the same direction, and the first shielding pattern 71 and the second shielding pattern 72 are intersected with each other to form an interdigital pattern, that is, the second shielding pattern 72 and the first shielding pattern 71 form an interdigital pattern, so that a large number of corners are arranged in the preset layout, thereby increasing the influence of random disturbance in the manufacturing process on the morphology of the integrated circuit photo-etching structure 3 finally manufactured by the photo-etching process.

The embodiment of the utility model provides a specifically provide three kinds of structures of predetermineeing the territory, these three kinds of territory structures of predetermineeing all can guarantee to predetermine the territory for the sensitive territory of technology, can prepare out the different photoetching structure 3 of parasitic capacitance value according to this territory of predetermineeing.

The specific structure of the physically unclonable function circuit 4 in the cryptographic chip provided by the present invention will be described in detail in the following embodiments of the present invention.

Referring to fig. 7, fig. 7 is a circuit diagram of a specific physically unclonable function circuit according to an embodiment of the present invention.

Different from the above embodiment, the embodiment of the present invention is based on the above embodiment of the present invention, and further the structure of the cryptographic chip, especially the structure of the physical unclonable function circuit 4 in the cryptographic chip is specifically limited. The rest of the contents have been described in detail in the above embodiments, and are not described again here.

In the embodiment of the present invention, the physical unclonable function circuit 4 further includes an operational amplifier 8, the top metal layer 1 is provided with at least four photo-etching structures 3, the photo-etching structures 3 are divided into a first photo-etching structure 33 and a second photo-etching structure 34, and the first photo-etching structure 33 and the second photo-etching structure 34 are connected in series to form a connection point between the first photo-etching structure 33 and the second photo-etching structure 34; one input terminal of the operational amplifier 8 is connected to one of the connection points, and the other input terminal of the operational amplifier 8 is connected to the other of the connection points.

A most basic unit of the physically unclonable function circuit 4 is composed of four photo-etched structures 3 and an operational amplifier 8, and the most basic unit of the physically unclonable function circuit 4 can output a random value of 0 or 1 of one bit. The four photo-etching structures 3 are divided into two first photo-etching structures 33 and two second photo-etching structures 34, wherein one first photo-etching structure 33 and one second photo-etching structure 34 are connected in series to form a series photo-etching structure 35, and the other first photo-etching structure 33 and the other second photo-etching structure 34 are connected in series to form another series photo-etching structure 35. Since the above-mentioned photo-etched structure 3 can be understood as a capacitor, the corresponding above-mentioned series photo-etched structure 35 can be understood as a series capacitor. A connection point is formed between the first photolithographic structure 33 and the second photolithographic structure 34 in series, and an operational amplifier 8 typically has two inputs, and the two inputs of the operational amplifier 8 are each connected to a connection point of a series photolithographic structure 35.

It should be noted that the connection point does not generally correspond to a solid structure, and the connection point may be one of two end points of the first photo-etched structure 33 and the second photo-etched structure 34 connected to each other. It should also be noted that the series photo-etching structure 35 is usually connected to a power source at one end, and connected to ground at the other end to form a loop. The specific voltage of the power supply needs to be specifically set according to the operational amplifier 8, which is not specifically limited in the embodiment of the present invention. For the specific structure of the operational amplifier 8, reference may be made to the prior art, and details thereof will not be described herein.

In the embodiment of the present invention, when the photo-etching structures 3 are both the first photo-etching structure 33 or the second photo-etching structure 34, the preset layouts used for etching the photo-etching structures 3 need to be consistent, that is, the preset layouts for etching the first photo-etching structure 33 need to be the same, and the preset layouts for correspondingly etching the second photo-etching structure 34 also need to be the same; that is, the structures between the tandem photoetching structures 35 need to be kept consistent during design, so as to eliminate the interference of layout design on the final generated result of the operational amplifier 8. Of course, the structure of the second preset layout used for preparing the second photoetching structure 34 can be the same as or different from the structure of the first preset layout used for preparing the first photoetching structure 33, depending on the specific situation, the embodiment of the present invention is not limited specifically.

Since the shapes of the first photo-etching structure 33 and the second photo-etching structure 34 are distorted during the preparation, the capacitance values of the two series photo-etching structures 35 can be randomly changed, and the difference between the capacitance values of the two series photo-etching structures 35 connected to the same operational amplifier 8 can also be randomly changed. The operational amplifier 8 is used as a comparator to amplify the difference to obtain the digitized identification data.

Specifically, when the capacitance of the serial photo-etching structure 35 connected to the positive input terminal of the operational amplifier 8 is greater than the capacitance of the serial photo-etching structure 35 connected to the negative input terminal of the operational amplifier 8, the operational amplifier 8 outputs "1", otherwise "0" is output. Since the difference between the tandem photo-etched structures 35 is random, i.e. the "1" or "0" output by the operational amplifier 8 is random. When the physically unclonable function circuit 4 comprises a plurality of the above-mentioned substrate-most elements of the physically unclonable function circuit 4, a string of random numbers may be randomly generated as a key. At this time, in the cryptographic chip prepared by using the same preset layout, the same process and the same material, the keys output by the different physical unclonable function circuits 4 are completely random. In general, in order to protect the physically unclonable function circuit 4 in the cryptographic chip from damage, the operational amplifier 8, which is relatively delicate in structure, is usually required to be located in the functional layer 2 and protected by the top metal layer 1.

The embodiment of the utility model provides a cryptographic chip, because the territory that each series connection light etching structure 35 of preparation used is the same in the preparation process, can get rid of the design and to the influence that series connection light etching structure 35 caused. The operational amplifier 8 can amplify the difference between different tandem photo-etching structures 35 to obtain digitized identification data. And the identification data is completely random and can be used as a key. The above-described physically unclonable function circuit 4 is constituted only by the tandem photo-etching structure 35 and the operational amplifier 8, and its structure is very simple.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It is right above that the utility model provides a password chip has carried out the detailed introduction. The principles and embodiments of the present invention have been explained herein using specific examples, and the above descriptions of the embodiments are only used to help understand the method and its core ideas of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the protection scope of the appended claims.

Claims (10)

1. The cryptographic chip is characterized by comprising a functional layer and a top metal layer positioned on the functional layer;

the top metal layer is provided with at least one photoetching structure, the photoetching structure comprises a first conductor and a second conductor which are distributed along the horizontal direction and are mutually isolated, and the first conductor and the second conductor are both formed by photoetching through a preset layout;

the preset layout comprises a first shielding graph corresponding to the first conductor and a second shielding graph corresponding to the second conductor; the first shielding graph comprises at least one shielding finger extending along a preset direction;

the functional layer is provided with a decryption module and a storage module, and a physical unclonable function circuit comprising the photoetching structure is used for generating a secret key; the decryption module is used for receiving the secret key and the ciphertext stored in the storage module, and decrypting the ciphertext through the secret key to decrypt a plaintext.

2. The cryptographic chip of claim 1, wherein the first mask pattern comprises a plurality of mask fingers, and wherein the length values of the mask fingers are all the same.

3. The cryptographic chip of claim 2, wherein the first mask pattern and the second mask pattern have a gap therebetween, and a width of the gap is the same at any position.

4. The cryptographic chip of claim 1, wherein the second mask pattern annularly surrounds the first mask pattern, the first mask pattern comprising a mask block and at least two of the mask fingers extending in different directions, the mask fingers contacting the mask block.

5. The cryptographic chip of claim 4, wherein the first mask pattern comprises four of the mask fingers, the first mask pattern being cross-shaped.

6. The cryptographic chip of claim 1, wherein the first mask pattern comprises a mask block and at least two of the mask fingers extending in a same direction, the mask fingers contacting the mask block.

7. The cryptographic chip of claim 6, wherein the second masking pattern and the first masking pattern form an interdigitated pattern.

8. The cryptographic chip of claim 1, wherein the decryption module is further configured to receive plaintext and encrypt the plaintext according to the key, so as to encrypt the plaintext into ciphertext for storage by the storage module.

9. The cryptographic chip according to any of claims 1 to 8, wherein the physically unclonable function circuit further comprises an operational amplifier, the top metal layer is provided with at least four photo-etched structures, the photo-etched structures are divided into a first photo-etched structure and a second photo-etched structure, and the first photo-etched structure and the second photo-etched structure are connected in series to form a connection point between the first photo-etched structure and the second photo-etched structure; one input end of the operational amplifier is connected with one of the connection points, and the other input end of the operational amplifier is connected with the other of the connection points.

10. The cryptographic chip of claim 9, wherein the operational amplifier is located in the functional layer.

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