CN210245551U

CN210245551U - Low-power-consumption low-offset Hall sensor

Info

Publication number: CN210245551U
Application number: CN201920975758.5U
Authority: CN
Inventors: Xiaohong Dong; 董晓红; Binyang Huang; 黄彬阳
Original assignee: Shenzhen Home Town Chip Micro Technology Co ltd
Current assignee: Shenzhen Home Town Chip Micro Technology Co ltd
Priority date: 2019-06-21
Filing date: 2019-06-21
Publication date: 2020-04-03
Anticipated expiration: 2029-06-21

Abstract

The utility model discloses a low-power consumption low imbalance hall sensor, including two sets of hall sensing devices, two sets of hall sensing devices all include four contact terminal a, b, c, d, four contact terminal are respectively through the deposited metal interconnection, the equal electric connection power VCC of a terminal, the ground end is all connected to the b terminal, c, d terminal respectively with two input electric connection of operational amplifier, the substrate is wrapped up in the two sets of hall sensing devices outside, be equipped with N + injection 3 and P + injection 4 on the substrate, the both ends of substrate are equipped with the unsettled N-well of all being equipped with the electric potential; the utility model discloses an increase a structure, area identical hall sensing device, the hall sensing element that two sets of symmetries set up like this can furthest ground annihilator the intrinsic disorder of spare.

Description

Low-power-consumption low-offset Hall sensor

Technical Field

The utility model relates to a sensor technical field specifically is a low-power consumption low imbalance hall sensor.

Background

The Hall sensors are classified from implementation processes, mainly comprise a BIPOLAR process and a CMOS process, the Hall sensors adopting the BIPOLAR process generally have higher working voltage and larger power consumption, and have the advantages of low offset voltage, high sensitivity and high working speed, and the Hall sensors manufactured by the CMOS process generally have low working voltage and small power consumption, can be applied to portable equipment, and have the defects of large offset and relatively lower sensitivity.

The development trend of semiconductor technology is to realize the integration of sensors under the same technology, and after a micro sensor is combined with other circuits on a standard CMOS technology platform, the complexity of peripheral circuits can be reduced, the packaging cost can be reduced, the mass production with low cost can be realized, and the market competitiveness is better.

In the low power consumption design in the prior art, the hall sensing element is generally compatible with the CMOS process, the hall sensing element has four contact terminals a, b, c, d, the a end is connected to the VCC power supply, the b end is grounded, the direction of the current flowing through the hall device is from a to b, according to the hall effect principle, the two ends c and d generate hall voltage, the end c and the end d are respectively connected to the two input ends of the operational amplifier to amplify and output the hall voltage, the disadvantage of the prior art scheme is that: due to the restriction of the process cost, the Hall sensitive element cannot be completely symmetrical, so that the offset is large.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a low-power consumption low imbalance hall sensor has advantages such as can reduce hall sensing element imbalance for solve the problem that proposes in the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme: the utility model provides a low-power consumption low imbalance hall sensor, includes two sets of hall sensing device, two sets of hall sensing device are H1 and H2 respectively, two sets of hall sensing device all include four contact terminal a, b, c, d, through sedimentary metal interconnection between the a terminal, the equal electric connection power VCC of a terminal, also through sedimentary metal interconnection between the b terminal, the ground end is all being connected to the b terminal, also through sedimentary metal interconnection between the c terminal, also through sedimentary metal interconnection between the d terminal, c, d terminal respectively with two input electric connection of operational amplifier, the substrate is being wrapped up in two sets of hall sensing device outsides, be equipped with N + on the substrate and pour into 3 and P + into 4, the both ends of substrate are equipped with all and are equipped with the unsettled N-well of electric potential.

Preferably, the two groups of Hall sensing devices are symmetrically arranged, the structures and the areas of the two groups of Hall sensing devices are completely the same, and four terminals of the two groups of Hall sensing devices are reversely arranged and symmetrically connected.

Preferably, the current in the Hall sensitive device flows from the terminal a to the terminal b, and a Hall voltage is generated between the terminal c and the terminal d in the vertical direction.

Preferably, a P + injection region ring is arranged around the N-well with the suspended potential, and four heavily doped regions N + injection regions are arranged in the N-well with the suspended potential.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model discloses a CMOS technology of low-power consumption develops a novel low imbalance hall sensor structure, realizes on standard CMOS technology platform, integrated microsensor and large-scale integrated circuit, on hall sensing element's of prior art basis, increases a structure, the hall sensing element that the area is identical, two hall sensing element's in this circuit structure are the structure that a symmetry set up, the hall sensing element that two sets of symmetries set up like this can furthest eliminate the inherent imbalance of ware.

Drawings

FIG. 1 is a schematic structural view of the present invention;

fig. 2 is a schematic plan view of the present invention;

FIG. 3 is a schematic longitudinal structure of the present invention;

fig. 4 is a schematic diagram of an example of the present invention.

In the figure: 1. pressing a key; 2. a Hall sensing circuit; 3. and a permanent magnet.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The same reference numbers in different drawings identify the same or similar elements; it should be further understood that terms such as "first," "second," "third," "upper," "lower," "front," "rear," "inner," "outer," "end," "portion," "section," "width," "thickness," "zone," and the like, may be used solely for convenience in reference to the figures and to aid in describing the invention, and are not intended to limit the invention.

Referring to fig. 1-4, the present invention provides a technical solution: the utility model provides a low-power consumption low imbalance hall sensor, including two sets of hall sensing device, two sets of hall sensing device are H1 and H2 respectively, two sets of hall sensing device all include four contact terminal a, b, c, d, through the deposited metal interconnection between the a terminal, the equal electric connection power VCC of a terminal, also through the deposited metal interconnection between the b terminal, the b terminal is all connected with the ground end, also through the deposited metal interconnection between the c terminal, also through the deposited metal interconnection between the d terminal, c, d terminal respectively with two input electric connection of operational amplifier, the substrate is wrapped up to two sets of hall sensing device outsides, be equipped with N + injection 3 and P + injection 4 on the substrate, the both ends of substrate are equipped with the unsettled N-well of electric potential.

Specifically, the two groups of hall sensing devices are symmetrically arranged, the structures and the areas of the two groups of hall sensing devices are completely the same, and four terminals of the two groups of hall sensing devices are reversely arranged and symmetrically connected.

Specifically, the current in the Hall sensitive device flows from the terminal a to the terminal b, and a Hall voltage is generated between the terminal c and the terminal d in the vertical direction, and the symmetrical flow of the current can eliminate offset voltage.

Specifically, a P + injection region ring is arranged around the N-well with the suspended potential, four heavily doped region N + injection regions are arranged in the N-well with the suspended potential, the P + injection ring is a contact hole of a P-type substrate, surface carrier flowing caused by inversion of a device is prevented, and four contact terminals are connected by punching the N + injection region.

The implementation mode is as follows: according to the technical scheme, the device is characterized in that the device is a P-type substrate 1 in fig. 3, N-wells 2, N + implants 3, P + implants 4 and N-wells 5, the N-wells on the left side and the right side in fig. 4 are completely the same, a P + injection region ring is arranged around the two N-wells, the P + injection region ring is a contact hole of the P-type substrate and prevents surface carriers from flowing due to inversion of the device, Hall sensitive surfaces in the N-wells are also completely the same, four heavily doped region N + injection regions are arranged in each N-well, four contact terminals are formed by punching the N + injection regions, and the four contact terminals form a structure similar to van der pol resistors and are of a symmetrical structure as shown in fig. 3.

According to fig. 2, two hall sensitive devices are interconnected by deposited metal, wherein the left terminal of the left device is connected with the rightmost terminal of the right device, namely the a terminal, the terminal in the middle of the two devices is connected, namely the b terminal, the terminal above the left device is connected with the terminal below the right device, namely the c terminal, and the rest is the d terminal; and the outer rings of the two Hall sensitive devices are provided with N-wells with suspended electric potentials, and the suspended N-wells have the function of anti-electromagnetic interference.

According to fig. 1, current flows from an end a to an end b in a horizontal direction, a hall voltage is generated between an end c and an end d in a vertical direction according to a hall effect principle, an output voltage Vo (H1) between the end c and the end d of a hall sensing device H1 is Vh + Voff, where Vh is a hall voltage, Voff is an offset voltage of the device, an output voltage Vo (H2) of the hall sensing device H2 is Vh + Voff, the two output voltages are added, and a voltage Vin input to a next-stage operational amplifier is (Vh + Voff) + (-Vh + Voff) is 2 Vh; from the above, the offset voltage Voff is cancelled.

According to the embodiment of fig. 4, when the key 1 is pressed, the hall sensing surface of the hall sensing circuit 2 is close to the magnetic field of the permanent magnet 3, and when the detected magnetic field strength is greater than the set threshold value, the hall circuit outputs a conducting signal.

In the embodiment, because the using amount of the Hall circuits on each keyboard exceeds 100, the Hall circuits are required to have the characteristics of low power consumption and low cost, and by applying the technical scheme of the invention and adopting a 5V standard CMOS process, the average working current of the Hall circuits is as low as 3 uA-30A, and the Hall sensitive device has the characteristic of low offset voltage.

In the implementation of the present invention, the two hall sensing device structures with the same area described in the technical solution are not limited, and the area ratio of H1 to H2 may be designed to be 1: 2 or 1: 4 or 1: 9, etc.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The low-power-consumption low-offset Hall sensor comprises two groups of Hall sensitive devices and is characterized in that: the two groups of Hall sensitive devices are respectively H1 and H2, the two groups of Hall sensitive devices all comprise four contact terminals a, b, c and d, the terminals a are interconnected through deposited metal, the terminals a are electrically connected with a power VCC, the terminals b are also interconnected through deposited metal, the terminals b are all connected with a ground end, the terminals c are also interconnected through deposited metal, the terminals d are also interconnected through deposited metal, the terminals c and d are respectively electrically connected with two input ends of an operational amplifier, the outer sides of the two groups of Hall sensitive devices are wrapped by a substrate, the substrate is provided with N + injection 3 and P + injection 4, and two ends of the substrate are provided with N-wells with suspended electric potentials.

2. A low power consumption low offset hall sensor according to claim 1, wherein: the two groups of Hall sensing devices are symmetrically arranged, the structures and the areas of the two groups of Hall sensing devices are completely the same, and four terminals of the two groups of Hall sensing devices are reversely arranged and symmetrically connected.

3. A low power consumption low offset hall sensor according to claim 1, wherein: the current in the Hall sensitive device flows from the a terminal to the b terminal, and a Hall voltage is generated between the c terminal and the d terminal in the vertical direction.

4. A low power consumption low offset hall sensor according to claim 1, wherein: and a P + injection region ring is arranged around the N-well with the suspended potential, and four heavily doped regions N + injection regions are arranged in the N-well with the suspended potential.