CN210201835U - Attenuator control panel and GNSS satellite signal forwarding system - Google Patents

Abstract

The embodiment of the utility model discloses an attenuator control panel and a GNSS satellite signal forwarding system, which comprises a shell, wherein a Thai bucket module, an amplifier, a power divider, an attenuator and an attenuator control panel are arranged in the shell; the input end of the amplifier is connected with the antenna, the output end of the amplifier is connected with the power divider, the power divider is connected with the bucket module and the attenuator, and the attenuator control board is connected with the attenuator; the amplifier collects and amplifies external satellite signals; the power divider divides the amplified satellite signal into two paths, one path is transmitted to the Taidou module, and the other path is transmitted to the attenuator; the Tai-Dou module collects current time information and position information when receiving the amplified satellite signals and transmits the current time information and position information to the attenuator control panel; the attenuator control panel analyzes and displays the time information and the position information, and outputs a corresponding attenuation value according to key operation so as to control the satellite signal amplified in the attenuator to be correspondingly attenuated. Therefore, the problem that satellite signals cannot be received and attenuated indoors in the prior art is solved.

Description

Attenuator control panel and GNSS satellite signal forwarding system

Technical Field

The utility model relates to the field of communication technology, especially, relate to an attenuator control panel and GNSS satellite signal transmit system.

Background

With the continuous development of world communication technology, Global Navigation Satellite System (GNSS) has become a global navigation positioning system. The application and popularization of the system cannot leave the research, development and production of terminal products. As is known, GNSS satellite signals are not received indoors, and to solve this problem, two schemes are mainly adopted at present: the simulator generates satellite-like downlink signals, and forwards downlink signals of actual satellites indoors.

Compared with the two schemes, the first scheme is realized by a special chip or an FPGA (field programmable gate array), a DSP (digital Signal processing) through an algorithm and a radio frequency module, the period is long, the cost is high, and a real-time satellite downlink Signal cannot be provided.

SUMMERY OF THE UTILITY MODEL

To the technical problem, the embodiment of the utility model provides an attenuator control panel and GNSS satellite signal transmit system to solve the problem that can not receive satellite signal and decay at present indoors.

The embodiment of the utility model provides an attenuator control panel, connect attenuator and tai dou module, it includes integrated power supply circuit, master control circuit, serial ports download circuit, memory, shows setting circuit and output circuit on a circuit board;

the power supply circuit is connected with the main control circuit, the serial port downloading circuit, the memory, the display setting circuit and the output circuit; the main control circuit is connected with the serial port downloading circuit, the memory, the display setting circuit and the output circuit; the serial port downloading circuit is connected with the Thai bucket module, and the output circuit is connected with the attenuator;

the power supply circuit steps down an input voltage and outputs a first voltage and a second voltage to supply power; the main control circuit analyzes the time information and the position information transmitted by the cloisonne bucket module and transmits the time information and the position information to the display setting circuit, and the serial port downloading circuit downloads a corresponding program to the main control circuit to upgrade the system; the display setting circuit displays position information, current time and attenuation value of the current attenuator; the display setting circuit also outputs a corresponding adjusting signal according to the key operation, the main control circuit adjusts the magnitude of the attenuation value according to the adjusting signal and outputs a corresponding attenuation value, and the main control circuit transmits the attenuation value to the memory for storage and outputs the attenuation value through the output circuit to control the attenuator to correspondingly attenuate.

Optionally, the attenuator control board further includes a download circuit connected to the main control circuit, and the download circuit downloads the program of the ARM chip and transmits the program to the main control circuit for program upgrading.

Optionally, the attenuator control board further includes a network circuit connected to the main control circuit, the network circuit receives the set attenuation parameter through an external network cable or a wireless network, and the main control circuit generates a corresponding attenuation value according to the attenuation parameter and outputs the attenuation value through the output circuit to control the attenuation corresponding to the attenuator.

Optionally, in the attenuator control board, the power circuit includes a first interface, a magnetic bead, a switching voltage adjusting chip, a voltage stabilizing chip, a first diode, a second diode, a first inductor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

a 1 st pin of the first interface is connected with a 24V power supply end, one end of a magnetic bead and the cathode of the first diode; the 2 nd pin of the first interface is grounded, the Vin pin of the switching voltage regulation chip is connected with the other end of the magnetic bead and the anode of the first capacitor, the anode of the first diode is connected with the cathode of the first capacitor and the ground, and the TAB pin of the switching voltage regulation chip is connected with the GND pin and the ground; a Feedback pin of the switching voltage regulation chip is connected with one end of the first inductor, the positive electrode of the second capacitor and the power supply end; an Output pin of the switching voltage regulating chip is connected with the negative electrode of the second diode and the other end of the first inductor; the On/Off pin of the switching voltage regulating chip is connected with the anode of the second diode, the cathode of the second capacitor and the ground; an IN pin of the voltage stabilizing chip is connected with the power supply end, the 5V power supply end and the anode of the third capacitor; and a GND pin of the voltage stabilizing chip is connected with the negative electrode of the third capacitor and the ground, an OUT pin of the voltage stabilizing chip is connected with the positive electrode of the fourth capacitor and the 3.3V power supply end, and the negative electrode of the fourth capacitor is grounded.

Optionally, in the attenuator control board, the serial port download circuit includes a USB to serial port chip, a second interface, a third interface, a USB interface, a first crystal oscillator, a first triode, a second triode, a first resistor, a second resistor, a third diode, a fifth capacitor, a sixth capacitor, and a seventh capacitor;

the TXD pin and the RXD pin of the USB serial-to-serial port chip are connected with the main control circuit, and the V3 pin of the USB serial-to-serial port chip is grounded through a fifth capacitor; the D + pin and the D-pin of the USB serial port conversion chip are respectively connected with the D + pin and the D-pin of the USB interface in a one-to-one manner; an XI pin of the USB serial-to-serial port chip is connected with one end of a first crystal oscillator and one end of a sixth capacitor, an XO pin of the USB serial-to-serial port chip is connected with the other end of the first crystal oscillator and one end of a seventh capacitor, the other end of the sixth capacitor is connected with the other end of the seventh capacitor and the ground, a VCC pin of the USB serial-to-serial port chip is connected with a power supply end, an RTS # pin of the USB serial-to-serial port chip is connected with an emitting electrode of a first triode and one end of a second resistor, and a DTR # pin of the USB serial-to-serial port chip; the collector of the first triode is connected with the cathode of the third diode and is also connected with a 3.3V power supply end through a first resistor; the positive electrode of the third diode is connected with the main control circuit, the emitting electrode of the second triode is connected with a 3.3V power supply end, the base electrode of the second triode is connected with the other end of the second resistor, the collecting electrode of the second triode is connected with the main control circuit through the third resistor, and the VCC pin of the USB interface is connected with the power supply end; the 1 st pin and the 3 rd pin of the second interface are both connected with the main control circuit; the 1 st pin and the 3 rd pin of the third interface J3 are both connected with the main control circuit.

Optionally, in the attenuator control board, the network circuit includes a PHY chip, an RMII interface, a second crystal oscillator, a second inductor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor;

the MDIO pin of the PHY chip is connected with the main control circuit through a fourth resistor, and the MDC pin of the PHY chip, the TXD0 pin, the TXD1 pin, the TXEN pin, the RXD0/MODE0 pin, the RXD1/MODE1 pin, the CSR _ DV/MODE2 pin and the nINT/REFCLKO pin of the PHY chip are connected with the main control circuit; the nRST pin of the PHY chip is grounded through a fifth resistor, the RBIAS pin of the PHY chip is grounded through a sixth resistor, the TXP pin of the PHY chip is connected with the 3.3VE end and the TD + pin of the RMII interface, the TXN pin of the PHY chip is connected with the 3.3VE end and the TD-pin of the RMII interface, the RXP pin of the PHY chip is connected with the 3.3VE end and the RD + pin of the RMII interface, the RXN pin of the PHY chip is connected with the 3.3VE end and the RD-pin of the RMII interface, the LED 1/REGOFFF pin of the PHY chip is connected with the LED (Y) pin A and the ground of the RMII interface, the LED2/nINTSEL pin of the PHY chip is connected with the LED (G) pin A and the ground of the RMII interface, the VDD1A pin of the PHY chip is connected with the VDD2A pin and the VDDD 3.3VE end, the IO pin of the PHY chip is connected with the 3-3V end, and; the XTAL1/CLKIN pin of the PHY chip is connected with one end of the seventh resistor, one end of the second crystal oscillator and one end of the ninth capacitor; the XTAL2 pin of the PHY chip is connected with the other end of the seventh resistor, the other end of the second crystal oscillator and one end of the eighth capacitor; the other end of the eighth capacitor is connected with the other end of the ninth capacitor and the ground, the TCT pin and the RCT pin of the RMII interface are both connected with the 3.3VE end, the LED (Y) pin and the K pin of the RMII interface are grounded through the eighth resistor, the LED (G) pin and the K pin of the RMII interface are grounded through the ninth resistor, the SHILLED pin and the CHS GND pin of the RMII interface are both grounded, one end of the second inductor is connected with the 3-3V end and one end of the eleventh capacitor, the other end of the second inductor is connected with the 3.3VE end and one end of the twelfth capacitor, and the other end of the eleventh capacitor is connected with the other end of the twelfth capacitor and the ground.

Optionally, in the attenuator control panel, the display setting circuit includes a liquid crystal screen and a knob key, the liquid crystal screen is located at a transparent window on one side of the housing and electrically connected to the main control circuit, and the knob key is disposed on the housing and electrically connected to the main control circuit;

the knob key generates a corresponding switching instruction and a corresponding adjusting instruction according to the key operation state, the main control circuit controls the liquid crystal display to display a corresponding interface according to the switching instruction, and controls the liquid crystal display to display a corresponding numerical value and information according to the adjusting instruction.

Optionally, in the attenuator control board, the TXP pin, the TXN pin, the RXP pin, and the RXN pin of the PHY chip may be connected to the 3.3VE terminal through a resistor, respectively.

Optionally, in the attenuator control board, the VDD1A pin, the VDD2A pin, and the VDDIO pin of the PHY chip are further grounded through a capacitor, respectively.

Optionally, in the attenuator control board, the TD + pin, the TD-pin, the RD + pin, and the RD-pin of the RMII interface RJ are also grounded through a capacitor, respectively.

The embodiment of the utility model provides a GNSS satellite signal forwarding system in the second aspect, which comprises a shell, wherein a cloisonne bucket module, an amplifier, a power divider, an attenuator and an attenuator control panel are arranged in the shell;

the input end of the amplifier is connected with the GNSS receiving antenna, the output end of the amplifier is connected with the power divider, the power divider is connected with the bucket module and the attenuator, and the attenuator control panel is connected with the attenuator;

the amplifier collects and amplifies external satellite signals; the power divider divides the amplified satellite signal into two paths, one path is transmitted to the Taidou module, and the other path is transmitted to the attenuator; the attenuator control panel controls the attenuation value of the attenuator, and the cloisonne bucket module collects current time information and position information and transmits the current time information and position information to the attenuator control panel when receiving the amplified satellite signal; the attenuator control panel analyzes and displays the time information and the position information, and outputs a corresponding attenuation value according to key operation so as to control the satellite signal amplified in the attenuator to be correspondingly attenuated.

Optionally, in the GNSS satellite signal forwarding system, the fighting module includes a baseband chip, a reading module, and an NMEA serial port; the reading module is connected with the baseband chip and the NMEA serial port, and the NMEA serial port is in communication connection with the attenuator control board;

the reading module receives current time information and position information of the amplified satellite signals and sends the current time information and position information to the attenuator control panel through the NMEA serial port to be displayed.

In the technical scheme provided by the embodiment of the utility model, the GNSS satellite signal forwarding system comprises a shell, wherein a cloisonne bucket module, an amplifier, a power divider, an attenuator and an attenuator control panel are arranged in the shell; the input end of the amplifier is connected with the antenna, the output end of the amplifier is connected with the power divider, the power divider is connected with the bucket module and the attenuator, and the attenuator control panel is connected with the attenuator; the amplifier collects and amplifies external satellite signals; the power divider divides the amplified satellite signal into two paths, one path is transmitted to the Taidou module, and the other path is transmitted to the attenuator; the cloisonne bucket module collects current time information and position information when receiving the amplified satellite signal and transmits the current time information and position information to the attenuator control panel; the attenuator control panel analyzes and displays the time information and the position information, and outputs a corresponding attenuation value according to key operation so as to control the satellite signal amplified in the attenuator to be correspondingly attenuated. Therefore, the problem that satellite signals cannot be received indoors in the prior art is solved.

Drawings

Fig. 1 is a schematic structural diagram of a GNSS satellite signal forwarding system according to an embodiment of the present invention.

Fig. 2 is a circuit diagram of a power supply circuit on the attenuator control board in the embodiment of the present invention.

Fig. 3 is a circuit diagram of a serial port downloading circuit on the attenuator control board in the embodiment of the present invention.

Fig. 4 is a circuit diagram of a network circuit on the attenuator control board according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. The embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts, belong to the protection scope of the present invention.

Referring to fig. 1, a GNSS satellite signal forwarding system provided in an embodiment of the present invention includes a housing, in which a taylor module 10, an attenuator control board 20 with a single channel of 31.5dB, an amplifier 30, a power divider 40, and an attenuator 50 are disposed; the input end of the amplifier 30 is connected with the GNSS receiving antenna, the output end of the amplifier 30 is connected with the power divider 40, the power divider 40 is connected with the bucket module 10 and the attenuator 50, and the attenuator control board 20 is connected with the attenuator 50. The amplifier 30 collects external satellite signals (i.e., GNSS satellite signals) and amplifies the signals; the power divider 40 divides the amplified satellite signal into two paths, one path is transmitted to the cloisonne bucket module 10, and the other path is transmitted to the attenuator 50; the cloisonne bucket module 10 collects current time information and position information when receiving the amplified satellite signal and transmits the current time information and position information to the attenuator control panel; the attenuator control board 20 analyzes and displays the time information and the position information, and outputs a corresponding attenuation value according to the key operation to control the satellite signal amplified in the attenuator to be attenuated correspondingly. The GNSS satellite signal forwarding system can attenuate and output signals of the attenuator 50, the attenuation range is 0-31.5dB, the minimum attenuation value at each time is 0.5dB, accurate attenuation can be provided for users, and the actual effect can be better simulated.

In this embodiment, the taiqi module 10 is a module with a model TD3020C, the TD3020C is a BDS B1/GPS L1 dual-mode navigation module based on a baseband chip with a model TD1010, and a dual-mode baseband chip and a dual-mode rf chip are integrated therein, so that a BDS B1 signal and a GPS L1 signal can be simultaneously accessed. The Taidou module is powered by 3.3V voltage, and supports power supply to the active antenna and software version upgrading. The cloisonne bucket module 10 supports three working modes, namely a single BDS B1 working mode, a single GPS L1 working mode and a BDS B1/GPS L1 dual-mode working mode, and can be switched among the three working modes by commands. The cloisonne bucket module 10 is provided with 2 paths of serial ports, as shown in figure 1; the NMEA serial port is used for outputting NMEA data, inputting instruction control and upgrading software (transmission upgrading program), and the default baud rate is 9600 bps; and the standby serial port is used for outputting data in a custom format and upgrading software, and the default baud rate is 115200 bps. In the embodiment, the BDS B1/GPS L1 dual-mode working mode and the NMEA serial port mode (baud rate 9600bps) of the fighting module 10 are used for control and information transmission. The attenuator control board 20 is provided with a serial port (a third interface J3 shown below) for serial communication with the tai-figu module 10, and when the reading module receives an amplified satellite signal transmitted by the power divider, the reading module reads current time information, BDS positioning information and GPS positioning information from the baseband chip, and transmits the current time information, BDS positioning information and GPS positioning information to the attenuator control board through the NMEA serial port for displaying the current time and position information.

In this embodiment, the attenuator control board 20 adjusts the attenuation value of the attenuator 50 through an external knob or network. The attenuator control panel adopts a network technology to realize remote monitoring of system equipment by a user. The main controller of the attenuator control panel adopts a chip which is produced by an Italian semiconductor and has the model of STM32F107VCT6, the chip is an ARM chip with 100 pins, the chip is provided with 5 paths of serial ports and an Ethernet MAC layer, and the ARM chip can realize the control of the attenuator through a network or a peripheral knob. The user only needs to add the PHY chip to realize network communication, thereby facilitating the circuit design of the user.

The attenuator control board comprises a power circuit 21, a main control circuit 22, a serial port downloading circuit 24, a memory 26, a display setting circuit 27 and an output circuit 28 which are integrated on a circuit board; the power supply circuit 21 is connected with the main control circuit 22, the serial port downloading circuit 24, the memory 26, the display setting circuit 27 and the output circuit 28; the main control circuit 22 is connected with the download circuit 23, the serial port download circuit 24, the memory 26, the display setting circuit 27 and the output circuit 28; the serial port downloading circuit 24 is connected with the fighting module 10, and the output circuit 28 is connected with the attenuator 50.

The power supply circuit 21 steps down an input voltage (24V voltage in this embodiment) and outputs a first voltage (5V voltage) and a second voltage (3.3V voltage) to supply power; the main control circuit 22 analyzes the time information and the position information transmitted by the fighting module and transmits the time information and the position information to the display setting circuit 27, the serial port downloading circuit 24 downloads a corresponding program to the main control circuit 22 through a serial port in the serial port downloading circuit to upgrade the system, and the memory 26 is used for storing the attenuation value of the current attenuator; the display setting circuit 27 is used for displaying BDS positioning information, GPS positioning information, current time, attenuation value of the current attenuator, and outputting a corresponding adjusting signal according to a key operation, the main control circuit adjusts the magnitude of the attenuation value according to the adjusting signal and outputs a corresponding attenuation value, and the main control circuit transmits the attenuation value to the memory for storage and outputs the attenuation value through the output circuit 28 to control the attenuation of the attenuator correspondingly.

In a further embodiment, the attenuator control board further includes a download circuit 23 connected to the main control circuit 22, and the download circuit downloads the program of the ARM chip through an SWD interface therein and transmits the program to the main control circuit 22 for program upgrading.

In a further embodiment, the attenuator control board further includes a network circuit 25 connected to the main control circuit 22, the network circuit 25 receives attenuation parameters set by a user through an external network cable or a wireless network, and the main control circuit generates corresponding attenuation values according to the attenuation parameters and outputs the attenuation values through an output circuit to control the attenuation of the attenuator.

Referring to fig. 2, the power circuit 21 includes a first interface J1, a magnetic bead F1, a switching voltage adjusting chip U1, a voltage stabilizing chip U2, a first diode D1 (preferably a TVS transistor), a second diode D2 (preferably a schottky diode), a first inductor L1, a first capacitor C1 (preferably 470 μ F), a second capacitor C2 (preferably 470 μ F), a third capacitor C3 (preferably 220 μ F), and a fourth capacitor C4 (preferably 220 μ F); the 1 st pin of the first interface J1 is connected with a 24V power supply end, one end of a magnetic bead F1 and the negative electrode of a first diode D1; the 2 nd pin of the first interface J1 is grounded, the Vin pin of the switching voltage regulation chip U1 is connected with the other end of the magnetic bead F1 and the anode of the first capacitor C1, the anode of the first diode D1 is connected with the cathode of the first capacitor C1 and the ground, and the TAB pin of the switching voltage regulation chip U1 is connected with the GND pin and the ground; a Feedback pin of the switching voltage regulating chip U1 is connected with one end of the first inductor L1, the positive electrode of the second capacitor C2 and the power supply end VBTN; an Output pin of the switching voltage regulation chip U1 is connected with the cathode of the second diode D2 and the other end of the first inductor L1; the On/Off pin of the switching voltage regulating chip U1 is connected with the anode of the second diode D2, the cathode of the second capacitor C2 and the ground; the IN pin of the voltage stabilizing chip U2 is connected with the power supply end VBTN, the 5V power supply end and the anode of the third capacitor C3; the GND pin of the voltage-stabilizing chip U2 is connected with the negative electrode of the third capacitor C3 and the ground, the OUT pin of the voltage-stabilizing chip U2 is connected with the positive electrode of the fourth capacitor C4 and the 3.3V power supply end, and the negative electrode of the fourth capacitor C4 is grounded.

The switching voltage regulation chip U1 that the model is LM2596 is adopted in this embodiment to realize the 5 ~ 24V voltage input of first interface J1 transmission, and LM2596 has wide voltage, and the ripple is little, characteristics such as power conversion rate height. The GNSS satellite signal forwarding system has an input voltage of 12V and an output voltage of 5V, and then converts the 5V voltage (from the power supply terminal VBTN) into a 3.3V voltage by using a forward low-voltage-drop voltage stabilization chip (i.e., a voltage stabilization chip U2) of model ASM 117-3.3. Wherein, 5V voltage is used for serial port circuit voltage, and 3.3V voltage is used for a GNSS satellite signal forwarding system. The first capacitor C1 to the fourth capacitor C4 respectively filter the voltage on the connected pins.

The main control circuit 22 includes a main controller (a chip with model number STM32F107VCT 6) and peripheral circuits (such as a first crystal oscillator circuit, a reset circuit, etc.), where the first crystal oscillator is a passive first crystal oscillator with a frequency of 25 MHZ. The download circuit 23 adopts an SWD mode for downloading, that is, it is composed of JTMS and JTCK two signal lines, power line and ground line, and completes the program download of ARM chip. The main control circuit 22 and the download circuit 23 are prior art and will not be described in detail here.

Referring to fig. 3, the serial port downloading circuit 24 includes a USB to serial port chip U3, a second interface J2, a third interface J3, a USB interface J4, a first crystal oscillator Y1, a first triode Q1, a second triode Q2, a first resistor R1, a second resistor R2, a third resistor R3, a third diode D3, a fifth capacitor C5, a sixth capacitor C6, and a seventh capacitor C7; the TXD pin and the RXD pin of the USB serial port conversion chip U3 are correspondingly connected with the RXD1 pin and the TXD1 pin of the main controller; the V3 pin of the USB serial-to-serial port chip U3 is grounded through a fifth capacitor C5; the D + pin and the D-pin of the USB-to-serial port chip U3 are respectively connected with the D + pin and the D-pin of the USB interface J4 in a one-to-one manner; an XI pin of the USB to serial port chip U3 is connected with one end of a first crystal oscillator Y1 and one end of a sixth capacitor C6, an XO pin of the USB to serial port chip U3 is connected with the other end of the first crystal oscillator Y1 and one end of a seventh capacitor C7, the other end of the sixth capacitor C6 is connected with the other end of the seventh capacitor C7 and the ground, a VCC pin of the USB to serial port chip U3 is connected with a power supply terminal VBTN, an RTS # pin of the USB to serial port chip U3 is connected with an emitter of a first triode Q1 and one end of a second resistor R2, and a DTR # pin of the USB to serial port chip U3 is connected with a base of a first triode Q1; the collector of the first triode Q1 is connected with the cathode of the third diode D3 and is also connected with the 3.3V power supply end through a first resistor R1; the positive electrode of the third diode D3 is connected with a RESET pin of the main controller, the emitting electrode of the second triode Q2 is connected with a 3.3V power supply end, the base electrode of the second triode Q2 is connected with the other end of the second resistor R2, the collector electrode of the second triode Q2 is connected with a BOOT0 pin of the main controller through the third resistor R3, and a VCC pin of the USB interface J4 is connected with a power supply end VBTN; the 1 st pin and the 3 rd pin of the second interface J2 are respectively connected with the RXD2 pin and the TXD2 pin of the master controller in a one-to-one mode; the 1 st pin and the 3 rd pin of the third interface J3 are respectively connected with the RXD3 pin and the TXD3 pin of the master controller in a one-to-one manner.

In this embodiment, the USB to serial port chip U3 is of a type CH340G, and CH340G is a USB bus adapter chip, so as to implement a USB to serial port or USB to print port function. CH340G supports either 5V or 3.3V voltage. When the 5V operating voltage is used, the VCC pin of the USB serial-to-serial port chip U3 inputs the 5V voltage of the power supply terminal VBTN, and the V3 pin should have an external power decoupling capacitor (i.e., the fifth capacitor C5) with a capacitance value of 4700pF or 0.01 uF. When the 3.3V working voltage is used, the V3 pin of the USB serial-to-serial port chip U3 is connected with the VCC pin through the chip internal control, the 3.3V voltage is input at the same time, and the working voltage of other circuits connected with the USB serial-to-serial port chip U3 cannot exceed 3.3V.

In this embodiment, 5V voltage is used to supply power to the USB to serial port chip U3 and is provided by the power supply terminal VBTN of the switching voltage adjusting chip U1. The USB interface J4 is a download port, and transmits USB signals to the USB serial-to-serial chip U3, and converts the USB signals into corresponding serial signals (TXD1 and RXD1) for output.

The serial port downloading circuit 24 not only has the function of a serial port, but also can realize downloading and upgrading of system software. The STM32F107 chip can be downloaded by a serial port besides an SWD mode downloading program, so that the circuit realizes system one-key downloading by utilizing the functions of the circuit. The third interface J3 is a serial port 3 channel, and a receiving end of the channel is connected with an output end of the taiqi fighting module 10, so as to read information of the current taiqi fighting module in real time, such as key information of big dipper, GPS, longitude and latitude, and the like. The second interface J2 is a spare serial port channel.

Referring to fig. 4, the network circuit 25 includes a PHY chip U4, an RMII interface RJ, a second crystal oscillator Y2, a second inductor L2, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9; the MDIO pin of the PHY chip U4 is connected with the EHT _ MDIO pin of the main controller through a fourth resistor R4, and the MDC pin of the PHY chip U4 is connected with the EHT _ MDC pin of the main controller; the TXD0 pin, the TXD1 pin, the TXEN pin, the RXD0/MODE0 pin, the RXD1/MODE1 pin, the CSR _ DV/MODE2 pin and the nINT/REFCLKO pin of the PHY chip U4 are respectively connected with the RMII _ TXD0 pin, the RMII _ TXD1 pin, the RMII _ TXEN pin, the RMII _ RXD0 pin, the RMII _ RXD1 pin, the RMII _ CSR pin and the RMII _ CLK pin of the main controller in a one-to-one manner; the nRST pin of PHY chip U4 is grounded through fifth resistor R5, the RBIAS pin of PHY chip U4 is grounded through sixth resistor R6, the TXP pin of PHY chip U4 is connected to the 3.3VE terminal and the TD + pin of RMII interface RJ, the TXN pin of PHY chip U4 is connected to the 3.3VE terminal and the TD-pin of RMII interface RJ, the RXP pin of PHY chip U4 is connected to the 3.3VE terminal and the RD + pin of RMII interface RJ, the RXN pin of PHY chip U4 is connected to the 3.3VE terminal and the RD-pin of RMII interface RJ, the LED1/REGOFF pin of PHY chip U4 is connected to the LED (y) pin of RMII interface RJ and ground, the LED 2/ndintert pin of PHY chip U4 is connected to the LED (g) pin of RMII interface RJ and ground, the VDD1 pin of PHY chip U4 is connected to the VDD2 pin and VDD2 pin of RMII interface RJ 3, the vddsel pin of PHY chip U399626 is connected to the tenth pin of RMII interface RJ 3, and the PHY chip is connected to the capacitor cr pin 5963C 3; the XTAL1/CLKIN pin of the PHY chip U4 is connected with one end of the seventh resistor R7, one end of the second crystal Y2 and one end of the ninth capacitor C9; the XTAL2 pin of the PHY chip U4 is connected with the other end of the seventh resistor R7, the other end of the second crystal Y2 and one end of the eighth capacitor C8; the other end of the eighth capacitor C8 is connected to the other end of the ninth capacitor C9 and ground, the TCT pin and the RCT pin of the RJ interface are both connected to the 3.3VE terminal, the led (y) K pin of the RJ interface is grounded through the eighth resistor R8, the led (g) K pin of the RJ interface is grounded through the ninth resistor R9, the SHILED pin and the CHS GND pin of the RJ interface are both grounded, one end of the second inductor L2 is connected to the 3-3V terminal and one end of the eleventh capacitor C11, the other end of the second inductor L2 is connected to the 3.3VE terminal and one end of the twelfth capacitor C12, and the other end of the eleventh capacitor C11 is connected to the other end of the twelfth capacitor C12 and ground.

Preferably, the TXP pin, TXN pin, RXP pin, RXN pin of the PHY chip U4 may also be connected to the 3.3VE terminal through a resistor, respectively, so as to pull up the four pins to a high level when no signal (TPTX ±, TPRX ±) is transmitted, thereby ensuring stable performance of the PHY chip U4 (model number LAN 8720). The VDD1A pin, the VDD2A pin and the VDDIO pin of the PHY chip U4 are grounded through a capacitor respectively, and power supplies of a 3.3VE end and a 3-3V end are filtered, so that power supply is more stable. TD + pin, TD-pin, RD + pin, RD-pin of the RMII interface RJ are also grounded through a capacitor respectively to filter signals (TPTX +/-and TPRx +/-) so as to stabilize the waveforms of the signals.

Here, EHT _ MDIO represents a data input signal, EHT _ MDC is a periodic clock signal, and RMII _ TXEN is a transmit enable signal. RMII _ TXD0 and RMII _ TXD1 represent data transmission signals, a set of 4 data signals. RMII _ RXD0 and RMII _ RXD1 represent data receive signals, a set of 4 data signals. RMII _ CSR is a carrier sense signal, RMII _ CLK is a continuous clock signal, EHT _ RESET is an Ethernet RESET signal, LINK _ LED is a network connection indicator light, and SPEED _ LED is a network transmission indicator light. TPTX +/-is a signal for connecting the PHY chip U4 with the transmitting end of the RJ interface, and TPRx +/-is a signal for connecting the PHY chip U4 with the receiving end of the RJ interface.

The network portion of the system uses a chip model LAN8720A as the PHY chip of the system. LAN8720A is a low power consumption 10/100M Ethernet PHY layer chip, the I/O pin voltage conforms to the IEEE802.3-2005 standard, and supports the communication with the Ethernet MAC layer through the RMII interface, and the built-in 10-BASE-T/100BASE-TX full duplex transmission module supports 10Mbps and 100 Mbps. The LAN8720A can support the automatic roll-over function of the HPAuto-MDIX by auto-negotiation with the best connection mode (speed and duplex mode) with the destination host, and the connection can be changed to direct connection or cross connection without changing the network cable.

The ARM chip (i.e., the main controller in the main control circuit 22) is connected to the LAN8720 through its internal ethernet bus, and communicates via the RMII interface. In this embodiment, a UDP mode (user datagram protocol) is used for performing point-to-point communication, so that a user can remotely monitor a device. In this embodiment, the LWIP network protocol stack is used to enable the user to control the attenuation value of the device through the network assistant, the user inputs the current attenuation value on the network assistant, and the device executes its operation after receiving the information.

The memory 26 is an AT24C02 chip with a size of 256 bytes, and the data can be stored for about 100 years, thus being sufficient for the system. The user can directly input and store the required attenuation value in the network command or the external knob key, and the attenuation value is still the current set value after rebooting every time. The chip can simultaneously store the IP address of the equipment, because the user needs more than one equipment, the IP address of each equipment is different, the user can change the IP address of the current equipment by a network assistant, and the changed IP address can be stored.

The display setting circuit 27 includes a liquid crystal screen and a knob key, the liquid crystal screen is located at a transparent window on one side of the casing and is electrically connected with the main control circuit, and the knob key is arranged on the casing and is electrically connected with the main control circuit (for example, an opening is formed on one side of the casing to expose a pressing part of the knob key, and a pin of the knob key is electrically connected with the X).

The method comprises the following steps that an LCD16032 LCD is adopted as a man-machine interaction interface, two functions are mainly displayed on the interface, firstly, after startup initialization is completed, the current geographic position and Beijing time are obtained to display the obtained main GNSS information, such as GPS (global positioning system), BD (Beidou) signals, CN value and longitude and latitude (integer part) of the current position, and the current year, month, day and Beijing time (such as 2018-11-2611:45:53) are obtained; the Beidou positioning interface (for example, BD:44dB N: 22E: 113 is displayed) and the GPS positioning interface (for example, GPS:46dB N: 22E: 113 is displayed) in the geographic position alternate. And the second is to display the attenuation value of the current attenuator (for example, display the current attenuation value: 10 dB). The two are switched by a knob key on the equipment, and after the system initialization is finished, the displayed interface is a GNSS information interface, wherein GPS signals and BD signals are alternately displayed. When a user presses a knob key, a switching instruction is generated, the main control circuit switches the system into an attenuator interface according to the switching instruction, an attenuation numerical interface is displayed on the liquid crystal screen at present, the user adjusts the attenuation value by rotating the knob key, and the main control circuit generates a corresponding attenuation value according to knob operation. The step pitch of the attenuation value of the system is 0.5dB, and when the user adjusts the output value of the attenuator, the knob key is pressed again; and the main control circuit detects that the knob key is triggered again, displays the adjusted attenuation value on the liquid crystal screen, stores the adjusted attenuation value in the AT24C02 chip, and restores the system interface to the previous GNSS information interface after the operation is finished.

The adjustment of the attenuation value can also be performed by sending an instruction by the network assistant, and the specific process is as follows:

firstly, opening a network debugging assistant at a computer end, selecting a UDP communication mode, connecting the current host IP and the target IP, initializing the host computer, adjusting the local IP to 192.168.1.252, and adjusting the address of the target host to 192.168.1.250 after clicking connection. After the network port of the equipment is connected with the network port of the host, a user can control the attenuator of the equipment by himself, input the numerical value to be attenuated at present, and the numerical value is received by the network circuit 29 after being clicked and sent, and is output to the attenuator through the output circuit, so that corresponding control can be realized.

The attenuation value range of the attenuator is 0-31.5dB, wherein the attenuation step distance is 0.5dB value, and the network assistant can send 0-63 characters to represent 0-31.5 dB. When the attenuation value of the equipment needs to be adjusted to 20dB by a user, the attenuation value is input on the network assistant only by 40, after the attenuation value is clicked and sent, the liquid crystal screen is converted into an attenuation value interface from the previous positioning interface of the Taidou module, and the attenuation value interface is automatically returned to the positioning interface of the Taidou module after 2s delay. The set attenuation value is automatically stored in a memory, and after each time of starting, the attenuation value is automatically displayed as the attenuation value set at the last time.

The IP address of the equipment (GNSS forwarding system) and the local (computer used by the user) IP can be adjusted by self, and the IP address of the equipment is adjusted: send character 130, device IP + +; send character 131, device IP- -; send character 132, device IP save. Local IP address adjustment: send character 133, local IP + +; send character 134, local IP- -; send character 135, local IP save. After the device IP is modified, the target IP of the network assistant needs to be adjusted to the modified IP, and the same is true after the local IP is modified. Local IP does not suggest frequent modifications by the user. When the user needs to use the switch to monitor the equipment, the current IP address of the equipment is modified.

In this embodiment, the output circuit 28 outputs data (0-31.5dB) by using a six-bit reverse schmitt trigger with a model number of 74HC14D, and the output data is kept stable. The output circuit 28 is connected to the attenuator for attenuation control.

To sum up, the attenuator control panel and GNSS satellite signal forwarding system provided by the present invention can lock sky satellite signals through an outdoor GNSS receiving antenna, and guide satellite signals from outdoors to indoors, or to other places where satellite signals cannot be received, so that a GNSS satellite receiving terminal can receive adjustable satellite signals, and various works to be completed outdoors can be completed indoors; the GNSS signal positioning and time service testing device is small in size, low in power consumption, easy to operate and powerful in function, and is suitable for occasions, such as terminal production testing workshops with GNSS functions, large base station laboratories, underground parking lots, tunnels, high-speed rail bus stations and the like, which need positioning, time service testing or use of GNSS signals, and GNSS/SINS group and navigation system testing.

The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims (9)

1. An attenuator control panel is connected with an attenuator and a Taidou module and is characterized by comprising a power circuit, a main control circuit, a serial port downloading circuit, a memory, a display setting circuit and an output circuit which are integrated on a circuit board;

the power supply circuit is connected with the main control circuit, the serial port downloading circuit, the memory, the display setting circuit and the output circuit; the main control circuit is connected with the serial port downloading circuit, the memory, the display setting circuit and the output circuit; the serial port downloading circuit is connected with the Thai bucket module, and the output circuit is connected with the attenuator;

the power supply circuit steps down an input voltage and outputs a first voltage and a second voltage to supply power; the main control circuit analyzes the time information and the position information transmitted by the cloisonne bucket module and transmits the time information and the position information to the display setting circuit; the display setting circuit displays position information, current time and attenuation value of the current attenuator; the display setting circuit also outputs a corresponding adjusting signal according to the key operation, the main control circuit adjusts the magnitude of the attenuation value according to the adjusting signal and outputs a corresponding attenuation value, and the main control circuit transmits the attenuation value to the memory for storage and outputs the attenuation value through the output circuit to control the attenuator to correspondingly attenuate.

2. The attenuator control board of claim 1, further comprising a network circuit connected to the main control circuit, wherein the network circuit receives the set attenuation parameters through an external network cable or a wireless network, and the main control circuit generates corresponding attenuation values according to the attenuation parameters and outputs the attenuation values through the output circuit to control the corresponding attenuation of the attenuator.

3. The attenuator control board of claim 2, wherein the power circuit comprises a first interface, a magnetic bead, a switching voltage regulation chip, a first diode, a second diode, a first inductor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

a 1 st pin of the first interface is connected with a 24V power supply end, one end of a magnetic bead and the cathode of the first diode; the 2 nd pin of the first interface is grounded, the Vin pin of the switching voltage regulation chip is connected with the other end of the magnetic bead and the anode of the first capacitor, the anode of the first diode is connected with the cathode of the first capacitor and the ground, and the TAB pin of the switching voltage regulation chip is connected with the GND pin and the ground; a Feedback pin of the switching voltage regulation chip is connected with one end of the first inductor, the positive electrode of the second capacitor and the power supply end; an Output pin of the switching voltage regulating chip is connected with the negative electrode of the second diode and the other end of the first inductor; the On/Off pin of the switching voltage regulating chip is connected with the anode of the second diode, the cathode of the second capacitor and the ground; an IN pin of the voltage stabilizing chip is connected with the power supply end, the 5V power supply end and the anode of the third capacitor; and a GND pin of the voltage stabilizing chip is connected with the negative electrode of the third capacitor and the ground, an OUT pin of the voltage stabilizing chip is connected with the positive electrode of the fourth capacitor and the 3.3V power supply end, and the negative electrode of the fourth capacitor is grounded.

4. The attenuator control board of claim 3, wherein the serial port download circuit comprises a USB to serial port chip, a second interface, a third interface, a USB interface, a first crystal oscillator, a first triode, a second triode, a first resistor, a second resistor, a third diode, a fifth capacitor, a sixth capacitor and a seventh capacitor;

the TXD pin and the RXD pin of the USB serial-to-serial port chip are connected with the main control circuit, and the V3 pin of the USB serial-to-serial port chip is grounded through a fifth capacitor; the D + pin and the D-pin of the USB serial port conversion chip are respectively connected with the D + pin and the D-pin of the USB interface in a one-to-one manner; an XI pin of the USB serial-to-serial port chip is connected with one end of a first crystal oscillator and one end of a sixth capacitor, an XO pin of the USB serial-to-serial port chip is connected with the other end of the first crystal oscillator and one end of a seventh capacitor, the other end of the sixth capacitor is connected with the other end of the seventh capacitor and the ground, a VCC pin of the USB serial-to-serial port chip is connected with a power supply end, an RTS # pin of the USB serial-to-serial port chip is connected with an emitting electrode of a first triode and one end of a second resistor, and a DTR # pin of the USB serial-to-serial port chip; the collector of the first triode is connected with the cathode of the third diode and is also connected with a 3.3V power supply end through a first resistor; the positive electrode of the third diode is connected with the main control circuit, the emitting electrode of the second triode is connected with a 3.3V power supply end, the base electrode of the second triode is connected with the other end of the second resistor, the collecting electrode of the second triode is connected with the main control circuit through the third resistor, and the VCC pin of the USB interface is connected with the power supply end; the 1 st pin and the 3 rd pin of the second interface are both connected with the main control circuit; the 1 st pin and the 3 rd pin of the third interface J3 are both connected with the main control circuit.

5. The attenuator control board of claim 4, wherein the network circuit comprises a PHY chip, an RMII interface, a second crystal oscillator, a second inductor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor;

the MDIO pin of the PHY chip is connected with the main control circuit through a fourth resistor, and the MDC pin, the TXD0 pin, the TXD1 pin, the TXEN pin, the RXD0/MODE0 pin, the RXD1/MODE1 pin, the CSR _ DV/MODE2 pin and the nINT/REFCLKO pin of the PHY chip are connected with the main control circuit; the nRST pin of the PHY chip is grounded through a fifth resistor, the RBIAS pin of the PHY chip is grounded through a sixth resistor, the TXP pin of the PHY chip is connected with the 3.3VE end and the TD + pin of the RMII interface, the TXN pin of the PHY chip is connected with the 3.3VE end and the TD-pin of the RMII interface, the RXP pin of the PHY chip is connected with the 3.3VE end and the RD + pin of the RMII interface, the RXN pin of the PHY chip is connected with the 3.3VE end and the RD-pin of the RMII interface, the LED 1/REGOFFF pin of the PHY chip is connected with the LED (Y) pin A and the ground of the RMII interface, the LED2/nINTSEL pin of the PHY chip is connected with the LED (G) pin A and the ground of the RMII interface, the VDD1A pin of the PHY chip is connected with the VDD2A pin and the VDDD 3.3VE end, the IO pin of the PHY chip is connected with the 3-3V end, and; the XTAL1/CLKIN pin of the PHY chip is connected with one end of the seventh resistor, one end of the second crystal oscillator and one end of the ninth capacitor; the XTAL2 pin of the PHY chip is connected with the other end of the seventh resistor, the other end of the second crystal oscillator and one end of the eighth capacitor; the other end of the eighth capacitor is connected with the other end of the ninth capacitor and the ground, the TCT pin and the RCT pin of the RMII interface are both connected with the 3.3VE end, the LED (Y) pin and the K pin of the RMII interface are grounded through the eighth resistor, the LED (G) pin and the K pin of the RMII interface are grounded through the ninth resistor, the SHILLED pin and the CHS GND pin of the RMII interface are both grounded, one end of the second inductor is connected with the 3-3V end and one end of the eleventh capacitor, the other end of the second inductor is connected with the 3.3VE end and one end of the twelfth capacitor, and the other end of the eleventh capacitor is connected with the other end of the twelfth capacitor and the ground.

6. The attenuator control board according to claim 1, wherein the display setting circuit includes a liquid crystal screen and a knob button, the liquid crystal screen is located at a transparent window on one side of the housing and electrically connected with the main control circuit, and the knob button is disposed on the housing and electrically connected with the main control circuit;

the knob key generates a corresponding switching instruction and a corresponding adjusting instruction according to the key operation state, the main control circuit controls the liquid crystal display to display a corresponding interface according to the switching instruction, and controls the liquid crystal display to display a corresponding numerical value and information according to the adjusting instruction.

7. The attenuator control board according to claim 5, wherein the TXP pin, the TXN pin, the RXP pin and the RXN pin of the PHY chip are respectively connected to the 3.3VE terminal through a resistor.

8. A GNSS satellite signal repeating system, which comprises a housing, wherein a cloisonne bucket module, an amplifier, a power divider, an attenuator and an attenuator control board according to any one of claims 1-7 are arranged in the housing;

the input end of the amplifier is connected with the GNSS receiving antenna, the output end of the amplifier is connected with the power divider, the power divider is connected with the bucket module and the attenuator, and the attenuator control panel is connected with the attenuator;

the amplifier collects and amplifies external satellite signals; the power divider divides the amplified satellite signal into two paths, one path is transmitted to the Taidou module, and the other path is transmitted to the attenuator; the cloisonne bucket module collects current time information and position information when receiving the amplified satellite signal and transmits the current time information and position information to the attenuator control panel; the attenuator control panel analyzes and displays the time information and the position information, and outputs a corresponding attenuation value according to key operation so as to control the satellite signal amplified in the attenuator to be correspondingly attenuated.

9. The GNSS satellite signal forwarding system of claim 8, wherein the taiqi module comprises a baseband chip, a reading module and an NMEA serial port; the reading module is connected with the baseband chip and the NMEA serial port, and the NMEA serial port is in communication connection with the attenuator control board;

and when receiving the amplified satellite signal, the reading module reads the current time information and position information from the baseband chip and sends the current time information and position information to the attenuator control panel through the NMEA serial port for displaying.

Images