CN210157281U

CN210157281U - USB digital television signal source

Info

Publication number: CN210157281U
Application number: CN201921189707.6U
Authority: CN
Inventors: 王威; 曾文斌; 侯啸林
Original assignee: Shenzhen Qiyuan Core Technology Co Ltd
Current assignee: Shenzhen Qiyuan Core Technology Co Ltd
Priority date: 2019-07-25
Filing date: 2019-07-25
Publication date: 2020-03-17
Anticipated expiration: 2029-07-25

Abstract

The utility model discloses a USB digital television signal source, by the USB3.0 interface is as the data communication media, thereby convenience of customers carries out the information interaction of USB data with USB digital television signal source and outside host computer, conveniently carry, can realize converting outside USB data into the parallel data that FPGA can discern through first USB controller, can realize encapsulating the parallel data that FPGA can discern into USB data through the second USB controller, thereby can transmit for outside host computer, can carry out the internal parameter through FPGA according to the parameter configuration data in the USB data of outside host computer transmission and rewrite, in order to realize different standard transformation, and then can carry out data processing according to software radio technologies such as the code that different standard standards define, interweave, map and the modulation, and then realize the output with different standard signal through the radio frequency module; the utility model discloses when the television signal of multiple standard can be exported, multiple test demand is satisfied in can also portablely shifting.

Description

USB digital television signal source

Technical Field

The utility model relates to a signal source technical field especially relates to a USB digital television signal source.

Background

With the continuous popularization of digital televisions in China, the technical development of television signal sources is brought. All instruments that generate test signals may be referred to collectively as signal sources. The digital television signal source is used for providing a high-quality standard test signal, the product application field mainly comprises chip research and development and verification test, scheme research and development and verification, product research and development test, product verification and demonstration, product production test and quality inspection test and the like in the digital television industry, and the whole digital television industry chain is almost covered. The digital television signal source has the functions of processing data of a digital television TS code stream according to software radio technologies such as coding, interleaving, mapping and modulation defined by different system standards, finally outputting image audio data of the digital television TS code stream in a radio frequency RF mode through radio frequency microwave technologies such as analog modulation, frequency conversion, filtering and the like, and providing the image audio data for various digital television receiving devices (such as televisions, set-top boxes, handheld terminals, vehicle-mounted receivers and the like) to demodulate and restore the image audio data.

The existing digital television signal source can only support signals of 1 or 2 standard systems, because the existing digital television signal source adopts an Application Specific Integrated Circuit (ASIC) chip-see fig. 1, the ASIC chip is an ASIC chip for special applications, and is an Integrated Circuit designed for special purposes, so the standard signals that can be received by the ASIC chip are fixed, and output of standard signals of various standard systems cannot be realized, and further various test requirements cannot be met.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a USB digital television signal source can realize the output of multiple standard signal, satisfies multiple test demand.

In order to achieve the above object, a USB digital television signal source is provided, which includes a USB3.0 interface, a first USB controller, a second USB controller, an FPGA chip and a radio frequency module, wherein:

the USB3.0 interface is used for sending USB data to an external upper computer or receiving the USB data sent by the external upper computer;

the first USB controller is connected with the USB3.0 interface and the FPGA chip and is used for converting USB data received through the USB3.0 interface into parallel data and sending the parallel data to the FPGA chip;

the second USB controller is connected with the USB3.0 interface and the FPGA chip and is used for converting parallel data sent by the FPGA chip into USB data so as to send the USB data through the USB3.0 interface;

the FPGA chip is used for receiving the parallel data converted by the first USB controller, processing the data and outputting a digital signal;

the radio frequency module is connected with the FPGA chip and used for processing the digital signal and outputting a radio frequency signal.

In one possible implementation manner, the radio frequency module includes: two DAC chips, baseband filter, integrated PLL's IQ modulator and frequency conversion filtering processing circuit, wherein:

the double DAC chip is connected with the FPGA chip and used for converting the digital signals into analog signals to be output;

the baseband filter is connected with the double DAC chip and is used for filtering the analog signal and outputting a filtered signal;

the IQ modulator of the integrated PLL is connected with the baseband filter and used for modulating and outputting the filtered signal and outputting a modulation signal;

the frequency conversion filtering processing circuit is connected with the IQ modulator of the integrated PLL and is used for filtering the modulation signal and outputting a radio frequency signal.

In one possible implementation manner, the USB digital television signal source further includes:

and the flash memory is connected with the FPGA chip and used for storing compensation data for error calibration of the FPGA chip on the IQ modulator integrated with the PLL.

In one possible implementation manner, the variable frequency filtering processing circuit includes:

the filtering module comprises N groups of filtering branches and is used for filtering the modulation signals in each group of signal frequency ranges, wherein the signal frequency ranges corresponding to the N groups of filtering branches are different, the signal frequencies processed by the N groups of filtering branches are all larger than or equal to 100MHZ, and N is a positive integer larger than or equal to 2;

the first radio frequency switch is connected with the IQ modulator of the integrated PLL and used for receiving the modulation signal, switching according to the signal frequency of the modulation signal and connecting one end of the corresponding group of filtering branches;

and the second radio frequency switch is connected with the other end of the filtering branch according to the group of filtering branches connected with the first radio frequency switch and is used for outputting the radio frequency signals after filtering processing.

In one possible implementation manner, the filtering module further includes:

a low frequency filtering branch connected between the first radio frequency switch and the second radio frequency switch, wherein the low frequency filtering branch comprises: mixer, fixed frequency phase-locked loop and low pass filter, wherein:

the mixer is connected with one end of the low-frequency filtering branch and used for outputting a difference signal of a modulation signal and a fixed preset frequency sinusoidal signal, wherein the frequency of the difference signal is within a preset frequency range, and the preset frequency range is 40 MHz-100 MHz;

the fixed frequency phase-locked loop is connected with the frequency mixer and is used for generating a fixed preset frequency sinusoidal signal;

and the low-pass filter is connected with the other end of the low-frequency filtering branch and is used for filtering signals outside the preset frequency range.

In one possible implementation manner, the variable frequency filter processing circuit further includes: the device comprises a first digital step attenuator, a first power amplifier, an amplitude equalizer, a second power amplifier and a second digital step attenuator; wherein:

the first digital step attenuator is connected with the second radio frequency switch and used for attenuating the radio frequency signal after filtering processing and outputting a first attenuated signal;

the first power amplifier is connected with the first digital step attenuator and is used for amplifying the first attenuation signal and outputting a first amplified signal;

the amplitude equalizer is connected with the first power amplifier and used for compensating the first amplified signal and outputting a compensation signal;

the second power amplifier is connected with the amplitude equalizer and used for amplifying the compensation signal and outputting a second amplified signal;

and the second digital step attenuator is connected with the second power amplifier and used for attenuating a second amplified signal and outputting a second attenuated signal.

In one possible implementation manner, the variable frequency filter processing circuit further includes:

n group decay range switching module, N is for being greater than or equal to 1 positive integer, wherein, arbitrary group decay range switching module includes:

a third radio frequency switch connected with the second digital step attenuator;

the fourth radio frequency switch is matched with the third radio frequency switch and used for gating the attenuation module or the first straight-through branch through the matching between the third radio frequency switch and the fourth radio frequency switch;

the attenuation module is connected between the third radio frequency switch and the fourth radio frequency switch and is used for carrying out non-zero preset decibel attenuation on the second attenuation signal;

and the first straight-through branch is connected between the third radio frequency switch and the fourth radio frequency switch and is used for carrying out zero point division shell attenuation on the second attenuated signal.

the fifth radio frequency switch is connected with the third digital step attenuator;

the sixth radio frequency switch is matched with the fifth radio frequency switch and used for switching on the third power amplifier or the second through branch through the matching between the fifth radio frequency switch and the sixth radio frequency switch;

the third digital step attenuator is connected between the fourth radio frequency switch and the fifth radio frequency switch and is used for compensating different frequency powers of signals output by the attenuation range switching module and outputting a third compensation signal;

the third power amplifier is connected between the fifth radio frequency switch and the sixth radio frequency switch and used for amplifying the third compensation signal and outputting a corresponding radio frequency signal;

and the second straight-through branch is connected between the fifth radio frequency switch and the sixth radio frequency switch and is used for carrying out zero point-decibel attenuation on the signal output by the attenuation range switching module and outputting a corresponding radio frequency signal.

In one possible implementation manner, the FPGA chip is connected to the IQ modulator, the first rf switch, the second rf switch, the third rf switch, the fourth rf switch, the fifth rf switch, the sixth rf switch, the first digital step attenuator, the second digital step attenuator, and the third digital step attenuator of the integrated PLL, respectively.

In one possible implementation, the USB digital television signal source further includes an ASI line equalizer and an ASI line driver, wherein,

the ASI line equalizer is connected with the FPGA chip to realize TS code stream data input;

and the ASI line driver is connected with the FPGA chip to realize TS code stream data output.

Implement the embodiment of the utility model provides a following beneficial effect has:

the embodiment of the utility model provides a USB digital television signal source, including USB3.0 interface, first USB controller, second USB controller, FPGA chip and radio frequency module, wherein: the USB3.0 interface is used for sending USB data to an external upper computer or receiving the USB data sent by the external upper computer, wherein the USB data comprises TS (transport stream) code stream data or configuration data, and the configuration data is parameter configuration data corresponding to different standard standards; the first USB controller is used for converting the USB data received through the USB3.0 interface into parallel data and sending the parallel data to the FPGA chip; the second USB controller is used for converting the parallel data sent by the FPGA chip into USB data so as to send the USB data through the USB3.0 interface; the FPGA chip is used for receiving the parallel data converted by the first USB controller and performing data processing, wherein the data processing comprises updating parameters according to the configuration data to complete the replacement of the current standard, and/or processing TS code stream data according to the current standard to output digital signals; the radio frequency module is used for processing the digital signal and outputting a radio frequency signal. The utility model discloses in, by the USB3.0 interface is as data communication media to convenience of customers carries out the information interaction of USB data with USB digital television signal source and outside host computer, conveniently carries, can realize converting outside USB data into the parallel data that FPGA can discern through first USB controller, just can realize encapsulating into USB data with the parallel data that FPGA can discern through the second USB controller, thereby can transmit for outside host computer; internal parameter rewriting can be carried out according to parameter configuration data in USB data transmitted by an external upper computer through the FPGA so as to realize standard transformation of different systems, data processing can be further carried out according to software radio technologies such as coding, interweaving, mapping and modulation defined by standards of different systems, and then output of standard signals of different systems is realized through a radio frequency module; the utility model discloses when the television signal of multiple standard can be exported, multiple test demand is satisfied in can also portablely shifting.

Drawings

FIG. 1 is a schematic diagram of a digital television signal source of a prior art design;

fig. 2 is a schematic structural diagram of a USB digital television signal source according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another USB digital television signal source according to an embodiment of the present invention;

fig. 4 is a schematic diagram of an ideal I, Q quadrature modulator in an embodiment of the invention;

fig. 5 is a schematic diagram of an IQ modulator calibration according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

As described in the background art, the ASIC chip is used to implement the digital television signal source in the prior art, so that the conventional digital television signal source can only support 1 or 2 standard signals, and cannot output standard signals of multiple standards and meet multiple test requirements. The inventor, in studying this problem, considers using an FPGA chip instead of an ASIC chip to implement a digital television signal source, therefore, the digital television signal source can support signals with a plurality of standard systems, output signals with a plurality of standard systems and meet a plurality of test requirements, in order to realize portability of products, the inventor uses USB3.0 as a data transmission interface, the FPGA chip and the USB3.0 interface can not directly carry out data transmission, in order to solve the problem, the inventor introduces a first USB controller and a second USB controller, wherein the first USB controller is used for converting USB data received through the USB3.0 interface into parallel data and sending the parallel data to the FPGA chip for processing, and the second USB controller is used for converting the parallel data sent by the FPGA chip into USB data, the data is sent out through the USB3.0 interface, so that the problem of data transmission between the FPGA chip and the USB3.0 interface is solved; it can be seen from the inventive concept of the present invention that the present invention is a contribution to the prior art in that the FPGA chip is used to replace the ASIC chip to realize the digital television signal source, and the first USB controller and the second USB controller are introduced to solve the data transmission problem between the FPGA chip and the USB3.0 interface.

Referring to fig. 2, an embodiment of the present invention provides a USB digital television signal source, which includes a USB3.0 interface 01, a first USB controller 02, a second USB controller 03, an FPGA chip 04, and a radio frequency module 05, which are described in detail below.

The USB3.0 interface 01 is configured to send USB data to an external upper computer, or receive USB data sent by the external upper computer, where the USB data includes TS code stream data or configuration data, and the configuration data is parameter configuration data corresponding to different standard standards.

The USB3.0 interface is a high-speed data interface with small volume, is convenient to plug and unplug, so that the USB digital television signal source is convenient to carry and transfer, and can be connected with a common configuration notebook computer for use.

In one embodiment, the USB data includes TS code stream data, configuration data, or control commands. The TS code stream data is MPEG2 format data in DVD programs, and many types of data such as video, audio, custom information, etc. can be included in the TS code stream data. The configuration data is parameter configuration data corresponding to different standard systems, and controls the FPGA to change parameters, for example, when DVB-C standard data is to be output, the configuration data may include related parameter data of software radio technologies such as coding, interleaving, mapping, and modulation defined by the DVB-C standard system, and the FPGA rewrites the parameters according to the related parameter data, so that the FPGA can process and output the DVB-C standard data. The control command is a connection control command of an external upper computer to internal devices of a USB digital television signal source, and the FPGA receives the control command and controls whether the devices such as the IQ modulator 10, the first radio frequency switch 13, the second radio frequency switch 14, the third radio frequency switch 28, the fourth radio frequency switch 29, the fifth radio frequency switch 33, the sixth radio frequency switch 34, the first digital step attenuator 20, the second digital step attenuator 24 and the third digital step attenuator 30 of the integrated PLL are connected or not through a control line interface. For example, when the control command is to disconnect the first digital step attenuator 20, the FPGA control line interface outputs a corresponding command to control the disconnection of the first digital step attenuator 20.

The first USB controller 02 is configured to convert USB data received through the USB3.0 interface 01 into parallel data, and send the parallel data to the FPGA chip 04. The second USB controller 03 is configured to convert the parallel data sent by the FPGA chip 04 into USB data, and send the USB data through the USB3.0 interface 01.

In one embodiment, the first USB controller 02 and the second USB controller 03 are configured to perform data conversion. The first USB controller 02 converts serial data of the USB into parallel data, and sends the parallel data to the FPGA chip 04. The second USB controller 03 converts the received parallel data of the FPGA into serial data, encapsulates the serial data into a format specified by a USB protocol, and transmits the serial data to the USB3.0 interface 01. The first USB controller 02 and the second USB controller 03 may be designed as a general USB controller, i.e. integrated into a USB interface chip.

The FPGA chip 04 is configured to receive the parallel data converted by the first USB controller 02 and perform data processing, where the data processing includes updating parameters according to the configuration data to complete replacement of a current standard, and/or processing TS code stream data according to the current standard to output a digital signal.

In one possible implementation, the FPGA chip 04 includes a control line interface. The control line interfaces are respectively connected with the IQ modulator 10, the first radio frequency switch 13, the second radio frequency switch 14, the third radio frequency switch 28, the fourth radio frequency switch 29, the fifth radio frequency switch 33, the sixth radio frequency switch 34, the first digital step attenuator 20, the second digital step attenuator 24 and the third digital step attenuator 30 of the integrated PLL, so that the FPGA chip 04 is controlled according to the received control command.

It should be noted that the FPGA chip 04 is a field programmable gate array, and the FPGA chip 04 has a large number of flip-flops and I/O pins therein, and the working state thereof is set by a program stored in an on-chip RAM, so that the on-chip RAM needs to be programmed during working. The user can adopt different programming modes according to different configuration modes. When power is on, the FPGA chip 04 reads data in an EPROM (erasable programmable read only memory) into an on-chip programming RAM (random access memory), and after configuration is completed, the FPGA chip 04 enters a working state. After power failure, the FPGA is restored to a white chip, and the internal logic relation disappears, so that the FPGA chip 04 can be repeatedly used. The programming of the FPGA chip 04 does not need a dedicated FPGA programmer, and only needs a general EPROM and PROM programmer. When the function of the FPGA chip 04 needs to be modified, only one EPROM needs to be replaced. Thus, different circuit functions can be generated by the same FPGA and different programming data. Thus, the use of FPGAs is very flexible.

In one possible implementation manner, the USB3.0 interface 01 receives USB data of an external upper computer, after configuration data included in the USB data is converted into parallel data by the first USB controller 02, the parallel data is received by the configuration interface on the FPGA chip 04, and the content of the FPGA chip 04 is changed according to the parallel data, that is, corresponding parameters and programs are modified, so that the FPGA chip 04 can output corresponding radio frequency signals according to a standard preset in the configuration data. Therefore, the data of the TS code stream of the digital television is processed according to software radio technologies such as coding, interleaving, mapping, modulation and the like defined by different standard standards (such as DVB-C, DVB-C2, DVB-T/H, DVB-T2, DVB-S, DVB-S2, DVB-S2X, DTMB, CMMB, ATSC, ATSC-M/H, J.83B, ISDB-T, ISDB-S and the like). Referring to fig. 2, the USB digital television signal source further includes a memory, where the memory may be an EPROM or a DDR3, and when the memory is a DDR3, the USB digital television signal source may perform data streaming with the DDR34 through a DDR3 interface of the FPGA.

It should be noted that the embodiment of the present invention provides a USB digital television signal source, the structure according to the USB digital television signal source realizes carrying out data processing output according to different standard standards on digital television TS code stream data, that is, by setting up a USB3.0 interface 01, a first USB controller 02 and a second USB controller 03 to receive USB data transmitted from an external host computer, and overcome the existing prejudice to replace the conventionally used ASIC chip into an FPGA chip 04, fully utilize the device characteristics that the FPGA chip 04 can change the internal parameter program of the chip, receive configuration data transmitted from the USB3.0 interface 01 to carry out program modification, realize standard replacement of the FPGA chip 04 standard, carry out data processing according to TS code stream data transmitted from the USB3.0 interface 01, and output corresponding digital television signals. Therefore, the replacement of the digital television signal system standard can be realized through the structure that the USB3.0 interface 01 is connected with the FPGA chip 04 through the first USB controller 02 and the second USB controller 03 respectively.

In one possible implementation, the USB digital television signal source further includes an ASI line equalizer 06 and an ASI line driver 07. The ASI line equalizer 06 is used for connecting an ASI interface of the FPGA chip 04 to realize TS code stream data input. The ASI line driver 07 is used to connect to an ASI interface of the FPGA chip 04, and to output TS code stream data.

The universal USB3.0 interface 01, the specific ASI interface and the asynchronous serial interface are arranged on the USB digital television signal source, and a standard DVB interface for transmitting code streams is arranged on the asynchronous serial interface so as to meet the requirement that the ASI interface of user equipment is connected with the ASI interface of the FPGA chip 04.

The radio frequency module 05 is configured to process the digital signal and output a radio frequency signal.

In one possible implementation manner, the output radio frequency signal may be sent to various digital television receiving devices (such as a television, a set-top box, a handheld terminal, a vehicle-mounted receiver, and the like) to demodulate and restore the video and audio data. The USB digital television signal source can output test signals of various standards of different systems.

Referring to fig. 3, in one possible implementation, the rf module 05 includes a dual DAC chip 08, a baseband filter 09, an IQ modulator 10 integrated with PLL, and a frequency conversion filter processing circuit 11, which are described in detail below.

The dual DAC chip 08 is used for converting the digital signal into an analog signal and outputting the analog signal. In one possible implementation, a 12-bit or 14-bit dual DAC chip 08 is used to output I, Q two paths of baseband signals. The baseband filter 09 filters the I, Q baseband signals, that is, the baseband filter 09 filters the analog signals and outputs the filtered signals, wherein the filtering includes filtering the output sampling clock leakage and/or filtering the image interference. The PLL-integrated IQ modulator 10 is configured to modulate and output the filtered signal, and output the modulated signal. The use of an IQ modulator integrated with a PLL (phase locked loop) can reduce the product volume. The frequency conversion filtering processing circuit 11 is configured to perform filtering processing on the modulation signal output by the IQ modulator 10 integrated with the PLL, and output a radio frequency signal.

Referring to fig. 4, fig. 4 is a schematic diagram of an ideal IQ quadrature modulator consisting of two multipliers, an adding (subtracting) device and a quadrature phase shifter. Wherein cos ω t represents a local oscillator, which is generally implemented by using a PLL (phase locked loop). The quadrature phase shifter shifts the local oscillator by 90 degrees, namely, cos ω t is converted into sin ω t. The two input ends respectively represent I, Q two paths of baseband signals. The output of an ideal modulator is Y ═ cos (ω t) -Q × (ω t). I, Q represent the two baseband signals at the input end respectively. The modulator can realize the displacement of the baseband energy to the radio frequency band. In practice, the IQ modulator chip is not ideal, and therefore the signal is distorted, resulting in poor signal quality. Therefore, the utility model discloses a FPGA chip 04 and flash memory 35 carry out the error calibration, specifically explain below.

In one possible implementation, the USB digital television signal source further includes a flash memory 35. The flash memory 35 is configured to communicate with the FPGA chip 04 through an SPI interface on the FPGA chip 04, and store compensation data for the FPGA chip 04 to perform error calibration on the PLL-integrated IQ modulator 10; wherein the compensation data are compensation values for IQ phase, amplitude and DC component of the modulation signal at each frequency point. The Flash Memory 35 may be a non-volatile semiconductor Memory, and data is not lost even when power is off. The output frequency range of the PLL-integrated IQ modulator 10 is 100MHz to 2200MHz, and the quadrature, amplitude, and dc offset errors of the modulator are calibrated by a correction module inside the FPGA chip 04, so that a higher MER (modulation error ratio) can be obtained finally. The calibration module inside the FPGA chip 04 calibrates by reading the compensation data on the flash memory 35.

Referring to fig. 5, the correction process of the PLL (phase locked loop) integrated IQ modulator is described in detail below: an external upper computer firstly sends a control command through a USB3.0 interface 01, a USB digital television signal source outputs a modulation signal at a set frequency point, an IQ modulator 10 of an integrated PLL is connected to an external equipment vector signal analyzer, the vector signal analyzer analyzes IQ phase, amplitude and direct current characteristics of the modulation signal, and error data are transmitted to the upper computer. The upper computer judges whether the error is in an allowable range, if not, a control command is transmitted to the FPGA chip 04 through the USB3.0 interface 01, a correction module in the FPGA chip 04 calculates the data quantity to be compensated according to the error, and the compensation value is combined into I, Q baseband signals through a DAC data interface of the FPGA chip 04 until the error signal measured by the vector signal analyzer is in the allowable range. At this time, the calibration module inside the FPGA chip 04 writes the compensation data (amplitude, phase, and dc) at the frequency point into the flash memory 35 through the SPI interface. This calibration process is only done once at the factory. When the FLASH memory is used subsequently, the FPGA chip 04 only needs to read the data stored in the FLASH for calling.

It should be noted that, in the embodiment of the present invention, the FPGA chip 04 is set to calibrate I, Q amplitude, quadrature and dc offset errors of the IQ modulator itself, so as to prevent the IQ modulator output signal from being distorted to cause signal quality deterioration, effectively compensate the inherent error of the modulator in the prior art, and achieve the purpose of high index. A flash memory 35 is provided to store compensation data so that the compensation data source corrected by the FPGA chip 04 for the PLL-integrated IQ modulator 10 can be fully utilized.

In one possible implementation manner, the variable frequency filtering processing circuit 11 includes a filtering module 12, a first radio frequency switch 13, and a second radio frequency switch 14, which are described in detail below.

As shown in fig. 3, the filtering module 12 includes N sets of filtering branches 15, configured to filter the modulation signals in each set of signal frequency ranges, where the signal frequency ranges corresponding to the N sets of filtering branches 15 are different, and the signal frequencies processed by the N sets of filtering branches 15 are all greater than or equal to 100MHZ, where N is a positive integer greater than or equal to 2. The first rf switch 13 is connected between the filtering module 12 and the PLL-integrated IQ modulator 10, and is configured to receive the modulation signal, so as to switch according to the signal frequency of the modulation signal, and connect to one end of the corresponding filtering branch 15. The second rf switch 14 is connected to the other end of the filtering branch 15 according to a group of filters connected to the first rf switch 13, and is configured to output the filtered rf signal. Illustratively, the frequency of the output of the PLL-integrated IQ modulator 10 is between 100MHZ and 2200MHZ when N is equal to 7, and the harmonic and spurious components generated by the modulation are filtered out using a radio frequency switch plus filter combination scheme. For frequency signals of 100MHz or above, the filters are divided into 7 groups, and the radio frequency switches are switched according to different signal frequencies, so that the signals of different frequencies are filtered by the filters of different groups, and further, the harmonic waves and the stray waves in the whole frequency range of 100MHz to 2200MHz are effectively filtered.

For signals in the frequency band of 40MHz to 100MHz, the IQ modulator cannot be directly generated, and can be obtained by adopting the frequency mixer 18 to carry out down-conversion. In one possible implementation manner, the filtering module 12 further includes: a low frequency filtering branch 16. The low-frequency filtering branch 16 includes a fixed-frequency phase-locked loop 17, a mixer 18 and a low-pass filter 19, which will be described in detail below.

The fixed frequency pll 17 is used to generate a fixed preset frequency sinusoidal signal. The mixer 18 is connected to one end of the low-frequency filtering branch 16, and configured to output a difference signal between the modulation signal and the fixed preset-frequency sinusoidal signal, where the frequency of the difference signal is within a preset frequency range, and the preset frequency range is 40MHz to 100 MHz. And the low-pass filter 19 is connected to the other end of the low-frequency filtering branch 16 and is used for filtering signals outside the preset frequency range. Illustratively, when it is required to output a signal below 100MHz, the first rf switch 13 and the second rf switch 14 are simultaneously switched to the low-frequency filtering branch 16, the low-frequency filtering branch 16 includes a mixer 18, a fixed-frequency phase-locked loop 17(PLL) module and an LPF (low-pass filter 19), first, the fixed-frequency phase-locked loop 17PLL generates a 315MHz fixed sinusoidal signal, wherein the fixed-frequency PLL is generated by using a PLL ic chip, and only outputs a fixed frequency point, for example, 315MHz, and controls the IQ modulator to generate a frequency signal in the range of 355MHz to 415MHz, the mixer 18 generates an output signal of the difference between the two, that is, an output signal in the range of 40MHz to 100MHz, and the low-pass filter 19 is used to filter the unwanted signal generated by the mixer 18 outside the range of 40MHz to 100 MHz.

In one possible implementation manner, the variable frequency filter processing circuit 11 further includes: the first digital step attenuator 20, the first power amplifier 21, the amplitude equalizer 22, the second power amplifier 23, and the second digital step attenuator 24 are described in detail below.

The first digital step attenuator 20 is configured to attenuate the filtered radio frequency signal and output a first attenuated signal. The first power amplifier 21 is configured to amplify the first attenuated signal and output a first amplified signal. The amplitude equalizer 22 is used for compensating the first amplified signal and outputting a compensated signal. The second power amplifier 23 is configured to amplify the compensation signal and output a second amplified signal. The second digital step attenuator 24 is used for attenuating the second amplified signal and outputting a second attenuated signal. By cascading two DSAs (digital step attenuators) and two PAs (power amplifiers) and one amplitude equalizer 22 circuit after the output of the filtering module 12. The DSA (digital step attenuator) is matched with the PA (power amplifier) to adjust the output power range, the amplitude equalizer 22 is mainly used for preliminarily compensating the characteristics of high insertion loss and low frequency unevenness of the PA (power amplifier) and the line, the difference of high and low frequency output power is reduced under the condition that the attenuator is not set, and the attenuation dynamic range of the DSA (digital step attenuator) can be utilized to the maximum extent.

In one possible implementation manner, the variable frequency filter processing circuit 11 further includes: n sets of fading range switching modules 25, where N is a positive integer greater than or equal to 1, and any set of fading range switching modules 25 includes: attenuation module 26, first pass-through branch 27, third rf switch 28 and fourth rf switch 29. This will be explained in detail below.

The attenuation module 26 is configured to perform non-zero preset decibel attenuation on the second attenuation signal. The first straight-through branch 27 is used for zero-point-decibel attenuation of the second attenuation signal. A third rf switch 28 and a fourth rf switch 29 for gating the attenuation module 26 or the first pass-through branch 27 by cooperation between the third rf switch 28 and the fourth rf switch 29. Illustratively, when N is equal to 3, the three-group attenuation range switching module 25 is further arranged after the second digital step attenuator 24 in order to further improve the dynamic range of the output power of the whole machine, and the three-group attenuation range switching module is composed of the third and fourth radio frequency switches 29 and 3 fixed attenuators of 30 dB. The circuit output power can be reduced by 30dB, 60dB and 90dB as a whole by switching the cooperative switching of the third and fourth rf switches 29.

In one possible implementation manner, the variable-frequency filtering processing circuit 11 further includes a third digital step attenuator 30, a third power amplifier 31, a second pass branch 32, a fifth radio frequency switch 33, and a sixth radio frequency switch 34, which are described in detail below.

The third digital step attenuator 30 is used to compensate the different frequency powers of the output signal of the attenuation range switching module 25, so as to keep the different frequency output powers flat, and output a third compensation signal. The third power amplifier 31 is configured to amplify the third compensation signal and output a corresponding radio frequency signal. The second straight-through branch 32 is configured to perform zero-point-decibel attenuation on the signal output by the attenuation range switching module 25, and output a corresponding radio frequency signal. A fifth rf switch 33 and a sixth rf switch 34, configured to switch on the third power amplifier 31 or the second through branch 32 through cooperation between the fifth rf switch 33 and the sixth rf switch 34. A DSA is cascaded at the rear stage of the circuit of the attenuation range switching module 25 and used for performing power compensation on output power with different frequencies, and the output power with different frequencies is kept flat. The final stage of the USB digital television signal source is provided with a PA (power amplifier) and a 0dB attenuation switching circuit, and when the circuit needs to output high power, the PA branch circuit is switched; when the circuit needs to output low power, the circuit is switched to a 0dB attenuation branch circuit, and meanwhile, the output of large and small signals is considered.

the embodiment of the utility model provides a USB digital television signal source, including USB3.0 interface 01, first USB controller 02, second USB controller 03, FPGA chip 04 and radio frequency module 05. The utility model discloses in, by USB3.0 interface 01 is as the data communication media to convenience of customers carries out the information interaction of USB data with USB digital television signal source and outside host computer, conveniently carries, can realize converting outside USB data into the parallel data that FPGA can discern through first USB controller 02, can realize encapsulating the parallel data that FPGA can discern into USB data through second USB controller 03, thereby can transmit for outside host computer; internal parameter rewriting can be carried out according to parameter configuration data in USB data transmitted by an external upper computer through the FPGA so as to realize standard transformation of different systems, data processing can be further carried out according to software radio technologies such as coding, interweaving, mapping and modulation defined by standards of different systems, and then output of standard signals of different systems is realized through the radio frequency module 05; the utility model discloses when the television signal of multiple standard can be exported, multiple test demand is satisfied in can also portablely shifting.

The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations are also considered as the protection scope of the present invention.

Claims

1. The utility model provides a USB digital television signal source which characterized in that, includes USB3.0 interface, first USB controller, second USB controller, FPGA chip and radio frequency module, wherein:

2. The USB digital television signal source of claim 1, wherein the rf module comprises: two DAC chips, baseband filter, integrated PLL's IQ modulator and frequency conversion filtering processing circuit, wherein:

3. The USB digital television signal source of claim 2, further comprising:

4. The USB digital television signal source of claim 3, wherein the frequency conversion filter processing circuit comprises: the filtering module comprises N groups of filtering branches and is used for filtering modulation signals in each group of signal frequency ranges, wherein the signal frequency ranges corresponding to the N groups of filtering branches are different, the signal frequencies processed by the N groups of filtering branches are all larger than or equal to 100MHZ, and N is a positive integer larger than or equal to 2;

5. The USB digital television signal source of claim 4, wherein the filtering module further comprises:

6. The USB DTV signal source of any one of claims 4 or 5, wherein the frequency conversion filter processing circuit further comprises: the device comprises a first digital step attenuator, a first power amplifier, an amplitude equalizer, a second power amplifier and a second digital step attenuator; wherein:

7. The USB digital television signal source of claim 6, wherein the frequency conversion filter processing circuit further comprises:

8. The USB digital television signal source of claim 7, wherein the frequency conversion filter processing circuit further comprises:

9. The USB digital television signal source of claim 8,

the FPGA chip is respectively connected with an IQ modulator, a first radio frequency switch, a second radio frequency switch, a third radio frequency switch, a fourth radio frequency switch, a fifth radio frequency switch, a sixth radio frequency switch, a first digital step attenuator, a second digital step attenuator and a third digital step attenuator which are integrated with a PLL.

10. The USB digital television signal source of claim 1, further comprising an ASI line equalizer and an ASI line driver, wherein,