CN210093112U - High efficiency BUCK synchronous rectification control circuit - Google Patents
High efficiency BUCK synchronous rectification control circuit Download PDFInfo
- Publication number
- CN210093112U CN210093112U CN201920889487.1U CN201920889487U CN210093112U CN 210093112 U CN210093112 U CN 210093112U CN 201920889487 U CN201920889487 U CN 201920889487U CN 210093112 U CN210093112 U CN 210093112U
- Authority
- CN
- China
- Prior art keywords
- circuit module
- low
- level switch
- buck
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Dc-Dc Converters (AREA)
Abstract
The utility model relates to a synchronous rectification control circuit of high efficiency BUCK, including the state that utilizes the detection SW potentiometre come the open closure state of perception high level switch to and utilize the gate pole potentiometre that detects the low level switch to come the open closure state of perception low level switch. The problem of delay and interference of signal transmission between different power domains is avoided, real-time detection and reaction of Buck synchronous rectification are achieved, the dead time of closing a high-level switch and a low-level switch simultaneously is reduced to the theoretical minimum value on the premise of ensuring system safety, and a Buck synchronous rectification circuit which is stable, reliable and efficient is achieved.
Description
Technical Field
The utility model relates to a step-down DC-DC circuit field, concretely relates to synchronous rectification control circuit of high efficiency BUCK.
Background
The BUCK is one of basic topologies of DC-DC, mainly realizes the step-down conversion from direct current to direct current, generally needs a PWM logic circuit to control alternate conduction of two MOS tubes to realize voltage conversion, the duty ratio of the PWM logic circuit regulates direct current output electricity, a functional block diagram is shown in figure 1, when a high-level switch on the PWM logic circuit is conducted, an input end power supply charges and stores energy to a load and an inductor L through the high-level switch and the inductor L, the inductor L is equivalent to a constant current source and plays a role in transferring energy, and a capacitor is equivalent to a constant voltage source and plays a role in smoothing and filtering in the circuit; when the upper high-level switch is turned off and the lower low-level switch is turned on, the inductor L forms a current loop through the load and the low-level switch to release energy and continuously supply power to the load.
When the circuit normally works, the PWM signal is continuously output at a higher frequency, the frequency range is usually 30KHZ to 4MHz, the voltage at the output end of the PWM signal consists of a tiny ripple wave and a larger direct-current component, and the output voltage is constant in macroscopic view. The duty cycle (denoted by D, meaning the ratio of the upper switch on time to the period), the input Voltage (VIN), and the output Voltage (VOUT) of the PWM during steady state of the circuit are related as follows: VOUT ═ VIN × D; in an actual circuit, the judging and detecting methods from the turning-on of a high-order switch, the turning-off of a low-order switch to the turning-off of the high-order switch and the turning-on of the low-order switch are different, and the switching intermediate states, namely dead time, are different.
The first traditional mode is as follows: PWM works with fixed switching frequency, the low-level switch is turned on after the high-level switch is turned off and the fixed delay time T1 is added, the high-level switch is turned on after the low-level switch is turned off and the fixed delay time T2 is added, so that the possibility that upper and lower MOS tubes are simultaneously conducted is avoided, however, in the structure, the delay time must be provided with a certain margin, the margin needs to consider production process fluctuation, junction capacitance distribution of the MOS tubes, driving current fluctuation and other factors, and all the delay time is set to be relatively long. Before the high-order switch is turned off, the low-order switch is not turned on, the low-order switch is turned off, and before the high-order switch is not turned on, the loop current flows through the parasitic diode of the low-order switch to form a current loop, the peak current of the inductor is the largest at the moment, the forward voltage drop generated on the parasitic diode of the low-order switch is also the largest, the typical value is between 0.6V and 1V, the loss generated by the system is very large, and the integral conversion efficiency is reduced. Because the PWM switching signal works all the time, the switching loss is more than 10mA when the PWM switching signal outputs no load, the requirement of a new generation of green energy is not met, and the driving waveforms of the high-order switch and the low-order switch are shown in figure 2.
The traditional mode two: the method is characterized in that optimization is improved on the basis of the traditional mode I, gate signals of a high-position switch are detected, when the gate signals of the high-position switch are detected to be changed from on to off, the signals of the high-position switch for turning off are informed to a synchronous rectification logic control circuit, then the on signals of a low-position switch are generated, similarly, when the gate signals of the low-position switch are detected to be changed from on to off, the signals of the low-position switch for turning off are informed to a synchronous rectification logic circuit module, and then the on signals of the high-position switch are generated. Compared with the traditional mode, the control of the pair of dead time is more accurate, but certain defects still exist, for a high-voltage Buck line, the driving of a high-level switch and a gate pole detection line are in independent power domains, so that after the high-level switch is detected to be turned off, a signal that the high-level switch is turned off needs to be informed to a synchronous rectification control logic through a level-shift line, and the synchronous rectification control logic generates a signal that a low-level switch is turned on. Therefore, although the dead time control of the high-low level switch is improved to a certain extent, the dead time control is not preferable for the high-voltage Buck, on one hand, the dead time is increased due to level-shift transmission, and on the other hand, once a signal transmission error occurs in the level-shift, the high-low level switch may be directly turned on at the same time, so that the system is burnt, and the implementation schematic diagram of the method is shown in fig. 3.
SUMMERY OF THE UTILITY MODEL
To the shortcoming of above-mentioned prior art, the utility model provides a synchronous rectification control circuit of high efficiency BUCK can effectively promote system conversion efficiency, can effectively detect the turn-off signal of high level switch and low level switch, and the at utmost reduces the blind spot time delay, avoids the risk that high level switch and low level switch switched on simultaneously again.
The purpose of the utility model and the technical problem thereof can be realized by adopting the following technical scheme.
According to the utility model provides a high efficiency BUCK synchronous rectification control circuit, including rectifier inductance, high level switch, low level switch, Buck rectification logic circuit module, high level switch drive circuit module, low level switch drive circuit module, SW electric potential detection circuit module, low tube Gate electric potential detection circuit module, BUCK loop control circuit module, first divider resistance, second divider resistance and output capacitance; the lower output end of the high-level switch, the upper output end of the low-level switch, the input end of the SW potential detection circuit module and the rectification inductor are connected at one point, the input end of the high-level switch is connected with the output end of the high-level switch driving circuit module, the input end of the low-level switch is connected with the output end of the low-level switch driving circuit module, the low-level switch driving circuit module and the high-level switch driving circuit module are respectively connected with two output ends of the Buck rectification logic circuit module, the output end of the SW potential detection circuit module and the output end of the lower tube Gate potential detection circuit module are respectively connected with two input ends of the Buck rectification logic circuit module, two output ends of the BUCK loop control circuit module are respectively connected with the other two input ends of the Buck rectification logic circuit module, the input end of the rectifier inductor is respectively connected with the lower output end of the high-order switch and the upper output end of the low-order switch, and the output end of the rectifier inductor is connected with the output anode; the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series and connected between the output positive electrode and the output negative electrode, a connection point of the first voltage-dividing resistor and the second voltage-dividing resistor is a voltage feedback signal, the voltage feedback signal is connected to an input end of the BUCK loop control circuit module, and the output capacitor is connected between the output positive electrode and the output negative electrode.
The SW electric potential detection circuit module detects SW electric potential, the SW electric potential is the electric potential of the connection point between the high-order switch, the low-order switch and the rectifier inductor, and when the SW electric potential is lower than a first preset threshold value, the SW electric potential detection circuit module gives a SW low electric potential indication signal.
The BUCK loop control circuit module dynamically adjusts the on-off time of the high-order switch and the low-order switch according to the monitored voltage feedback signal, and respectively provides a high-order switch on/off indication signal and a low-order switch on/off indication signal.
The Buck rectification logic circuit module receives the low-level switch starting indication signal sent by the Buck loop control circuit module, receives the SW low-level indication signal sent by the SW potential detection circuit module, and outputs a control signal to the low-level switch driving circuit module to control the low-level switch to be started.
The low-level switch is connected with the low-level switch driving circuit module, the low-level switch driving circuit module is connected with the low-level switch, the low-level switch driving circuit module.
The Buck rectification logic circuit module receives the high-level switch starting indication signal sent by the BUCK loop control circuit module, receives the lower tube Gate low-pulling indication signal sent by the lower tube Gate potential detection circuit module, and outputs an indication signal to the high-level switch driving circuit module to control the high-level switch to be started.
The utility model relates to a synchronous rectification control circuit of high efficiency BUCK circuit utilizes the SW low voltage pilot signal of SW electric potential detection circuit module output as the foundation that the high level switch of judgement closed, directly inputs Buck rectification logic circuit module, need not monitor the close signal of high level switch drive circuit module, also avoids signal transmission delay to cause the increase of dead time simultaneously, and signal processing is simple, and the signal is also reliable and stable. The dead time can be optimized to the theoretical limit position with the SW low voltage indication signal.
Drawings
FIG. 1 is a schematic diagram of an exemplary synchronous rectification control circuit of a BUCK circuit.
FIG. 2 is a timing diagram of driving waveforms of MOS transistors in an exemplary synchronous rectification control circuit of the BUCK circuit.
FIG. 3 is a block diagram of an exemplary synchronous rectification control circuit of a BUCK circuit.
Fig. 4 is the utility model provides a high efficiency BUCK synchronous rectification control circuit's schematic structure.
Fig. 5 is a timing diagram of the high-level switch and the low-level switch of the high-efficiency BUCK synchronous rectification control circuit provided by the present invention.
Detailed Description
In order to further illustrate the technical means and effects thereof adopted by the high efficiency BUCK synchronous rectification control circuit for achieving the objectives of the present invention, a detailed description is made below with reference to the accompanying drawings and preferred embodiments of the present invention on the specific implementation, structure, features and effects thereof according to the high efficiency BUCK synchronous rectification control circuit.
Fig. 1 to fig. 3 are schematic diagrams of exemplary high-efficiency BUCK synchronous rectification control circuits and timing diagrams of driving waveforms of MOS transistors.
In fig. 1, when the upper MOS transistor M1 is turned on, the input power supply charges and stores energy to the load and the inductor L through the MOS transistor M1 and the inductor L, the inductor L is equivalent to a constant current source and plays a role in transferring energy, and the capacitor is equivalent to a constant voltage source and plays a role in smoothing filtering in the circuit; when the upper MOS transistor M1 is turned off and the lower MOS transistor M2 is turned on, the inductor L forms a current loop through the load and the MOS transistor M2 to release energy and continue to supply power to the load. When the circuit normally works, the PWM signal is continuously output at a higher frequency, the frequency range is usually 30KHZ to 2.5MHz, the voltage of the output end of the PWM signal consists of a tiny ripple wave and a larger direct-current component, and the output voltage is constant in macroscopic view. The relationship between the duty cycle (denoted by D, meaning the ratio of the conduction time of the upper MOS transistor M1 to the period), the input Voltage (VIN), and the output Voltage (VOUT) of the PWM at steady state of the circuit is: VOUT ═ VIN × D; in the actual circuit, the judgment and detection methods from the turning-on of the MOS transistor M1, the turning-off of the MOS transistor M2 to the turning-off of the MOS transistor M1 and the turning-on of the MOS transistor M2 are different, and the intermediate states of the switching, namely dead time, are different.
In fig. 2, the PWM operates at a fixed switching frequency, after the MOS transistor M1 is turned off, a fixed delay time T1 turns on the MOS transistor M2, and after the MOS transistor M2 is turned off, a fixed delay time T2 turns on the MOS transistor M1, so as to ensure that the possibility that the upper and lower MOS transistors are turned on at the same time does not occur. Before the MOS transistor M1 is turned off and the MOS transistor M2 is not turned on, the loop current passes through the parasitic diode of the MOS transistor M2 to form a current loop, at this time, the peak current of the inductor is the largest, the forward voltage drop generated on the parasitic diode of the MOS transistor M2 is also the largest, and is typically 0.6V to 1V, and the loss generated by the system is large, which results in the reduction of the overall conversion efficiency. Because the PWM switching signal is always operated, the switching loss is more than 10mA when the PWM switching signal is output under no load, which is not in accordance with the requirement of the new generation of green energy, and the driving waveforms of the MOS transistor M1 and the MOS transistor M2 are shown in fig. 2.
In fig. 3, the circuit structure of fig. 3 is a further improvement on the circuit structure of fig. 1, by detecting the gate signal of the high-side switch, when the gate signal of the high-side switch is detected to be changed from on to off, the off signal of the high-side switch is notified to the synchronous rectification logic control circuit, and then the on signal of the low-side switch is generated. Compared with the traditional mode, the control of the pair of dead time is more accurate, but certain defects still exist, for a high-voltage Buck line, the driving of a high-level switch and a gate pole detection line are in independent power domains, so that after the high-level switch is detected to be turned off, a signal that the high-level switch is turned off needs to be informed to a synchronous rectification control logic through a level-shift line, and the synchronous rectification control logic generates a signal that a low-level switch is turned on. Therefore, although the dead time control of the high-low level switch is improved to a certain extent, the dead time control is not preferred for the high-voltage Buck, on one hand, the dead time is increased due to level-shift transmission, and on the other hand, once signal transmission errors occur in the level-shift, the high-low level switch can be directly started at the same time, and further, the system is burnt.
In fig. 4, fig. 4 is a schematic structural diagram of a high efficiency BUCK synchronous rectification control circuit according to the present invention.
In fig. 4, the high efficiency BUCK synchronous rectification control circuit of the present invention includes a rectification inductor, a high-level switch, a low-level switch, a BUCK rectification logic circuit module, a high-level switch driving circuit module, a low-level switch driving circuit module, a SW potential detection circuit module, a low-pipe Gate potential detection circuit module, a BUCK loop control circuit module, a first divider resistor, a second divider resistor, and an output capacitor; the lower output end of the high-level switch, the upper output end of the low-level switch, the input end of the SW potential detection circuit module and the rectification inductor are connected at one point, the input end of the high-level switch is connected with the output end of the high-level switch driving circuit module, the input end of the low-level switch is connected with the output end of the low-level switch driving circuit module, the low-level switch driving circuit module and the high-level switch driving circuit module are respectively connected with two output ends of the Buck rectification logic circuit module, the output end of the SW potential detection circuit module and the output end of the lower tube Gate potential detection circuit module are respectively connected with two input ends of the Buck rectification logic circuit module, two output ends of the Buck loop control circuit module are respectively connected with the other two input ends of the Buck rectification logic circuit module, the input end of the rectifier inductor is respectively connected with the lower output end of the high-order switch and the upper output end of the low-order switch, and the output end of the rectifier inductor is connected with the output anode; the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series and connected between the output positive electrode and the output negative electrode, a connection point of the first voltage-dividing resistor and the second voltage-dividing resistor is a voltage feedback signal, the voltage feedback signal is connected to an input end of the Buck loop control circuit module, and the output capacitor is connected between the output positive electrode and the output negative electrode. In addition, the upper tube in fig. 4 refers to a high-level switch, and the lower tube refers to a low-level switch.
The SW electric potential detection circuit module detects SW electric potential, the SW electric potential is the electric potential of the connection point between the high-order switch, the low-order switch and the rectifier inductor, and when the SW electric potential is lower than a first preset threshold value, the SW electric potential detection circuit module gives a SW low electric potential indication signal.
The Buck loop control circuit module dynamically adjusts the on-off time of the high-order switch and the low-order switch according to the monitored voltage feedback signal, and respectively provides an on-off indication signal of the high-order switch and an on-off indication signal of the low-order switch.
The Buck rectification logic circuit module receives the low-level switch starting indication signal sent by the Buck loop control circuit module, receives the SW low-level indication signal sent by the SW potential detection circuit module, and outputs a control signal to the low-level switch driving circuit module to control the low-level switch to be started.
The low-level switch is connected with the low-level switch driving circuit module, the low-level switch driving circuit module is connected with the low-level switch, the low-level switch driving circuit module.
The Buck rectification logic circuit module receives the high-level switch starting indication signal sent by the Buck loop control circuit module, receives the lower tube Gate low-pulling indication signal sent by the lower tube Gate potential detection circuit module, and outputs an indication signal to the high-level switch driving circuit module to control the high-level switch to be started.
When the high-order switch is conducted, the potential of the SW end of the connection point between the rectifying inductor and the high-order switch and the low-order switch is equal to the input voltage VIN, and because the input voltage VIN is higher than the output voltage VOUT, the current on the rectifying inductor is increased by the voltage drop of the two ends of the rectifying inductor, wherein the current part which is higher than the requirement of the load is stored in the output capacitor in a charge mode in the period of time. When the PWM turn-off time adjusted in the loop circuit is reached, the high-level switch is turned off, at the moment, because of the reason that the inductive current cannot suddenly change, the rectifying inductor draws current from the SW end, so that the potential of the SW end is rapidly reduced, when the SW potential is reduced to a preset potential detection threshold value, the high-level switch can be judged to be completely turned off, and at the moment, the preset potential detection threshold value is far lower than the voltage difference between the output positive electrode and the output negative electrode, for example, the voltage difference is reduced to be below 100mV, so that the judgment error is avoided when no current exists in the rectifying inductor. And the continuous current from the SW end to the VOUT end is also arranged on the rectifying inductor, thereby being used as the condition for the conduction of the low-level switch. The judgment mode is not influenced by the drive delay of the high-Level switch, the moment of completely turning off the high-Level switch is ensured, meanwhile, the detection judgment line is in a low-Level power supply domain, signal transmission is not needed through a Level-shift line, the Level-shift transmission delay is avoided, the judgment signal is transmitted to a management logic line of the low-Level switch in the fastest mode, the mode has the advantages of reliability and timeliness, and dead time between the turning-off of the high-Level switch and the turning-on of the low-Level switch can be compressed to the theoretical limit on the premise of safety and reliability.
When the low-level switch is conducted, the voltage drop of the rectifier inductor from the SW end to the VOUT end is-VOUT, the inductor current begins to drop, and the part of the rectifier inductor, which is lower than the current required by the load, is complemented by the output capacitor in the process. When the starting time of the next period is reached, the BUCK loop control circuit module controls the low-level switch to be turned off, at the moment, the potential of the gate pole of the low-level switch is detected, when the potential of the gate pole of the low-level switch is reduced to be close to 0 potential, the low-level switch can be judged to be turned off completely, and the starting signal of the clock period is combined to serve as a condition that the high-level switch can be turned on. Because the judgment line is also in a low-Level power supply domain, the Level-shift is not needed, the judgment line also has the advantages of reliability and timeliness, and dead time between the turn-off of the low-Level switch and the turn-on of the high-Level switch can be compressed to be approximately the theoretical limit.
In the dead time, the current on the rectification inductance freewheels through a parasitic diode of the low-order switch, the conduction voltage drop of the freewheeling diode is about 800mV in general, and the channel voltage drop of the low-order switch is only the current I of the rectification inductanceLMultiplied by the internal resistance R of the low-level switchLS，IL×RLSGenerally, the voltage drop of the low-level switch is only 20-150 mV, so that the voltage drop of the low-level switch is increased by 800mV-I in dead timeL×RLS。
As shown in FIG. 5, the start time of each cycle is t0The high-level switch has a turn-on time t1The turn-off time of the high-level switch is t2The low-level switch has a turn-on time t3The turn-off time of the low-level switch is t4The conducting time of the high-level switch in the next period is t5Two sections of dead time occurring in each period are respectively t3-t2And t and5-t4。
compared with the ideal condition that the conduction time of the high-order switch and the low-order switch is completely connected, the energy which is lost more in two dead time sections
Is otherwise provided with
And
therefore, the length of the dead time directly affects the energy loss of the BUCK line in the energy conversion process, and therefore the dead time is compressed as much as possible to improve the conversion efficiency of the BUCK line in the energy conversion process. And the utility model discloses a synchronous rectification circuit can compress the dead time of BUCK circuit to being close to theoretical limit under safe and reliable's prerequisite. Safe, reliable and efficient voltage reduction conversion is realized.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above description, and although the present invention has been disclosed with the preferred embodiment, it is not limited to the present invention, and any skilled person in the art can make some modifications or equivalent variations within the technical scope of the present invention without departing from the technical scope of the present invention.
Claims (6)
1. A high-efficiency BUCK synchronous rectification control circuit is characterized by comprising a rectification inductor, a high-order switch, a low-order switch, a Buck rectification logic circuit module, a high-order switch driving circuit module, a low-order switch driving circuit module, an SW potential detection circuit module, a lower tube Gate potential detection circuit module, a BUCK loop control circuit module, a first voltage-dividing resistor, a second voltage-dividing resistor and an output capacitor; the lower output end of the high-level switch, the upper output end of the low-level switch, the input end of the SW potential detection circuit module and the rectification inductor are connected at one point, the input end of the high-level switch is connected with the output end of the high-level switch driving circuit module, the input end of the low-level switch is connected with the output end of the low-level switch driving circuit module, the low-level switch driving circuit module and the high-level switch driving circuit module are respectively connected with two output ends of the Buck rectification logic circuit module, the output end of the SW potential detection circuit module and the output end of the lower tube Gate potential detection circuit module are respectively connected with two input ends of the Buck rectification logic circuit module, two output ends of the BUCK loop control circuit module are respectively connected with the other two input ends of the Buck rectification logic circuit module, the input end of the rectifier inductor is respectively connected with the lower output end of the high-order switch and the upper output end of the low-order switch, and the output end of the rectifier inductor is connected with the output anode; the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series and connected between the output positive electrode and the output negative electrode, a connection point of the first voltage-dividing resistor and the second voltage-dividing resistor is a voltage feedback signal, the voltage feedback signal is connected to an input end of the BUCK loop control circuit module, and the output capacitor is connected between the output positive electrode and the output negative electrode.
2. The high efficiency BUCK synchronous rectification control circuit as claimed in claim 1, wherein the SW potential detection circuit module detects SW potential, the SW potential is the potential of the connection point between the high level switch, the low level switch and the rectification inductor, and when the SW potential is lower than a first preset threshold value, the SW potential detection circuit module gives a SW low potential indication signal.
3. The high-efficiency BUCK synchronous rectification control circuit as claimed in claim 2, wherein the BUCK loop control circuit module dynamically adjusts the ON/OFF time of the high-level switch and the low-level switch according to the monitored voltage feedback signal to respectively provide an ON/OFF indication signal of the high-level switch and an ON/OFF indication signal of the low-level switch.
4. The high efficiency BUCK synchronous rectification control circuit as claimed in claim 3, wherein the BUCK rectification logic circuit module receives the low level switch turn-on indication signal from the BUCK loop control circuit module, receives the SW low level indication signal from the SW potential detection circuit module, and outputs a control signal to the low level switch driving circuit module to control the low level switch to turn on.
5. The high efficiency BUCK synchronous rectification control circuit according to claim 3, wherein the lower Gate level detection circuit module detects a Gate level of the lower switch, the Gate level of the lower switch is a level of a connection point between the lower switch driving circuit module and the lower switch, and the lower Gate level detection circuit module provides a lower Gate pull-down indication signal when the Gate level of the lower switch is lower than a second predetermined threshold.
6. The high-efficiency BUCK synchronous rectification control circuit according to claim 5, wherein the BUCK rectification logic circuit module receives the high-side switch turn-on indication signal sent by the BUCK loop control circuit module, receives the lower Gate pull-down indication signal sent by the lower Gate potential detection circuit module, and outputs an indication signal to the high-side switch driving circuit module to control the high-side switch to be turned on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920889487.1U CN210093112U (en) | 2019-06-13 | 2019-06-13 | High efficiency BUCK synchronous rectification control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920889487.1U CN210093112U (en) | 2019-06-13 | 2019-06-13 | High efficiency BUCK synchronous rectification control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210093112U true CN210093112U (en) | 2020-02-18 |
Family
ID=69482763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920889487.1U Active CN210093112U (en) | 2019-06-13 | 2019-06-13 | High efficiency BUCK synchronous rectification control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210093112U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110336461A (en) * | 2019-06-13 | 2019-10-15 | 无锡猎金半导体有限公司 | A kind of high efficiency BUCK synchronous commutating control circuit |
-
2019
- 2019-06-13 CN CN201920889487.1U patent/CN210093112U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110336461A (en) * | 2019-06-13 | 2019-10-15 | 无锡猎金半导体有限公司 | A kind of high efficiency BUCK synchronous commutating control circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10498225B2 (en) | Dual-rectification full bridge interleaved single stage PFC converter circuit and control methods thereof | |
| US7023186B2 (en) | Two stage boost converter topology | |
| EP3058648B1 (en) | Gate drive apparatus for resonant converters | |
| US7518895B2 (en) | High-efficiency power converter system | |
| US9906147B2 (en) | Adaptive dead time control apparatus and method for switching power converters | |
| CN105846682B (en) | Novel hybrid control mode of forward and reverse converter | |
| CN103227568B (en) | Flyback converter and the method for operating described flyback converter | |
| CN102364859B (en) | Switching power supply control device and flyback switching power supply with same | |
| US7224149B2 (en) | Current resonance type DC/DC converter capable of decreasing losses on no-load and a light load | |
| US9136768B2 (en) | Switching power supply device | |
| US8582326B2 (en) | Switching power supply apparatus | |
| US8488346B2 (en) | Power conversion apparatus and method | |
| CN103199709A (en) | Double-switch flyback type power converter | |
| CN104300795A (en) | Flyback converter and control method of flyback converter | |
| US20170302176A1 (en) | System and Method for a Switched-Mode Power Supply | |
| CN103441680A (en) | Soft-switching full-bridge direct-current converter capable of reducing current-circulation loss | |
| CN113938020A (en) | Half-bridge LLC resonant converter | |
| JP2013090432A (en) | Forward type dc-dc conversion device | |
| CN210093112U (en) | High efficiency BUCK synchronous rectification control circuit | |
| CN110831284B (en) | LED driving power supply and controller thereof | |
| US10256717B2 (en) | Zero current detection circuit for converter soft switching control | |
| JP4172569B2 (en) | Switching power supply | |
| CN110943616B (en) | Buck/Boost circuit soft switch PWM-PFM control system and control method | |
| CN117578894A (en) | System and method for automatically determining switch states in a power converter | |
| Khyalap et al. | Soft switching control of synchronous buck converter with ZCD circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 214115 c1-6f, China Sensor Network International Innovation Park, 200 Linghu Avenue, Wuxi City, Jiangsu Province Patentee after: Jiangsu Xintan Microelectronics Co.,Ltd. Address before: 214135 b340, China Sensor Network International Innovation Park, 200 Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province Patentee before: WUXI LIEJIN SEMICONDUCTOR CO.,LTD. |