CN210090563U - Circuit unit for testing grid dynamic capacitance of inverter and test circuit - Google Patents
Circuit unit for testing grid dynamic capacitance of inverter and test circuit Download PDFInfo
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- CN210090563U CN210090563U CN201822268624.8U CN201822268624U CN210090563U CN 210090563 U CN210090563 U CN 210090563U CN 201822268624 U CN201822268624 U CN 201822268624U CN 210090563 U CN210090563 U CN 210090563U
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Abstract
The utility model relates to a circuit unit and test circuit for test of phase inverter grid developments electric capacity, circuit unit includes a CMOS phase inverter structure and two transmission gate A structures that the structure is the same: the first ports of the two transmission gates A are connected, the second port is a clock signal input end, and the third port is a signal output end and a voltage input end; the inverter comprises three ports which are respectively: the gate voltage input end, the PMOS source end and the NMOS source end, wherein one end of the PMOS source end and the NMOS source end is connected to the first ports of the two transmission gates A, and the other end of the PMOS source end and the NMOS source end is a bias voltage input end. A test circuit uses circuit unit as described above, the utility model discloses can realize the accurate measurement to phase inverter grid dynamic capacitance.
Description
Technical Field
The utility model relates to a circuit element tests the field, especially relates to a circuit unit and test circuit for test of phase inverter grid developments electric capacity.
Background
The inverter is the most basic and most common logic circuit in a standard cell library, is the most basic component unit of an integrated circuit, and is particularly widely applied to the integrated circuit. As shown in fig. 1, the CMOS inverter is composed of a P-type and an N-type MOS transistor, the gates of the two transistors are connected together and used as the input terminal of the inverter, the drains of the two transistors are also connected together and used as the output terminal of the inverter, the source and the substrate of the N-type MOS transistor are both grounded, and the source and the substrate of the P-type MOS transistor are connected to the power supply terminal (VDD).
The electrical characteristics of inverters are directly related to the performance of digital circuits. In the working state of the inverter, due to the voltage difference between the grid electrode and the power supply end (VDD/GND), the capacitance between the grid electrode and the power supply end (VDD/GND) is charged and discharged, so that the output of the inverter lags behind the input, wherein the capacitance between the grid electrode and the power supply end (VDD/GND) is regarded as the grid input capacitance of the inverter. The capacitance between the grid and the power supply end (VDD/GND) is regarded as the grid input capacitance of the inverter, and the grid capacitance of the inverter is changed continuously in the process of turning from low to high, namely the grid dynamic capacitance of the inverter. In a digital circuit, the gate dynamic capacitance of an inverter is used as the output load of a previous stage circuit, and is very important for the frequency characteristic of the digital circuit, but the accurate measurement of the gate dynamic capacitance of the inverter is one of the difficulties in the industry.
SUMMERY OF THE UTILITY MODEL
For solving the problem of the normal during operation accurate measurement phase inverter grid dynamic capacitance of phase inverter, the utility model provides a reasonable in design's phase inverter grid dynamic capacitance test circuit unit.
A circuit unit for testing dynamic capacitance of a gate electrode of an inverter, wherein the circuit unit comprises a CMOS inverter structure and two transmission gate A structures with the same structure:
the first ports of the two transmission gates A are connected, the second port is a clock signal input end, and the third port is a signal output end and a voltage input end; the inverter comprises three ports which are respectively: the gate voltage input end, the PMOS source end and the NMOS source end, wherein one end of the PMOS source end and the NMOS source end is connected to the first ports of the two transmission gates A, and the other end of the PMOS source end and the NMOS source end is a bias voltage input end.
A test circuit applies a circuit unit for testing the dynamic capacitance of a grid electrode of an inverter, wherein the PMOS source end of the inverter is respectively connected to the first ports and the bias voltage input ends of two transmission gates A through a first switch circuit; the NMOS source end of the phase inverter is respectively connected to the first ports of the two transmission gates A and the bias voltage input end through a second switch circuit; the two switch circuits respectively control the PMOS source ends to be connected with the first ports or the bias voltage input ends of the two transmission gates A, and the NMOS source ends to be connected with the bias voltage input ends or the first ports of the two transmission gates A.
In a preferred embodiment, the first switch circuit and the second switch circuit have the same configuration.
Each switch circuit is composed of two identical transmission gates B, first ports of the first transmission gate B and the second transmission gate B are connected to a PMOS source end of the phase inverter, a second port of the first transmission gate and a fourth port of the second transmission gate are connected to a signal line end, a third port of the first transmission gate is connected with first ports of the two transmission gates A, a third port of the second transmission gate is a bias voltage input end, and a fourth port of the first transmission gate is connected with a second port of the second transmission gate.
As a preferred embodiment, the transmission gate a and the transmission gate B have the same structure, and both the source and the drain of one PMOS and one NMOS are connected, and a not gate or an inverter is connected between the gates of the two MOS transistors.
As a preferred embodiment, when the third ports of the two transmission gates a are high-voltage input, the switching circuit controls the PMOS source terminal to be connected to the first ports of the two transmission gates a, the NMOS source terminal to be connected to the bias voltage input terminal, and obtains charge-discharge current at the third port; when the third ports of the two transmission gates are low-voltage input, the switch circuit controls the PMOS source end to be connected with the bias voltage input end and the NMOS source end to be connected with the first ports of the two transmission gates A, and charge-discharge current is obtained at the third ports; and calculating to obtain the grid capacitance of the inverter through the two groups of charging and discharging currents.
As a preferred embodiment, the clock input signals of the second ports of the two transmission gates a are opposite.
A test circuit comprising two circuit elements as above for inverter gate dynamic capacitance test: the first circuit unit is provided with a PMOS source end of an inverter which is connected to the first ports of the two transmission gates A; in the second circuit unit, the NMOS source end of the inverter is connected to the first ports of the two transmission gates A; and third ports of two transmission gates A in the two circuit units are connected with a current detection device.
In the first circuit unit, the voltage input of the third port of the two transmission gates A is high voltage; in the second circuit unit, the voltage input of the third port of the two transmission gates A is low voltage; and respectively obtaining charging and discharging currents from third ports of the two transmission gates A through the first circuit unit and the second circuit unit so as to calculate and obtain the grid capacitance of the inverter.
The circuit unit for testing the gate dynamic capacitance of the two inverters and the test circuit applying the circuit unit can be used for testing and calculating the gate capacitance of the inverter: in the first circuit unit, the voltage input of the third port of the two transmission gates A is high voltage, the input end of the bias voltage is low voltage, and the charge-discharge current is obtained from the output ends of the two transmission gates A; in the second circuit unit, the voltage input of the third port of the two transmission gates A is low voltage, the input end of the bias voltage is high voltage, and the charge-discharge current is obtained from the output ends of the two transmission gates A; and calculating the gate capacitance of the inverter through the charging and discharging currents obtained by the first circuit and the second circuit.
The utility model discloses a reasonable circuit design and improvement and the above-mentioned circuit unit that is used for test of phase inverter grid dynamic capacitance who reveals measure the phase inverter charge-discharge current under operating condition respectively through transmission gate A to calculate according to charge-discharge current and obtain grid dynamic capacitance. On one hand, the circuit avoids the direct measurement of current or capacitance on the grid electrode, but directly measures on the power supply end of the inverter to increase the testability of the current, and effectively eliminates the measurement error caused by square wave signals under the normal working state of the inverter; on the other hand, the grid voltage of the phase inverter fluctuates between a low level and a high level, and the drain current exists between the source electrode of the PMOS and the source electrode of the NMOS because the NMOS or the PMOS is not completely turned off, the circuit of the utility model can eliminate the drain current by utilizing a self-differential mode, thereby realizing the accurate measurement of the dynamic capacitance of the phase inverter; and thirdly, the dynamic capacitance test circuit unit with the switch circuit is provided, so that the capacitance test in the same circuit is realized, and the manufacturing cost and the test period are saved.
Drawings
Fig. 1 is a circuit configuration diagram of a CMOS inverter in the related art.
Fig. 2 is a circuit diagram of a CMOS transmission gate in the prior art.
Fig. 3 is a circuit diagram of a circuit symbol representation of a CMOS transfer gate of the prior art.
Fig. 4 is a structural diagram of one of the circuit units according to embodiment 1 of the present invention.
Fig. 5 is a block diagram of another circuit unit according to embodiment 1 of the present invention.
Fig. 6 is a structural view of embodiment 2 of the present invention.
Detailed Description
The inverter gate dynamic capacitance is usually measured at the gate terminal, which is difficult to measure accurately for two reasons: (1) the gate dynamic capacitance must be measured in the inverter operating state; (2) when the inverter normally works, square waves with certain frequency are conducted to the grid end, the current on the square waves is difficult to accurately measure, and the capacitance measurement is not suitable by directly measuring the current on the grid end. The LCR meter is commonly used to measure the gate capacitance of MOS devices, but since dynamic capacitance can only be measured in an operating state, the LCR meter can only measure the gate capacitance of a single MOS device.
The utility model provides a canThe circuit unit can accurately measure the dynamic capacitance of the grid electrode of the inverter. The circuit unit comprises a CMOS inverter structure and two transmission gate A structures. Transmission gate A plays on-off control's effect, and the on-resistance of transmission gate is less than ordinary switch, and through the size of adjusting the transmission gate, on-resistance can be littleer moreover. The transmission gate A in the application is a COMS transmission gate, and the structure of the transmission gate A comprises a P-type MOS tube and an N-type MOS tube, wherein the source electrodes of the PMOS and the NMOS are connected with each other, the drain electrodes of the PMOS and the NMOS are connected with each other, and a NOT gate or a phase inverter is connected between the grid electrodes of the two MOS tubes to enable two grid signals of the transmission gate to be complementary. FIG. 2 shows a circuit structure of the CMOS transmission gate (inverter NOR gate is omitted and not shown because of complementary signal identification), which includes an N-type MOS transistor T1And a P-type MOS transistor T2，T1And T2Respectively connected as the input and output of a transmission gate, T of the transmission gate1And T2Respectively connected to a set of complementary control signals (C and C'). Fig. 3 is a two circuit symbol representation of the transmission gate of fig. 2. In the transmission gate A, defining the source electrode or the drain electrode connected together in the CMOS transmission gate as a first port; defining the C' signal end as a second port which is a clock signal input end; the drains or sources connected together are defined as the third ports, which are the signal output terminal and the voltage input terminal.
In the circuit unit, first ports of two transmission gates A are connected, a second port is a clock signal input end, and a third port is a signal output end and a voltage input end; the inverter comprises three ports which are respectively: the gate voltage input end, the PMOS source end and the NMOS source end, wherein one end of the PMOS source end and the NMOS source end is connected to the first ports of the two transmission gates A, and the other end of the PMOS source end and the NMOS source end is a bias voltage input end.
Example 1
A circuit cell for inverter gate dynamic capacitance testing, said circuit cell comprising an inverter 1 structure, two transmission gate a2 structures: the first ports 21 of the two transmission gates A2 are connected, the second port 22 is a clock signal input end, and the third port 23 is a signal output end and a voltage input end; the inverter comprises three ports which are respectively: the gate voltage input end, the PMOS source end and the NMOS source end, one of the PMOS source end and the NMOS source end is connected to the first port 21 of the two transmission gates a2, and the other end is a bias voltage input end.
In the circuit unit for testing dynamic capacitance of the gate of the inverter shown in fig. 4, the source of the PMOS transistor of the inverter 1 is connected to the first port 21 of the two transmission gates a, and the source of the NMOS transistor is the bias voltage input terminal; in the circuit unit for testing dynamic capacitance of the gate of the inverter shown in fig. 4, the source of the NMOS transistor of the inverter 1 is connected to the first port 21 of the two transmission gates a, and the source of the PMOS transistor is the bias voltage input terminal.
In this embodiment, the transmission gate a2 structure is formed by connecting the source and the drain of a PMOS and an NMOS, and connecting the drain and the source, and a not gate or an inverter is connected between the gates of the two MOS transistors.
In this embodiment, the clock input signals of the second ports 22 of the two transmission gates a are opposite, and therefore, the two clock input signals may be provided by two clock signals, or may be implemented by inverting one clock signal.
The circuit unit for testing the dynamic capacitance of the gate of the inverter provided by the embodiment can be used for testing and calculating the gate capacitance of the inverter: the third ports of two transmission gates A2 in the circuit units of FIG. 4 and FIG. 5 are both connected with a current detection device; in the circuit unit for testing the gate dynamic capacitance shown in fig. 4, the voltage input at the third port 23 of the two transmission gates a is the high voltage VDD, the bias voltage input end of the inverter 1 is the low voltage GND, and the charge and discharge currents are respectively obtained from the output ends of the two transmission gates a2, that is, the capacitance at the VDD end of the inverter can be calculated; in the circuit unit for testing the gate dynamic capacitance shown in fig. 5, the voltage input to the third ports of the two transmission gates a is the low voltage GND, the bias voltage input end of the inverter is the high voltage VDD, and the charge and discharge currents are obtained from the output ends of the two transmission gates, so that the capacitance of the GND end of the inverter can be calculated; and adding the absolute values of the capacitance obtained by the two measurements to obtain the gate dynamic capacitance of the inverter.
Example 2
The present embodiment provides a test circuit, which applies a circuit unit for testing gate dynamic capacitance of an inverter as disclosed in embodiment 1, and is different from embodiment 1 in that a PMOS source terminal of the inverter 1 is connected to a first port and a bias voltage input terminal of two transmission gates a2 through a first switch circuit 31; the NMOS source of the inverter is connected to the first ports of the two transmission gates a and the bias voltage input end through the second switch circuit 32; the first switch circuit and the second switch circuit respectively control the PMOS source end to be connected with the first ports of the two transmission gates A or the bias voltage input end, and the NMOS source end to be connected with the bias voltage input end or the first ports of the two transmission gates A.
In this embodiment, the clock input signals of the second ports of the two transmission gates a are opposite, and therefore, the two clock input signals may be provided by two clock signals, or may be implemented by inverting one clock signal.
As shown in fig. 6, each of the first switch circuit 31 and the second switch circuit 32 is composed of two identical transmission gates B30, the transmission gate is the transmission gate shown in fig. 2, and the source or the drain of the transmission gate switch connected together is defined as a first port; defining a C signal end as a second port; defining the drain or the source of the transmission gate switch connected together as a third port; the C' signal terminal is defined as the fourth port.
The first switching circuit 31 and the second switching circuit 32 are identical in structure, and each of the switching circuits is composed of two identical transmission gates B30: the first ports of the first transmission gate and the second transmission gate are connected to the PMOS source end of the phase inverter 1, the second port of the first transmission gate and the fourth port of the second transmission gate are connected to the signal line end, the third port of the first transmission gate is connected with the first ports of the two transmission gates A, the third port of the second transmission gate is a bias voltage input end, and the fourth port of the first transmission gate is connected with the second port of the second transmission gate.
The circuit unit for testing the dynamic capacitance of the gate of the inverter provided by the embodiment can be used for testing and calculating the gate capacitance of the inverter: when the third ports of the two transmission gates a are high-voltage VDD inputs, the bias voltage input end is a low-voltage GND, the switch circuit controls the PMOS source end to be connected with the first ports of the two transmission gates a and the NMOS source end to be connected with the bias voltage input end (namely, the signal line end of the first switch circuit is high level and the signal line end of the second switch circuit is low level), and charge-discharge current is obtained at the third port; when the third ports of the two transmission gates are low-voltage GND input, the bias voltage input end is high-voltage VDD, the switch circuit controls the PMOS source end to be connected with the bias voltage input end, and the NMOS source end to be connected with the first ports of the two transmission gates A (namely, the signal line end of the first switch circuit is low level, and the signal line end of the second switch circuit is high level), and charge-discharge current is obtained at the third port; and calculating to obtain the grid capacitance of the inverter through the two groups of charging and discharging currents.
Finally, it should be noted that the above-mentioned list is only a specific embodiment of the present invention. It is obvious that the present invention is not limited to the above embodiments, but many variations are possible. All modifications which can be derived or suggested by a person skilled in the art from the disclosure of the present invention are to be considered within the scope of the invention.
Claims (9)
1. A circuit unit for testing dynamic capacitance of a grid electrode of an inverter is characterized by comprising a CMOS inverter structure and two transmission gate A structures with the same structure:
the first ports of the two transmission gates A are connected, the second port is a clock signal input end, and the third port is a signal output end and a voltage input end; the inverter comprises three ports which are respectively: the gate voltage input end, the PMOS source end and the NMOS source end, wherein one end of the PMOS source end and the NMOS source end is connected to the first ports of the two transmission gates A, and the other end of the PMOS source end and the NMOS source end is a bias voltage input end.
2. The circuit unit for testing the dynamic capacitance of the gate of the inverter according to claim 1, wherein the clock input signals of the second ports of the two transmission gates A are opposite.
3. A test circuit, characterized in that, the circuit unit for testing the dynamic capacitance of the gate of the inverter according to claim 1 is applied, the PMOS source terminal of the inverter is connected to the first port and the bias voltage input terminal of the two transmission gates a through the first switch circuit; the NMOS source end of the phase inverter is respectively connected to the first ports of the two transmission gates A and the bias voltage input end through a second switch circuit; the two switch circuits respectively control the PMOS source ends to be connected with the first ports or the bias voltage input ends of the two transmission gates A, and the NMOS source ends to be connected with the bias voltage input ends or the first ports of the two transmission gates A.
4. A test circuit as claimed in claim 3, wherein the first and second switching circuits are of identical construction.
5. A test circuit according to claim 4, wherein each switch circuit is formed by two identical transmission gates B, the first ports of the first and second transmission gates B are connected to the PMOS source terminal of the inverter, the second port of the first transmission gate and the fourth port of the second transmission gate are connected to the signal line terminal, the third port of the first transmission gate is connected to the first ports of the two transmission gates A, the third port of the second transmission gate is the bias voltage input terminal, and the fourth port of the first transmission gate is connected to the second port of the second transmission gate.
6. The test circuit as claimed in claim 5, wherein the transmission gate A and the transmission gate B have the same structure, and are connected by a source and a drain of a PMOS and an NMOS, and a NOT gate or an inverter is connected between the gates of the two MOS transistors.
7. A test circuit according to claim 3, wherein when the third port of the two transmission gates a is a high voltage input, the charge and discharge current is obtained at the third port; when the third ports of the two transmission gates are low-voltage input, the charge-discharge current is obtained at the third ports; and calculating to obtain the grid capacitance of the inverter through the two groups of charging and discharging currents.
8. A test circuit comprising two circuit elements of claim 1 for inverter gate dynamic capacitance testing: the first circuit unit is provided with a PMOS source end of an inverter which is connected to the first ports of the two transmission gates A; in the second circuit unit, the NMOS source end of the inverter is connected to the first ports of the two transmission gates A; and third ports of two transmission gates A in the two circuit units are connected with a current detection device.
9. The test circuit according to claim 8, wherein in the first circuit unit, the voltage input of the third port of the two transmission gates A is a high voltage; in the second circuit unit, the voltage input of the third port of the two transmission gates A is low voltage; and respectively obtaining charging and discharging currents from third ports of the two transmission gates A through the first circuit unit and the second circuit unit so as to calculate and obtain the grid capacitance of the inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822268624.8U CN210090563U (en) | 2018-12-29 | 2018-12-29 | Circuit unit for testing grid dynamic capacitance of inverter and test circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822268624.8U CN210090563U (en) | 2018-12-29 | 2018-12-29 | Circuit unit for testing grid dynamic capacitance of inverter and test circuit |
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| Publication Number | Publication Date |
|---|---|
| CN210090563U true CN210090563U (en) | 2020-02-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822268624.8U Active CN210090563U (en) | 2018-12-29 | 2018-12-29 | Circuit unit for testing grid dynamic capacitance of inverter and test circuit |
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| CN (1) | CN210090563U (en) |
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Address after: Room A407, Neusoft venture building, 99 Huaxing Road, Xihu District, Hangzhou City, Zhejiang Province, 310012 Patentee after: Hangzhou Guangli Microelectronics Co.,Ltd. Address before: Room A407, Neusoft venture building, 99 Huaxing Road, Xihu District, Hangzhou City, Zhejiang Province, 310012 Patentee before: Semitronix Corp. |