CN210090383U - Dual-channel high-frequency pulse excitation receiving board card based on PXI-to-serial port communication - Google Patents
Dual-channel high-frequency pulse excitation receiving board card based on PXI-to-serial port communication Download PDFInfo
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- CN210090383U CN210090383U CN201920135547.0U CN201920135547U CN210090383U CN 210090383 U CN210090383 U CN 210090383U CN 201920135547 U CN201920135547 U CN 201920135547U CN 210090383 U CN210090383 U CN 210090383U
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Abstract
The utility model discloses a binary channels high frequency pulse encourages and receives integrated circuit board based on PXI changes serial port communication for binary channels supersound water logging C scans detecting system's high frequency pulse encourages and echo receives, belongs to the nondestructive test field. The device comprises a PXI bus-to-serial port communication carrier plate, a bipolar pulse excitation circuit with two channels, an echo signal conditioning circuit of each bipolar pulse excitation circuit, an FPGA core system circuit and a power module. The upper computer transmits parameters of the excitation receiving card to the FPGA through the PXI bus-to-serial port communication carrier plate, controls to generate two-channel high-voltage pulse signals to excite respective water immersion type ultrasonic probe, receives reflected echo signals through the same probe, amplifies and filters the signals through the signal conditioning circuit, and transmits the signals to the dual-channel data acquisition card. The utility model discloses can produce two way excitation parameter adjustable bipolar pulse signal based on monolithic FPGA, can carry out C scanning to two test blocks simultaneously and detect, the integrated level of integrated circuit board is high, can improve detection efficiency.
Description
Technical Field
The high-frequency pulse excitation receiving board card for the double-channel ultrasonic water immersion C scanning detection system is realized, and belongs to the field of nondestructive testing.
Background
Ultrasonic water immersion C scanning detection is a detection method widely used in the field of nondestructive detection, is one of ultrasonic microscopes, and has the advantages of convenience in operation, visual detection result, high detection precision and the like. Two-dimensional acoustic images of the surface and interior of the test piece at different depth levels can be obtained using ultrasonic C-scan techniques. The defect existence on a certain depth level and the shape, the position, the distribution and the trend of the defect can be visually seen from the displayed two-dimensional image.
The ultrasonic tomography method is a detection method developed on the basis of an ultrasonic C scanning technology. Echo signals between the surface echo and the bottom echo are divided by a fixed time window width, so that layered processing in the depth direction of a tested piece can be realized, and further ultrasonic C scanning imaging at different depths can be obtained. The ultrasonic tomography reserves the advantages of high sensitivity, visual detection result and the like of C scanning, can locate the depth range of the defect and obtains wide development trend.
The ultrasonic signal excitation receivers commonly used in the C scanning detection system at present mainly comprise Panametrics 5800/5900 series and JSR DPR300/DPR500 series, and the excitation modes are unipolar negative high-voltage pulses. Although the performance of the commercial equipment is reliable, the commercial equipment has large volume, high cost and single excitation mode, limits the application range of the commercial equipment and is not beneficial to the integrated development of a C scanning detection system
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to the aforesaid not enough, provide a binary channels high frequency impulse excitation based on PXI changes serial port communication and receives the integrated circuit board for binary channels supersound water logging C scans detecting system's high frequency impulse excitation and receives, and this integrated circuit board is inserted in PXIe quick-witted incasement with other function integrated circuit boards equally, occupies a draw-in groove of quick-witted case, greatly improves detecting system's integrated level.
The utility model discloses a technical scheme receive the integrated circuit board for PXI changes serial ports communication based on binary channels high frequency pulse excitation, but excitation frequency, excitation pulse cycle number, excitation mode, repetition frequency, echo gain programme-controlled regulation. The excitation frequency adjusting range is 100kHz-25MHz, a 200Vpp single-period pulse to multi-period pulse sequence can be excited, the excitation mode comprises two types of repeated excitation and external trigger excitation, the excitation repetition frequency adjusting range is 0.1kHz-50kHz, and the echo gain adjusting range is 0-80 dB.
In order to realize the technical problem, the utility model discloses a technical scheme does: a dual-channel high-frequency pulse excitation receiving board card based on PXI to serial port communication is composed of a PXI bus to serial port communication carrier board and a dual-channel pulse excitation receiving board, wherein the PXI bus to serial port communication carrier board and the dual-channel pulse excitation receiving board are connected through pins, and one slot of a PXIe case is occupied.
The PXI bus-to-serial port communication carrier plate is connected with a PXIe-1071 case through a PXI bus socket, communication from a PXI bus to an RS232 serial port of a host is achieved based on a PXI bus interface chip PCI9054, and the transmission baud rate of the serial port is 9600.
The dual-channel pulse excitation receiving plate is composed of a bipolar pulse excitation circuit with two channels, an echo signal conditioning circuit, an FPGA core system circuit and a power module. The hardware design of the bipolar pulse excitation circuit and the echo conditioning circuit of the two channels is the same. The FPGA core system circuit is used as a main controller and is respectively connected with a field effect transistor driver control end in the excitation circuit and a DA chip in the echo signal conditioning circuit; the output of a field effect tube in the excitation circuit is connected with an SMA connector and is connected with the probe through a BNC wire; the SMA joint is simultaneously connected with an isolation amplitude limiting diode in the echo signal conditioning circuit.
The PXI bus serial port communication carrier board can provide 3.3V and 12V voltage for the dual-channel pulse excitation receiving board.
The bipolar pulse excitation circuit is formed by connecting a field effect transistor driver and an N/P channel enhanced field effect transistor, the voltage resistance of the field effect transistor is 200V, the minimum rising edge time and the minimum falling edge time during conduction are both 20ns, and bipolar high-voltage pulses with the maximum central frequency of 25MHz can be generated to excite a corresponding ultrasonic probe.
The echo signal conditioning circuit consists of an isolation amplitude limiting circuit, a voltage follower, a program-controlled gain amplifier and a 7-order low-pass Butterworth filter; the cathode of the isolation amplitude limiting diode is connected with the input end of the voltage follower, the output end of the voltage follower is connected with the input end of the program-controlled gain amplifier, the output of the program-controlled gain amplifier is connected with the 7-order passive low-pass Butterworth filter, the output of the 7-order passive low-pass Butterworth filter is connected with the SMA connector, and the echo signal is connected to the acquisition card through the BNC wire through the SMA connector.
The isolation amplitude limiting circuit is a parallel diode, clamps input voltage within conduction voltage of the diode, and is used for isolating high-voltage pulse generated by the exciting circuit to play a role in protecting a post-stage circuit.
The voltage follower selects AD8021 as a front input buffer of a rear-stage operational amplifier to play a role in impedance matching.
The programmable gain amplifier adopts a two-stage operational amplifier cascade mode, the voltage control end of the programmable gain amplifier is adjusted by controlling the output of the serial digital-to-analog converter through the FPGA, and then the function of gain adjustment is realized, the gain adjustment range is 0-80dB, and the bandwidth is 30 MHz.
The 7-order low-pass Butterworth filter is used for filtering high-frequency noise and improving the signal-to-noise ratio of echo signals, and the bandwidth is 30 MHz.
The power supply required by the FPGA and peripheral chips thereof in the power supply module is obtained by a linear voltage stabilizer, the power supply voltage of the field effect transistor is +/-100V, and the power supply voltage is provided by a DC-DC isolation voltage stabilization double-circuit high-voltage power supply module.
The utility model has the advantages of it is following: (1) the board card is provided with two signal excitation receiving channels, can drive and excite two ultrasonic focusing probes, realizes simultaneous C scanning chromatography detection of two test blocks, and excitation parameters of the channels are independently adjustable, so that the detection efficiency is improved. (2) The two-in-one board card only occupies one slot of the 4-slot case, and has the advantages of compact structure, small volume and high integration level.
Drawings
FIG. 1 is a schematic diagram of a main control unit and peripheral circuits;
FIG. 2 is a schematic diagram of a structure of an input/output interface of a board card;
FIG. 3 is a circuit diagram of one embodiment of a 7 th order low pass passive Butterworth filter;
FIG. 4.a) is a schematic diagram of time-frequency test of an excitation signal (single period 2.5 MHz);
FIG. 4.b) is a schematic diagram of time-frequency test of the excitation signal (three cycles at 5 MHz);
FIG. 5 is a schematic diagram of board echo signal testing;
FIG. 6 is a schematic diagram of a control program;
Detailed Description
The invention will be further described with reference to the accompanying drawings:
fig. 1 is a schematic diagram of a main control unit and peripheral modules of a dual-channel high-frequency pulse excitation receiving board card based on PXI-to-serial communication, and the dual-channel high-frequency pulse excitation receiving board card includes a PXI-bus-to-serial communication carrier board, a two-channel bipolar pulse excitation circuit, echo signal conditioning circuits of the two channels, an FPGA core system circuit, and a power module. The upper computer transmits parameters of the excitation receiving card to the FPGA through the PXI bus-to-serial port communication carrier plate, controls to generate two-channel high-voltage pulse signals to excite respective water immersion type ultrasonic probe, receives reflected echo signals through the same probe, amplifies and filters the signals through the signal conditioning circuit, and transmits the signals to the dual-channel data acquisition card.
In this embodiment, the PXI bus to serial port communication carrier board realizes the communication from the PXI bus to the RS232 serial port of the host based on the PCI9054 chip of the PXI bus interface, has a baud rate of 9600 for serial port transmission, and provides 3.3V and 12V voltages for the dual-channel pulse excitation receiving board. The PXI bus serial port conversion communication carrier plate is connected with the dual-channel pulse excitation receiving plate through the pin header, the two-in-one board card is inserted into one slot in the PXIe-1071 case through the PXI bus socket, and the integration level is high.
The FPGA in this embodiment is EP4CE10E22 of the circle IV series of Altera corporation, which has 91 general I/O, 2 phase-locked loops, and the highest clock frequency is 325 MHz. The FPGA core system circuit comprises a 50MHz crystal oscillator for providing clock input, an EPCS16 program memory, a JTAG configuration circuit and a PLL configuration circuit. The FPGA is used as a main control unit to respectively control the generation of two paths of pulse excitation circuit driving signals and the output voltage of a DA chip in a signal conditioning circuit to control the size of echo gain and the sending and receiving of serial port end parameters.
In the embodiment, the high-voltage pulse excitation circuit is based on a field effect transistor of a high-speed switching device, the field effect transistor is controlled to be switched on and off through a logic level signal output by the FPGA to generate a high-voltage pulse signal, the high-voltage pulse signal is used for exciting a corresponding ultrasonic probe, and a received weak echo signal is amplified and filtered by a signal conditioning circuit consisting of an amplitude limiting circuit, a voltage follower, a program-controlled gain amplifier and a 7-order passive low-pass Butterworth filter in sequence and then is output to an acquisition system.
In the embodiment, the voltages of 1.2V and 2.5V required by the FPGA core system are obtained by using linear voltage regulators AMS1117-1.2 and ADP124-2.5, and the high voltage +/-100V power supply of the field effect tube is provided by a DC-DC isolation voltage-stabilizing two-way high-voltage power supply module.
Fig. 2 is a schematic diagram of an input/output interface structure of a board card, which includes a PXI bus-to-serial port communication carrier board 1, a dual-channel pulse excitation receiving board 2, a trigger input interface 3, a first channel receiving output interface 4, a first channel excitation interface 5, a trigger output interface 6, a second channel receiving output interface 7, a second channel excitation interface 8, and a PXI bus socket 9. The input and output interfaces are SMA interfaces. The first channel excitation interface 5 and the second channel excitation interface 8 of the board are respectively connected with corresponding ultrasonic probes, and the first channel receiving output interface 4 and the second channel receiving output interface 7 are respectively connected with corresponding acquisition board channels; the trigger input interface 3 is connected with the output of a servo motor encoder, the trigger output interface 6 is connected with the trigger input interface of the acquisition card, the servo motor rotates for a circle, the encoder outputs a pulse number signal with a fixed number, the pulse signal output by the servo motor encoder is used as a trigger source for exciting the receiving board card, the fixed position excitation is achieved, and the acquisition board card is triggered to acquire data during excitation. The board card is inserted into the PXIe-1071 case through the PXI bus socket 9.
Fig. 3 is a circuit diagram of a 7-step passive low-pass butterworth filter of this embodiment, in which the 3dB bandwidth is 30MHz, and the function is to prevent interference of high-frequency noise and further improve the signal-to-noise ratio of the echo signal.
Fig. 4a) -4 b) are schematic diagrams of time-frequency testing of a single-channel excitation signal after the board design is completed, where fig. 4a) is a single-cycle 2.5MHz pulse time-frequency diagram output by the program setting, and fig. 4b) is a three-cycle 5MHz pulse time-frequency diagram output by the program setting. It can be seen from the time domain waveform that the excited bipolar square wave signal has good positive and negative polarity symmetry, the amplitude of the signal is attenuated to a certain extent due to the influence of the on-resistance voltage division of the field effect transistor, when the output signal is continuous square wave pulse with 3 periods, no obvious distortion exists, and the tailing phenomenon is slightly generated due to the capacitive load. The spectrum of the excitation signal is typical of a square wave signal, and the frequency components comprise the center frequency of the signal and odd harmonics of the center frequency. The actual center frequency of the excitation signal substantially coincides with the output set value.
Fig. 5 is a schematic diagram of a test block echo signal detected by a dual-channel water immersion C scanning detection system by applying a board card, wherein the gain is set to 10dB, a 5MHz water immersion type flat probe is excited, the upper and lower surface echoes of the test block can be obviously seen from the test result, and the echo signal to noise ratio is high, so that the test block echo signal can be used for water immersion C scanning tomography detection.
Fig. 6 is a schematic structural diagram of a control program, where the FPGA control program includes a hardware logic program written by Verilog and a CPU soft core operation program generated by NIOS configuration. The PLL is a clock management IP core and is used for carrying out frequency division or frequency multiplication processing on the clock provided by the crystal oscillator and providing the clock to each control module. The CPU soft core is used for realizing the output control of the DA chip in the program control gain module, the control of a serial port transceiving program and the parameter setting of other hardware logic programs. The excitation mode selection program and the parameter selector in the embodiment realize the selection of the excitation mode of the board card, and the selection comprises two modes of repeated excitation and external (encoder) triggering; the excitation control program realizes the control of the central frequency and the number of cycles of the excitation signal.
Claims (9)
1. Two-channel high-frequency pulse excitation receiving board card based on PXI transfer serial port communication is characterized in that: the PXI bus-to-serial port communication board is connected with the dual-channel pulse excitation receiving board through pins, and one slot of the PXIe case is occupied;
the PXI bus-to-serial port communication carrier plate is connected with a PXIe-1071 case through a PXI bus socket, communication from a PXI bus to an RS232 serial port of a host is realized based on a PXI bus interface chip PCI9054, and the transmission baud rate of the serial port is 9600;
the dual-channel pulse excitation receiving plate consists of a bipolar pulse excitation circuit with two channels, an echo signal conditioning circuit, an FPGA core system circuit and a power module; the hardware design of the bipolar pulse excitation circuit and the echo conditioning circuit of the two channels is the same; the FPGA core system circuit is used as a main controller and is respectively connected with a field effect transistor driver control end in the excitation circuit and a DA chip in the echo signal conditioning circuit; the output of a field effect tube in the excitation circuit is connected with an SMA connector and is connected with the probe through a BNC wire; the SMA joint is simultaneously connected with an isolation amplitude limiting diode in the echo signal conditioning circuit.
2. The PXI-to-serial port communication-based dual-channel high-frequency pulse excitation receiving board card as claimed in claim 1, wherein: the PXI bus serial port communication carrier board can provide 3.3V and 12V voltage for the dual-channel pulse excitation receiving board.
3. The PXI-to-serial port communication-based dual-channel high-frequency pulse excitation receiving board card as claimed in claim 1, wherein: the bipolar pulse excitation circuit is formed by connecting a field effect transistor driver and an N/P channel enhanced field effect transistor, the voltage resistance of the field effect transistor is 200V, the minimum rising edge time and the minimum falling edge time during conduction are both 20ns, and bipolar high-voltage pulses with the maximum central frequency of 25MHz can be generated to excite a corresponding ultrasonic probe.
4. The PXI-to-serial port communication-based dual-channel high-frequency pulse excitation receiving board card as claimed in claim 1, wherein: the echo signal conditioning circuit consists of an isolation amplitude limiting circuit, a voltage follower, a program-controlled gain amplifier and a 7-order low-pass Butterworth filter; the cathode of the isolation amplitude limiting diode is connected with the input end of the voltage follower, the output end of the voltage follower is connected with the input end of the program-controlled gain amplifier, the output of the program-controlled gain amplifier is connected with the 7-order passive low-pass Butterworth filter, the output of the 7-order passive low-pass Butterworth filter is connected with the SMA connector, and the echo signal is connected to the acquisition card through the BNC wire through the SMA connector.
5. The PXI-to-serial port communication-based dual-channel high-frequency pulse excitation receiving board card as claimed in claim 4, wherein: the isolation amplitude limiting circuit is a parallel diode, clamps input voltage within conduction voltage of the diode, and is used for isolating high-voltage pulse generated by the exciting circuit to play a role in protecting a post-stage circuit.
6. The PXI-to-serial port communication-based dual-channel high-frequency pulse excitation receiving board card as claimed in claim 4, wherein: the voltage follower selects AD8021 as a front input buffer of a rear-stage operational amplifier to play a role in impedance matching.
7. The PXI-to-serial port communication-based dual-channel high-frequency pulse excitation receiving board card as claimed in claim 4, wherein: the programmable gain amplifier adopts a two-stage operational amplifier cascade mode, the voltage control end of the programmable gain amplifier is adjusted by controlling the output of the serial digital-to-analog converter through the FPGA, and then the function of gain adjustment is realized, the gain adjustment range is 0-80dB, and the bandwidth is 30 MHz.
8. The PXI-to-serial port communication-based dual-channel high-frequency pulse excitation receiving board card as claimed in claim 4, wherein: the 7-order low-pass Butterworth filter is used for filtering high-frequency noise and improving the signal-to-noise ratio of echo signals, and the bandwidth is 30 MHz.
9. The PXI-to-serial port communication-based dual-channel high-frequency pulse excitation receiving board card as claimed in claim 1, wherein: the power supply required by the FPGA and peripheral chips thereof in the power supply module is obtained by a linear voltage stabilizer, the power supply voltage of the field effect transistor is +/-100V, and the power supply voltage is provided by a DC-DC isolation voltage stabilization double-circuit high-voltage power supply module.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112543133A (en) * | 2020-11-25 | 2021-03-23 | 广州斯达尔科技有限公司 | Multi-channel CNS (central nervous system) collaborative exciter based on synthetic instrument and control method |
| CN113325086A (en) * | 2021-05-21 | 2021-08-31 | 北京工业大学 | Detection system based on electromagnet type electromagnetic acoustic transducer |
| CN114113344A (en) * | 2021-11-11 | 2022-03-01 | 大连理工大学 | Electromagnetic ultrasonic stress measurement system and use method |
| CN114813942A (en) * | 2022-04-13 | 2022-07-29 | 北京工业大学 | Multipurpose modularization multichannel ultrasonic detection system |
| CN116090566A (en) * | 2021-10-29 | 2023-05-09 | 合肥本源量子计算科技有限责任公司 | Quantum control device, quantum control system and quantum computer |
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- 2019-01-26 CN CN201920135547.0U patent/CN210090383U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112543133A (en) * | 2020-11-25 | 2021-03-23 | 广州斯达尔科技有限公司 | Multi-channel CNS (central nervous system) collaborative exciter based on synthetic instrument and control method |
| CN113325086A (en) * | 2021-05-21 | 2021-08-31 | 北京工业大学 | Detection system based on electromagnet type electromagnetic acoustic transducer |
| CN116090566A (en) * | 2021-10-29 | 2023-05-09 | 合肥本源量子计算科技有限责任公司 | Quantum control device, quantum control system and quantum computer |
| CN114113344A (en) * | 2021-11-11 | 2022-03-01 | 大连理工大学 | Electromagnetic ultrasonic stress measurement system and use method |
| CN114113344B (en) * | 2021-11-11 | 2023-11-07 | 大连理工大学 | Electromagnetic ultrasonic stress measurement system and use method thereof |
| CN114813942A (en) * | 2022-04-13 | 2022-07-29 | 北京工业大学 | Multipurpose modularization multichannel ultrasonic detection system |
| CN114813942B (en) * | 2022-04-13 | 2024-06-04 | 北京工业大学 | Multipurpose modularization multichannel ultrasonic detection system |
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