CN210075211U - Signal transmission circuit and device - Google Patents
Signal transmission circuit and device Download PDFInfo
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- CN210075211U CN210075211U CN201921034846.1U CN201921034846U CN210075211U CN 210075211 U CN210075211 U CN 210075211U CN 201921034846 U CN201921034846 U CN 201921034846U CN 210075211 U CN210075211 U CN 210075211U
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/1018—Means associated with receiver for limiting or suppressing noise or interference noise filters connected between the power supply and the receiver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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Abstract
The utility model provides a signal transmission circuit and equipment relates to serial communication field. The signal transmission circuit comprises a sending end branch, a receiving end branch and an input/output port. The transmitting end branch is electrically connected with the first end of the input/output port, and the receiving end branch is electrically connected with the second end of the input/output port. Wherein, a filter circuit is arranged on at least one of the transmitting end branch and the receiving end branch. This openly can make this signal transmission circuit improve the interference killing feature at the in-process filtering high frequency spurious signal of transmission signal.
Description
Cross Reference to Related Applications
The present application is based on and claims priority from application No. 201810845533.8, filed 2018, 7/27, the disclosure of which is incorporated herein by reference in its entirety.
Technical Field
The present disclosure relates to the field of serial port communications, and in particular, to a signal transmission circuit and device.
Background
In the project of 'coal changes electricity' power peak regulation, for the hot air blower which carries out networking and remote data transmission by using the LoRa wireless technology, the main board of the hot air blower controller and the LoRa wireless module are electrically connected by an inter-board connecting wire (4 cores). At present, in a common wireless module, the power supply of a main control chip MCU (Microcontroller Unit) is mostly +3.3V, and the power supply of the main control chip MCU of a household air conditioner heater/air heater is mostly + 5V. The supply voltage levels of the two chips are different. In order to ensure that signals are transmitted between the MCU and the driving chip without errors, a 3.3V and 5V power conversion chip can be added between the two chips. The power conversion circuit may be built up, for example, with a transistor or a diode, and is provided in the LoRa wireless module. And the hot air blower controller mainboard chip and the LoRa wireless module can be directly connected through a wire.
SUMMERY OF THE UTILITY MODEL
The inventor of the present disclosure finds that, in the related art, the air heater controller motherboard chip and the LoRa wireless module are directly connected by a wire, which causes the connection port on the controller motherboard chip to have the problems of stray signals, electrostatic interference, level compatibility, and the like.
The technical problem that this disclosure solved is: a signal transmission circuit is provided to reduce spurious signals.
According to an aspect of the present disclosure, there is provided a signal transmission circuit including: a sending end branch, a receiving end branch and an input/output port; the transmitting end branch is electrically connected with a first end of the input/output port, and the receiving end branch is electrically connected with a second end of the input/output port; wherein, a filter circuit is arranged on at least one of the transmitting end branch and the receiving end branch.
In some embodiments, the transmit side branch comprises a transmit side; the filter circuit comprises a first filter circuit, the first filter circuit is arranged on the transmitting end branch, the first filter circuit comprises a first resistor and a first capacitor, one end of the first resistor is electrically connected to the transmitting end, the other end of the first resistor is electrically connected to the first end of the input/output port, one end of the first capacitor is electrically connected to the transmitting end or the first end, and the other end of the first capacitor is electrically connected to the ground end.
In some embodiments, the first resistor has a resistance value of 10 Ω to 100K Ω; a capacitance value of the first capacitor is 10pF to 0.2 μ F in a case where one end of the first capacitor is electrically connected to the first end; in a case where one terminal of the first capacitor is electrically connected to the transmitting terminal, a capacitance value of the first capacitor is not greater than 33 pF.
In some embodiments, the first filter circuit further includes a second capacitor, in a case where one end of the first capacitor is electrically connected to the transmitting end, one end of the second capacitor is electrically connected to the first end, and the other end of the second capacitor is electrically connected to the ground end.
In some embodiments, the second capacitor has a capacitance value of 10pF to 0.2 μ F.
In some embodiments, the first filter circuit further includes a second capacitor, one end of which is electrically connected to the transmitting end and the other end of which is electrically connected to the ground terminal in a case where one end of the first capacitor is electrically connected to the first terminal.
In some embodiments, the second capacitor has a capacitance value of no greater than 33 pF.
In some embodiments, the receiving end branch comprises a receiving end; the filter circuit includes a second filter circuit disposed on the receiving terminal branch, the second filter circuit includes a second resistor and a third capacitor, one end of the second resistor is electrically connected to the receiving terminal, the other end of the second resistor is electrically connected to the second terminal of the input/output port, one end of the third capacitor is electrically connected to the receiving terminal or the second terminal, and the other end of the third capacitor is electrically connected to a ground terminal.
In some embodiments, the second resistor has a resistance value of 10 Ω to 100K Ω; the capacitance value of the third capacitor is 10pF to 0.2 muF.
In some embodiments, the second filtering circuit further comprises a fourth capacitor; in a case where one end of the third capacitor is electrically connected to the receiving terminal, one end of the fourth capacitor is electrically connected to the second terminal, and the other end of the fourth capacitor is electrically connected to the ground terminal; or, in a case where one end of the third capacitor is electrically connected to the second terminal, one end of the fourth capacitor is electrically connected to the receiving terminal, and the other end of the fourth capacitor is electrically connected to the ground terminal.
In some embodiments, the fourth capacitor has a capacitance value of 10pF to 0.2 μ F.
In some embodiments, a first pull-up circuit is further disposed on the receiving-end branch, the first pull-up circuit including a third resistor, one end of the third resistor being electrically connected to the receiving end or the second end, and the other end of the third resistor being electrically connected to a power supply voltage end.
In some embodiments, the third resistor has a resistance value of 100 Ω to 1M Ω.
In some embodiments, a second pull-up circuit is further disposed on the transmitting side branch, and the second pull-up circuit includes a fourth resistor, one end of which is electrically connected to the transmitting side or the first end, and the other end of which is electrically connected to a power supply voltage end.
In some embodiments, the fourth resistor has a resistance value of 100 Ω to 1M Ω.
In some embodiments, the input/output port includes a hub, the first end of the hub is a first end of the input/output port, the second end of the hub is a second end of the input/output port, the third end of the hub is electrically connected to a power supply voltage terminal, and the fourth end of the hub is electrically connected to a ground terminal.
In some embodiments, the level of the power supply voltage terminal is 5V or 3.3V.
In some embodiments, the filter circuit is disposed on the transmit side branch; the receiving end branch is directly connected to the input/output port through a wire, or a current limiting resistor is arranged on the receiving end branch.
In some embodiments, the filter circuit is disposed on the receiving-end branch; the transmitting end branch is directly connected to the input/output port through a wire, or a current limiting resistor is arranged on the transmitting end branch.
In some embodiments, the filter circuit is disposed on the transmitting end branch and the receiving end branch respectively.
In some embodiments, the transmitting side branch and the receiving side branch are respectively configured to be electrically connected with a controller motherboard chip.
In some embodiments, the input-output port is configured to electrically connect with a radio module.
According to another aspect of the present disclosure, there is provided an apparatus comprising: a signal transmission circuit as hereinbefore described.
In some embodiments, the apparatus further comprises: a controller mainboard chip and a wireless module; the controller mainboard chip and the wireless module are respectively electrically connected with the signal transmission circuit.
In some embodiments, the controller motherboard chip is a controller motherboard chip of an air heater or a controller motherboard chip of an air conditioner heater.
In the signal transmission circuit, the filter circuit is arranged on at least one of the transmitting end branch and the receiving end branch, so that the signal transmission circuit can filter high-frequency stray signals in the signal transmission process, and the anti-interference capability is improved.
Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
fig. 1 is a circuit connection diagram schematically illustrating a signal transmission circuit according to some embodiments of the present disclosure;
FIG. 2 is a circuit connection diagram schematically illustrating signal transmission circuitry according to further embodiments of the present disclosure;
FIG. 3 is a circuit connection diagram schematically illustrating signal transmission circuitry according to further embodiments of the present disclosure;
FIG. 4 is a circuit connection diagram that schematically illustrates signal transmission circuitry, in accordance with further embodiments of the present disclosure;
FIG. 5 is a circuit connection diagram schematically illustrating signal transmission circuitry according to further embodiments of the present disclosure;
FIG. 6 is a circuit connection diagram schematically illustrating signal transmission circuitry according to further embodiments of the present disclosure;
FIG. 7 is a circuit connection diagram schematically illustrating signal transmission circuitry according to further embodiments of the present disclosure;
FIG. 8 is a circuit connection diagram that schematically illustrates signal transmission circuitry, in accordance with further embodiments of the present disclosure;
fig. 9 is a block diagram that schematically illustrates an apparatus according to some embodiments of the present disclosure.
It should be understood that the dimensions of the various parts shown in the figures are not drawn to scale. Further, the same or similar reference numerals denote the same or similar components.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments are to be construed as merely illustrative, and not as limitative, unless specifically stated otherwise.
The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
In the present disclosure, when a specific device is described as being located between a first device and a second device, there may or may not be intervening devices between the specific device and the first device or the second device. When a particular device is described as being coupled to other devices, that particular device may be directly coupled to the other devices without intervening devices or may be directly coupled to the other devices with intervening devices.
All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
The inventor of the present disclosure finds that, in the related art, the air heater controller motherboard chip and the LoRa wireless module are directly connected by a wire, which causes the connection port on the controller motherboard chip to have the problems of stray signals, electrostatic interference, level compatibility, and the like.
In view of the above, the inventors of the present disclosure propose a signal transmission circuit to reduce spurious signals and the like.
Fig. 1 is a circuit connection diagram schematically illustrating a signal transmission circuit according to some embodiments of the present disclosure.
As shown in fig. 1, the signal transmission circuit may include: a transmitting side branch 110, a receiving side branch 120, and an input/output port 130. For example, the transmitting side branch 110 may include a transmitting side 111, and the receiving side branch 120 may include a receiving side 121. As shown in fig. 1, the transmitting-side branch 110 is electrically connected to a first end of the input/output port 130, and the receiving-side branch 120 is electrically connected to a second end of the input/output port 130. A filter circuit is disposed on at least one of the transmitting side branch 110 and the receiving side branch 120.
In some embodiments, as shown in fig. 1, a filter circuit 112 is disposed on the transmit side branch 110. As shown in fig. 1, the receiving end branch 120 is directly connected to the input/output port 130 through a wire. In other embodiments, a current limiting resistor or the like may be disposed on the receiving end branch 120.
In other embodiments, a filter circuit (not shown in fig. 1) may be disposed on the receiving-end branch 120. The transmitting end branch can be directly connected to the input/output port through a lead, and a current limiting resistor can also be arranged on the transmitting end branch.
In other embodiments, a filter circuit may be disposed on each of the transmitting-end branch 110 and the receiving-end branch 120.
In the signal transmission circuit of the above embodiment, by setting the filter circuit on at least one of the transmitting end branch and the receiving end branch, the signal transmission circuit can filter high-frequency stray signals in the signal transmission process, improve the anti-interference capability, and ensure the accuracy and stability of the transmitted signals as much as possible.
In some embodiments, the transmitting side branch 110 and the receiving side branch 120 are respectively configured to be electrically connected to a controller motherboard chip. For example, the transmitting end 111 and the receiving end 121 may be electrically connected to a controller motherboard chip. In some embodiments, the input-output port 130 is configured to electrically connect with a radio module. Thus, signals can be transmitted between the controller main board chip and the wireless module through the signal transmission circuit. The signal transmission circuit filters high-frequency stray signals in the signal transmission process, and the protection capability and the anti-interference capability of the main board circuit are improved.
Fig. 2 is a circuit connection diagram schematically illustrating signal transmission circuits according to further embodiments of the present disclosure.
In some embodiments, the input-output port may include a hub 230. For example, the first end of the hub 230 is the first end of the input-output port, and the second end of the hub 230 is the second end of the input-output port. Additionally, as shown in fig. 2, the third terminal of the pin block 230 is electrically connected to the power voltage terminal VDD, and the fourth terminal of the pin block 230 is electrically connected to the ground terminal.
In some embodiments, as shown in fig. 2, the filtering circuit may include a first filtering circuit 212. The first filter circuit 212 may be disposed on the transmit side branch 110. The first filter circuit 212 may include a first resistor R1 and a first capacitor C1. One end of the first resistor R1 is electrically connected to the transmitting terminal 111. The other end of the first resistor R1 is electrically connected to a first end of an input-output port (e.g., the pin header 230). One end of the first capacitor C1 is electrically connected to the transmitting end 111 (not shown in fig. 2) or a first end of the input-output port (e.g., the header 230) (shown in fig. 2). The other end of the first capacitor C1 is electrically connected to ground.
In this embodiment, the first filter circuit is formed by the first resistor and the first capacitor, and is disposed on the transmitting-end branch, so that the signal transmitted on the transmitting-end branch can be filtered. For example, high frequency spurs may be filtered out, leaving a low rate waveform such as a UART (Universal Asynchronous Receiver/Transmitter).
In addition, the first filter circuit can also play a role in electrostatic protection for the I/O port of the mainboard chip. For example, the first resistor R1 may divide and limit voltage when there is electrostatic interference, so that energy is dissipated in the form of heat through the first resistor, and therefore, the first resistor R1 may play a role in resisting static electricity, thereby improving the anti-static capability of the motherboard serial interface.
In some embodiments, the resistance value of the first resistor R1 may be 10 Ω to 100K Ω, such as 1.8K Ω. The resistance value of the first resistor R1 can be adjusted according to actual conditions.
Preferably, one end of the first capacitor C1 is electrically connected to a first end of the input-output port (e.g., the pin header 230), as shown in fig. 2. Therefore, the port damage of the controller mainboard chip caused by overlarge current in the discharging process of the first capacitor can be prevented. For example, during signal transmission, the first capacitor may be charged, and if the potential on the port side of the controller motherboard chip (the port is connected to the transmitting terminal 111, which is not shown in fig. 2) is relatively low, the first capacitor may be discharged to the port. Since the first resistor R1 is present between the first capacitor C1 and the transmitting terminal 111, the first resistor R1 can serve as a current limiting function, and therefore, the current discharged by the first capacitor C1 does not burn out the ports of the controller motherboard chip.
In the above case, for example, the capacitance value of the first capacitor C1 may be 10pF to 0.2 μ F, for example, 1 nF. The capacitance value of the first capacitor C1 can be appropriately modulated according to the degree of deformation of the communication signal waveform.
In other embodiments, one end of the first capacitor C1 is electrically connected to the transmitting end 111. In this case, a capacitor having a relatively small capacitance value may be selected as the first capacitor C1, so that the current when the first capacitor is discharged is relatively small, and the port of the controller board chip may be prevented from being burned out when the first capacitor is discharged. For example, in such a case, the capacitance value of the first capacitor C1 is ≦ 33 pF.
Fig. 3 is a circuit connection diagram schematically illustrating a signal transmission circuit according to further embodiments of the present disclosure.
In some embodiments, as shown in fig. 3, the first filter circuit 312 includes a second capacitor C2 in addition to the first resistor R1 and the first capacitor C1.
In some embodiments, as shown in fig. 3, in the case where one end of the first capacitor C1 is electrically connected to the first end of the input/output port (e.g., the header 230), one end of the second capacitor C2 is electrically connected to the transmitting terminal 111, and the other end of the second capacitor C2 is electrically connected to the ground terminal. In this case, the second capacitor C2 has a capacitance value of 33pF or less, for example, similarly to the above.
In other embodiments, in the case where one end of the first capacitor C1 is electrically connected to the transmitting terminal 111, one end of the second capacitor C2 is electrically connected to a first end of the input/output port (e.g., the header 230), and the other end of the second capacitor C2 is electrically connected to the ground terminal. In such a case, for example, the second capacitor C2 may have a capacitance value of 10pF to 0.2 μ F, e.g., 1 nF. The capacitance value of the second capacitor C2 can be appropriately modulated according to the degree of deformation of the communication signal waveform.
In the above-described embodiment, the first resistor, the first capacitor, and the second capacitor constitute the first filter circuit, and the first filter circuit is disposed on the transmitting-end branch, so that the signal transmitted on the transmitting-end branch can be filtered. For example, high frequency spurious signals may be filtered out, leaving a low rate waveform such as a UART. The first filter circuit can also play a role in electrostatic protection for the I/O port of the mainboard chip.
Fig. 4 is a circuit connection diagram schematically illustrating a signal transmission circuit according to further embodiments of the present disclosure. In contrast to the signal transmission circuit shown in fig. 2, in the signal transmission circuit shown in fig. 4, the second filter circuit 422 is provided on the receiving-side branch 121.
In some embodiments, as shown in fig. 4, the filtering circuit may include a second filtering circuit 422. The second filter circuit 422 is disposed on the receiving end branch 121.
As shown in fig. 4, the second filter circuit 422 may include a second resistor R2 and a third capacitor C3. One end of the second resistor R2 is electrically connected to the receiving terminal 121. The other end of the second resistor R2 is electrically connected to a second end of the input-output port (e.g., the pin header 230). One end of the third capacitor C3 is electrically connected to the receiving terminal 121 (shown in fig. 4) or the second end of the input/output port (not shown in fig. 4). The other end of the third capacitor C3 is electrically connected to ground.
In the above-described embodiment, the second filter circuit is formed by the second resistor and the third capacitor, and is disposed on the receiving-end branch, so that the signal transmitted on the receiving-end branch can be filtered. For example, high frequency spurious signals may be filtered out, leaving a low rate waveform such as a UART.
In addition, the second filter circuit can also play a role in electrostatic protection for the I/O port of the mainboard chip. For example, the second resistor R2 can divide and limit voltage when there is electrostatic interference, so that energy is dissipated in the form of heat through the second resistor, and therefore, the second resistor R1 can play a role in resisting static electricity, thereby improving the anti-static capability of the motherboard serial interface.
In some embodiments, the resistance value of the second resistor R2 may be 10 Ω to 100K Ω, such as 1.8K Ω. The resistance value of the second resistor R2 can be adjusted according to actual conditions.
In some embodiments, the capacitance value of the third capacitor C3 may be 10pF to 0.2 μ F, for example 1 nF. The capacitance value of the third capacitor C3 can be appropriately modulated according to the degree of deformation of the communication signal waveform.
Fig. 5 is a circuit connection diagram schematically illustrating a signal transmission circuit according to further embodiments of the present disclosure.
In some embodiments, as shown in fig. 5, the second filter circuit 522 includes a fourth capacitor C4 in addition to the second resistor R2 and the third capacitor C3.
In some embodiments, as shown in fig. 5, in the case that one end of the third capacitor C3 is electrically connected to the receiving end 121, one end of the fourth capacitor C4 is electrically connected to the second end of the input/output port (e.g., the header 230), and the other end of the fourth capacitor C4 is electrically connected to the ground.
In other embodiments, in the case that one end of the third capacitor C3 is electrically connected to the second end of the input/output port (e.g., the header 230), one end of the fourth capacitor C4 is electrically connected to the receiving end 121, and the other end of the fourth capacitor is electrically connected to the ground.
In the above embodiment, the second filter circuit is formed by the second resistor, the third capacitor and the fourth capacitor, and is disposed on the receiving-end branch, so that the signal transmitted on the receiving-end branch can be filtered. For example, high frequency spurious signals may be filtered out, leaving a low rate waveform such as a UART. The second filter circuit can also play a role in electrostatic protection for the I/O port of the mainboard chip.
In some embodiments, the capacitance value of the fourth capacitor C4 may be 10pF to 0.2 μ F, for example 1 nF. The capacitance value of the fourth capacitor C4 can be appropriately modulated according to the degree of deformation of the communication signal waveform.
Fig. 6 is a circuit connection diagram schematically illustrating a signal transmission circuit according to further embodiments of the present disclosure.
In some embodiments, as shown in fig. 6, a first pull-up circuit 621 may be further disposed on the receiving-end branch 120. The first pull-up circuit 621 may include a third resistor R3. One end of the third resistor R3 is electrically connected to a second end of the input-output port (e.g., the pin header 230). The other end of the third resistor R3 is electrically connected to the power supply voltage terminal VDD. In this fig. 6, third resistor R3 is near one side of hub 230. In some embodiments, the resistance value of the third resistor R3 may be 100 Ω to 1M Ω, e.g., 10K Ω. The resistance value of the third resistor R3 can be adjusted according to actual conditions.
Since the level shift circuit is provided in the wireless module electrically connected to the input/output port (e.g., the hub 230), and the level shift circuit includes a transistor, etc., it is necessary that the signal on the receiving end branch is at a high level to operate the transistor, a first pull-up circuit may be provided on the receiving end branch to pull up the signal on the receiving end to a power supply level. Therefore, in the above-described embodiment, by providing the first pull-up circuit on the receiving-end branch, the purpose of level compatibility can be achieved.
In other embodiments, if a pull-up resistor is built in the I/O port of the controller motherboard chip corresponding to the receiving end branch, the first pull-up circuit may not be provided on the receiving end branch.
Fig. 7 is a circuit connection diagram schematically illustrating a signal transmission circuit according to further embodiments of the present disclosure. In the signal transmission circuit shown in fig. 7, the first pull-up circuit 621 is closer to the receiving terminal 121 side than the signal transmission circuit shown in fig. 6. That is, one end of the third resistor R3 is electrically connected to the receiving terminal 121, and the other end of the third resistor R3 is electrically connected to the power supply voltage terminal VDD.
Fig. 8 is a circuit connection diagram schematically illustrating a signal transmission circuit according to further embodiments of the present disclosure.
In some embodiments, as shown in fig. 8, a second pull-up circuit 812 is also provided on the transmit side leg 110. The second pull-up circuit 812 may include a fourth resistor R4. One end of the fourth resistor R4 is electrically connected to a first end of an input-output port (e.g., the pin header 230). The other end of the fourth resistor R4 is electrically connected to the power supply voltage terminal VDD. I.e. the fourth resistor R4 may be arranged on the side close to the needle holder.
In other embodiments, one end of the fourth resistor R4 is electrically connected to the transmitting terminal 111 (not shown in fig. 8). The other end of the fourth resistor R4 is electrically connected to the power supply voltage terminal VDD. That is, the fourth resistor R4 may be provided on the side near the transmitting end.
Similarly to the first pull-up circuit, in the above-described embodiment, by providing the second pull-up circuit on the transmitting-end branch, the purpose of level compatibility can be achieved.
In some embodiments, the fourth resistor R4 may have a resistance value of 100 Ω to 1M Ω, such as 10K Ω. The resistance value of the fourth resistor R4 can be adjusted according to actual conditions.
In other embodiments, if a pull-up resistor is built in the I/O port of the controller motherboard chip corresponding to the transmitting side branch, the second pull-up circuit may not be provided on the transmitting side branch.
In the embodiment of the present disclosure, the level of the power supply voltage terminal VDD may be 5V or 3.3V. For example, when the power supply level of the controller motherboard chip is 5V, the level of the power supply voltage terminal VDD to which the signal transmission circuit is electrically connected is 5V; and under the condition that the power supply level of the controller mainboard chip is 3.3V, the level of a power supply voltage end VDD electrically connected with the signal transmission circuit is 3.3V. In this embodiment, the controller motherboard chip side can be made 5V or 3.3V voltage compatible. Of course, the scope of the present disclosure is not limited to the level values of the power supply voltage terminals disclosed herein, and the required level values may be adopted according to actual situations.
In the embodiment of the disclosure, the resistance values of the first resistor and the second resistor, and the capacitance values of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor may be adjusted according to an actual interference condition, a waveform deformation degree and an electrostatic experiment condition.
In some embodiments of the present disclosure, there is also provided an apparatus comprising a signal transmission circuit as described above. For example, the signal transmission circuit may be the signal transmission circuit shown in fig. 1 to 8.
In some embodiments, the device may further include a controller motherboard chip and a wireless module. The controller mainboard chip and the wireless module are respectively electrically connected with the signal transmission circuit.
Fig. 9 is a block diagram that schematically illustrates an apparatus according to some embodiments of the present disclosure. For example, the device may be a hot air blower or an air conditioner heater, etc.
As shown in fig. 9, the apparatus may include: a controller main board chip 901, a wireless module 902 and a signal transmission circuit 903. For example, the controller motherboard chip may be a controller motherboard chip of an air heater or a controller motherboard chip of an air conditioner heater. For example, the wireless module may be a LoRa wireless module. For example, the signal transmission circuit may be the signal transmission circuit shown in fig. 1 to 8. The controller board chip 901 and the wireless module 902 are electrically connected to the signal transmission circuit 903, respectively. For example, the controller board chip 901 is electrically connected to a transmitting end branch (e.g., a transmitting end of the transmitting end branch) and a receiving end branch (e.g., a receiving end of the receiving end branch) of the signal transmission circuit 903, respectively. The wireless module 902 is electrically connected to the input/output port of the signal transmission circuit 903.
In the device of this embodiment, the controller motherboard chip and the wireless module realize signal transmission through the signal transmission circuit, and the signal transmission circuit filters high-frequency stray signals in the process of transmitting signals, thereby improving the protection capability and the anti-interference capability of the motherboard circuit.
In an embodiment of the present disclosure, the controller motherboard chip 901 may include a power supply voltage port (e.g., 5V), a transmitting port (for the motherboard chip to transmit UART data), a receiving port (for the motherboard chip to receive UART data), and a ground port. The wireless module 902 may include a power supply voltage port (e.g., 5V), a transmit port (for the wireless module to transmit UART data), a receive port (for the wireless module to receive UART data), and a ground port.
Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (25)
1. A signal transmission circuit, comprising:
a sending end branch, a receiving end branch and an input/output port;
the transmitting end branch is electrically connected with a first end of the input/output port, and the receiving end branch is electrically connected with a second end of the input/output port;
wherein, a filter circuit is arranged on at least one of the transmitting end branch and the receiving end branch.
2. The signal transmission circuit of claim 1,
the transmitting end branch comprises a transmitting end;
the filter circuit comprises a first filter circuit arranged on the transmitting end branch,
the first filter circuit includes a first resistor having one end electrically connected to the transmitting terminal, and the other end electrically connected to the first terminal of the input/output port, and a first capacitor having one end electrically connected to the transmitting terminal or the first terminal, and the other end electrically connected to a ground terminal.
3. The signal transmission circuit of claim 2,
the resistance value of the first resistor is 10 omega to 100K omega;
a capacitance value of the first capacitor is 10pF to 0.2 μ F in a case where one end of the first capacitor is electrically connected to the first end;
in a case where one terminal of the first capacitor is electrically connected to the transmitting terminal, a capacitance value of the first capacitor is not greater than 33 pF.
4. The signal transmission circuit of claim 2,
the first filter circuit further comprises a second capacitor,
in a case where one end of the first capacitor is electrically connected to the transmitting end, one end of the second capacitor is electrically connected to the first end, and the other end of the second capacitor is electrically connected to the ground end.
5. The signal transmission circuit of claim 4,
the second capacitor has a capacitance value of 10pF to 0.2 μ F.
6. The signal transmission circuit of claim 2,
the first filter circuit further comprises a second capacitor,
in a case where one end of the first capacitor is electrically connected to the first terminal, one end of the second capacitor is electrically connected to the transmitting terminal, and the other end of the second capacitor is electrically connected to the ground terminal.
7. The signal transmission circuit of claim 6,
the second capacitor has a capacitance value of no more than 33 pF.
8. The signal transmission circuit according to any one of claims 1 to 7,
the receiving end branch comprises a receiving end;
the filter circuit includes a second filter circuit disposed on the receiving-end branch,
the second filter circuit includes a second resistor having one end electrically connected to the receiving terminal, and the other end electrically connected to the second terminal of the input/output port, and a third capacitor having one end electrically connected to the receiving terminal or the second terminal, and the other end electrically connected to a ground terminal.
9. The signal transmission circuit of claim 8,
the resistance value of the second resistor is 10 Ω to 100K Ω;
the capacitance value of the third capacitor is 10pF to 0.2 muF.
10. The signal transmission circuit of claim 8,
the second filter circuit further comprises a fourth capacitor;
in a case where one end of the third capacitor is electrically connected to the receiving terminal, one end of the fourth capacitor is electrically connected to the second terminal, and the other end of the fourth capacitor is electrically connected to the ground terminal; alternatively, the first and second electrodes may be,
in a case where one end of the third capacitor is electrically connected to the second terminal, one end of the fourth capacitor is electrically connected to the receiving terminal, and the other end of the fourth capacitor is electrically connected to the ground terminal.
11. The signal transmission circuit of claim 10,
the capacitance value of the fourth capacitor is 10pF to 0.2 muF.
12. The signal transmission circuit of claim 8,
a first pull-up circuit is also arranged on the receiving end branch,
the first pull-up circuit includes a third resistor, one end of which is electrically connected to the receiving terminal or the second terminal, and the other end of which is electrically connected to a power supply voltage terminal.
13. The signal transmission circuit of claim 12,
the resistance value of the third resistor is 100 Ω to 1M Ω.
14. The signal transmission circuit of claim 2,
a second pull-up circuit is also arranged on the transmitting end branch,
the second pull-up circuit includes a fourth resistor, one end of which is electrically connected to the transmitting terminal or the first terminal, and the other end of which is electrically connected to a power supply voltage terminal.
15. The signal transmission circuit of claim 14,
the fourth resistor has a resistance value of 100 Ω to 1M Ω.
16. The signal transmission circuit of claim 1,
the input and output port comprises a needle seat,
the first end of the needle seat is the first end of the input/output port, the second end of the needle seat is the second end of the input/output port, the third end of the needle seat is electrically connected to a power supply voltage end, and the fourth end of the needle seat is electrically connected to a grounding end.
17. The signal transmission circuit according to any one of claims 12 to 16,
the level of the power supply voltage end is 5V or 3.3V.
18. The signal transmission circuit of claim 1,
the filter circuit is arranged on the transmitting end branch; the receiving end branch is directly connected to the input/output port through a wire, or a current limiting resistor is arranged on the receiving end branch.
19. The signal transmission circuit of claim 1,
the receiving end branch is provided with the filter circuit; the transmitting end branch is directly connected to the input/output port through a wire, or a current limiting resistor is arranged on the transmitting end branch.
20. The signal transmission circuit of claim 1,
the filter circuit is respectively arranged on the transmitting end branch and the receiving end branch.
21. The signal transmission circuit of claim 1,
the transmitting end branch and the receiving end branch are respectively configured to be electrically connected with a controller mainboard chip.
22. The signal transmission circuit of claim 1,
the input-output port is configured to electrically connect with a radio module.
23. An apparatus, comprising: a signal transmission circuit as claimed in any one of claims 1 to 22.
24. The apparatus of claim 23, further comprising:
a controller mainboard chip and a wireless module;
the controller mainboard chip and the wireless module are respectively electrically connected with the signal transmission circuit.
25. The apparatus of claim 24,
the controller mainboard chip is a controller mainboard chip of an air heater or a controller mainboard chip of an air conditioner heater.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2018108455338 | 2018-07-27 | ||
| CN201810845533 | 2018-07-27 |
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| CN210075211U true CN210075211U (en) | 2020-02-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921034846.1U Active CN210075211U (en) | 2018-07-27 | 2019-07-04 | Signal transmission circuit and device |
| CN201910599549.XA Pending CN110855304A (en) | 2018-07-27 | 2019-07-04 | Signal transmission circuit and device |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910599549.XA Pending CN110855304A (en) | 2018-07-27 | 2019-07-04 | Signal transmission circuit and device |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN210075211U (en) |
| WO (1) | WO2020019631A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110855304A (en) * | 2018-07-27 | 2020-02-28 | 珠海格力电器股份有限公司 | Signal transmission circuit and device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686872A (en) * | 1995-03-13 | 1997-11-11 | National Semiconductor Corporation | Termination circuit for computer parallel data port |
| JP2002290269A (en) * | 2001-03-27 | 2002-10-04 | Sanyo Electric Co Ltd | Hybrid high frequency component and information terminal employing it |
| CN202737863U (en) * | 2012-09-05 | 2013-02-13 | 长沙威胜信息技术有限公司 | Radio communication circuit |
| CN105553505B (en) * | 2015-06-29 | 2018-10-26 | 宇龙计算机通信科技(深圳)有限公司 | Carrier wave polymerize radio circuit and communication terminal |
| CN108718219B (en) * | 2016-05-23 | 2020-08-04 | Oppo广东移动通信有限公司 | Anti-harmonic interference device for carrier aggregation, antenna device and mobile terminal |
| CN206312185U (en) * | 2016-11-17 | 2017-07-07 | 南京熊猫电子股份有限公司 | A kind of signal circuit for read write line |
| CN207460232U (en) * | 2017-12-04 | 2018-06-05 | 南京长峰航天电子科技有限公司 | A kind of signal acquisition and Transmission system for the estimation of submarine target orientation |
| WO2020019631A1 (en) * | 2018-07-27 | 2020-01-30 | 珠海格力电器股份有限公司 | Signal transmission circuit and device |
-
2018
- 2018-12-12 WO PCT/CN2018/120472 patent/WO2020019631A1/en active Application Filing
-
2019
- 2019-07-04 CN CN201921034846.1U patent/CN210075211U/en active Active
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110855304A (en) * | 2018-07-27 | 2020-02-28 | 珠海格力电器股份有限公司 | Signal transmission circuit and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110855304A (en) | 2020-02-28 |
| WO2020019631A1 (en) | 2020-01-30 |
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