CN210052737U - Fan-out circuit structure and display panel with same - Google Patents
Fan-out circuit structure and display panel with same Download PDFInfo
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- CN210052737U CN210052737U CN201921023014.XU CN201921023014U CN210052737U CN 210052737 U CN210052737 U CN 210052737U CN 201921023014 U CN201921023014 U CN 201921023014U CN 210052737 U CN210052737 U CN 210052737U
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Abstract
The application provides a fan-out circuit structure and have its display panel, fan-out circuit structure includes: at least two routing layers; and the insulating layers are filled between the adjacent signal wires, and the adjacent signal wires are positioned on different routing layers. This application can greatly reduced display panel to the requirement of exposure precision, and it has the insulating layer to fill between the signal line for the probability greatly reduced of short circuit appears because of the distance is too close in adjacent signal line, has also reduced the required precision of manufacturing equipment simultaneously, has improved the yield of product.
Description
Technical Field
The application relates to the field of displays, in particular to a fan-out circuit structure and a display panel with the same.
Background
With the increasing demand of people for the resolution of display screens, the arrangement of pixels on the display screens is very dense, especially for mobile phone screens, and the PPI (pixels per inch) of the mobile phone screens with high resolution is even as high as more than 400. The manufacturing requirement of a high PPI of a display screen on a fan-out area is high, in the prior art, a conventional fan-out area adopts the same metal wire to form a layer of signal routing, when the PPI of the display screen is high, the interval between two adjacent metal signal wires is small due to the routing mode, the ageing precision of equipment is slightly reduced, two adjacent signal routing wires with small intervals are easily connected together to form a short circuit, and the manufacturing failure is caused.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a fan-out circuit structure aims at solving the interval between the adjacent signal line too closely, appears the problem of short circuit easily.
In order to achieve the above object, the utility model provides a fan-out circuit structure, fan-out circuit structure includes: at least two routing layers; and the insulating layers are filled between the adjacent signal wires, and the adjacent signal wires are positioned on different routing layers.
Optionally, the signal line includes a straight portion and a bent portion, and the bent portion of the signal line closer to the center of the fan-out line structure is longer.
Optionally, the straight portion and the bent portion are integrally formed.
Optionally, the lengths of the signal lines are the same.
The utility model discloses still provide another kind of fan-out circuit structure, fan-out circuit structure includes: at least two routing layers; the signal lines comprise a plurality of signal sections, the adjacent signal sections are located on different routing layers on the same signal line, and the adjacent signal sections in the signal line routing direction are perpendicular to the different routing layers.
Optionally, the signal line includes a straight portion and a bending portion, and the bending portion includes a plurality of signal segments.
Optionally, the bending part of the signal wire closer to the center of the fan-out circuit structure is longer.
Optionally, the lengths of the signal lines are the same.
The utility model also provides a display panel, include as above arbitrary the fan-out circuit structure, display panel still includes driver chip and pixel unit, the input of fan-out circuit structure is connected driver chip, the output of fan-out circuit structure is connected pixel unit.
Optionally, the driving chip includes a scan driver and a source driver, the pixel includes a thin film transistor and a pixel electrode, the scan driver is connected to the thin film transistor through the fan-out line structure, and the source driver is connected to the pixel electrode through the fan-out line structure.
The utility model discloses technical scheme divide into two at least routing layers through the fan-out line structure that will connect pixel unit and source drive or gate drive, and it has the insulating layer to fill between the adjacent signal line, and adjacent signal line is located the routing layer of difference. Compared with the situation that all signal wires are arranged into one wiring layer, the distance between every two adjacent signal wires can be increased due to the arrangement mode of the signal wires on the plurality of wiring layers, the requirement on exposure precision can be greatly reduced, the insulating layers are filled between the signal wires, the probability that the adjacent signal wires are short-circuited due to too close distance is greatly reduced, the precision requirement of manufacturing equipment is reduced, and the yield of products is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an embodiment of a fan-out circuit structure of the present application;
FIG. 2 is an enlarged view of a portion of FIG. 1 at A;
FIG. 3 is an enlarged view of a portion of FIG. 1 at B;
fig. 4 is a partial enlarged view of the further embodiment at B in fig. 1.
The reference numbers illustrate:
the implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that all the directional indications (such as up, down, left, right, front, and rear … …) in the embodiment of the present application are only used to explain the relative position relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indication is changed accordingly.
In addition, the descriptions referred to as "first", "second", etc. in this application are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
As shown in fig. 1, the present application proposes a fan-out wiring structure 10, the fan-out wiring structure 10 including: at least two routing layers; and the insulating layers are filled between the adjacent signal lines 13, and the adjacent signal lines 13 are positioned on different routing layers.
In this embodiment, the electrical connection between each pixel unit and the gate driver or the source driver is implemented by the fan-out line structure 10, so that signals of the gate driver or the source driver are transmitted to the pixel unit, the signal lines 13 forming the fan-out line structure 10 are arranged to form at least two routing layers, and two adjacent signal lines 13 are located on different routing layers. Taking the arrangement of the signal lines 13 of the fan-out line structure 10 as two layers as an example, one signal line 13 on the second routing layer is arranged between two adjacent signal lines 13 on the first routing layer, as shown in fig. 2 and fig. 3, the signal line 132 is located on the first routing layer, and the signal line 133 is located on the second routing layer, so that the first routing layer has enough space to set the arrangement distance between the signal lines 13 to a safe distance that does not cause short circuit, the requirement on the exposure precision can be greatly reduced, the probability of occurrence of short circuit of the adjacent signal lines 13 is greatly reduced, and meanwhile, the precision requirement of the manufacturing equipment is also reduced. In the embodiment, the space between the signal lines 13 is filled with an insulating material to form an insulating layer (not shown), so that the finished fan-out wiring structure 10 is represented as a whole with the signal lines 13 and the insulating material bonded to each other, and the signal lines 13 are in the insulating material and arranged as at least two routing layers.
In the manufacturing process of the fan-out circuit structure 10, the signal lines 132 on the first routing layer are arranged first, and the adjacent signal lines 132 are spaced at a proper distance, so that the two adjacent signal lines 132 filled with the insulating material will not form a short circuit due to the close distance. After the first routing layer is arranged, an insulating material is laid on the first routing layer to enable the signal wires 132 to be filled with the insulating material, then the signal wires 133 are arranged on the insulating material to form a second routing layer, the signal wires 133 of the second routing layer are located in the interval of the adjacent signal wires 132 of the first routing layer, and only one signal wire 13 on the adjacent routing layer is arranged in the interval of every two adjacent signal wires 13 on the same routing layer. After the second routing layer is arranged, an insulating material is laid on the second routing layer so that the spaces between the signal lines 133 are filled with the insulating material. The rest of the hierarchy is performed in the same steps.
The routing layer number of the fan-out routing structure 10 is determined according to the number of the signal lines 13, when the number of the pixel units is large, the routing layer number can be increased so that a safety distance which can not cause short circuit is reserved between the adjacent signal lines 13 on the same layer, in this embodiment, the distance between the adjacent routing layers is greater than or equal to the safety distance so as to avoid short circuit between the adjacent signal lines 13 on different routing layers, and when the safety distance reaches a critical value, the projection of the adjacent signal lines 13 can be overlapped.
The signal line 13 comprises a straight line part 11 and a bent part 12, and the bent part 12 of the signal line 13 closer to the center of the fan-out circuit structure 10 is longer; the signal lines 13 are the same length.
Since the electrical connection between each pixel unit and the gate driver or the source driver is implemented by the fan-out line structure 10, the voltage on the pixel unit is input through the fan-out line structure 10, and therefore, in order to avoid the voltage from being different in voltage value after the voltage is lost and reaches each pixel, the lengths of the signal lines 13 should be as equal as possible, so that the resistances of the signal lines 13 are the same. However, the same source driver or gate driver transmits signals to a plurality of pixel units, so that the input end of the fan-out wiring structure 10 is small and the output end is large, resulting in a longer bending portion 12 being required for a signal line 13 closer to the center of the fan-out wiring structure 10 to accommodate a change in distance. In one embodiment, the signal line 13 is extended to detour the bent portion 12, and the bent portion 12 having a plurality of bends is formed.
In this embodiment, the straight portion 11 and the bent portion 12 are integrally formed, so as to reduce the manufacturing process of the signal line 13 and reduce the production cost.
As shown in fig. 4, the present application also proposes another fan-out wiring structure 10, the fan-out wiring structure 10 including: at least two routing layers; the signal lines 13 are filled with insulating layers between the adjacent signal lines 13, each signal line 13 comprises a plurality of signal segments 131, the adjacent signal segments 131 on the same signal line 13 are located on different routing layers, and the adjacent signal segments 131 perpendicular to the routing direction of the signal lines 13 are located on different routing layers.
In this embodiment, the electrical connection between each pixel unit and the gate driver or the source driver is implemented by the fan-out line structure 10, so that the signals of the gate driver or the source driver are transmitted to the pixel unit, a plurality of signal lines 13 forming the fan-out line structure 10 are arranged to form at least two routing layers, two adjacent signal lines 13 are located on different routing layers, the same signal line 13 is formed by different signal segments 131, and the adjacent signal segments 131 are respectively located on different routing layers. Taking the arrangement of the signal lines 13 of the fan-out line structure 10 as two layers as an example, one signal line 13 on the second routing layer is arranged between two adjacent signal lines 13 on the first routing layer, so that the first routing layer has enough space to set the arrangement distance between the signal lines 13 to a safe distance that does not cause short circuit, and the adjacent signal segments 131 on the same signal line 13 are respectively positioned on two adjacent routing layers to increase the distance between the adjacent signal lines 13 on the adjacent routing layers, thereby greatly reducing the requirements on exposure precision, greatly reducing the probability of short circuit of the adjacent signal lines 13, and simultaneously reducing the precision requirement of the manufacturing equipment. In the embodiment, the space between the signal lines 13 is filled with an insulating material to form an insulating layer, so that the finished fan-out wiring structure 10 is represented by the signal lines 13 and the insulating material being combined with each other, and the signal lines 13 are in the insulating material and arranged as at least two routing layers.
In this embodiment, since the adjacent signal segments 131 on the same signal line 13 are located on different routing layers, in the manufacturing process of the fan-out circuit structure 10, the adjacent signal segments 131 on the same signal line 13 are arranged in two steps: the signal segments 131 of the signal lines 13 on the first routing layer are arranged first, and the adjacent signal lines 13 are spaced apart by a suitable distance, so that the two adjacent signal lines 132 filled with the insulating material do not form a short circuit due to the close distance. After the first routing layer is arranged, an insulating material is laid on the first routing layer to enable the space between the signal wires 13 to be filled with the insulating material, then the insulating material of the adjacent signal sections 131 at the connecting positions is removed, then the signal sections 131, located on the second routing layer, of the signal wires 13 are arranged on the insulating material, the adjacent signal sections 131, which belong to the same signal wire 13 and are located on different routing layers, are connected into the same signal wire 13 at the positions where the insulating material is removed, the signal wires 13 of the second routing layer are located in the interval of the adjacent signal wires 13 of the first routing layer, and only one signal wire 13 of the adjacent routing layer is arranged in the interval of every two adjacent signal wires 13 on the same routing layer. After the second routing layer is arranged, an insulating material is laid on the second routing layer to fill the space between the signal lines 133 with the insulating material, and then the insulating material of the adjacent signal segments 131 at the connection positions is removed. The rest of the hierarchy is performed in the same steps.
The routing layer number of the fan-out routing structure 10 is determined according to the number of the signal lines 13, when the number of the pixel units is large, the routing layer number can be increased so that a safety distance which can not cause short circuit is reserved between the adjacent signal lines 13 on the same layer, in this embodiment, the distance between the adjacent routing layers is greater than or equal to the safety distance so as to avoid short circuit between the adjacent signal lines 13 on different routing layers, and when the safety distance reaches a critical value, the projection of the adjacent signal lines 13 can be overlapped.
Optionally, the signal line 13 includes a straight portion 11 and a bent portion 12, and the bent portion 12 includes a plurality of signal segments 131; the lengths of the signal lines 13 are the same; the bent portion 12 of the signal line 13 closer to the center of the fan-out wiring structure 10 is longer.
Since the electrical connection between each pixel unit and the gate driver or the source driver is implemented by the fan-out line structure 10, the voltage on the pixel unit is input through the fan-out line structure 10, and therefore, in order to avoid the voltage from being different in voltage value after the voltage is lost through the fan-out circuit and reaches each pixel, the lengths of the signal lines 13 should be as equal as possible, so that the resistances of each signal line 13 are the same. However, the same source driver or gate driver transmits signals to a plurality of pixel units, so that the input end of the fan-out wiring structure 10 is small and the output end is large, resulting in a longer bending portion 12 being required for a signal line 13 closer to the center of the fan-out wiring structure 10 to accommodate a change in distance. In one embodiment, the signal line 13 is extended to detour the bent portion 12, and the bent portion 12 having a plurality of bends is formed.
In a specific implementation, each of the straight portion 11 and the bent portion 12 may be formed by connecting a plurality of signal segments 131, and adjacent signal segments 131 are located on different routing layers; only the bending portion 12 may be formed by connecting a plurality of signal segments 131, and adjacent signal segments 131 are located on different routing layers.
The application further provides a display panel, which includes the fan-out line structure 10, the display panel further includes a driving chip and a pixel unit, an input end of the fan-out line structure 10 is connected to the driving chip, and an output end of the fan-out line structure 10 is connected to the pixel unit; the driving chip comprises a scanning driver and a source driver, the pixel comprises a thin film transistor and a pixel electrode, the scanning driver is connected to the thin film transistor through the fan-out line structure 10, and the source driver is connected to the pixel electrode through the fan-out line structure 10.
As an embodiment, the electrical connection between each pixel unit and the gate driver or the source driver is implemented by the fan-out circuit structure 10, so that the signal of the gate driver or the source driver is transmitted to the pixel unit, the input end of the fan-out circuit structure 10 is connected to the gate driver or the source driver, the output end is connected to the pixel unit, and the fan-out circuit structure 10 transmits the electrical signal of the gate driver or the source driver to the pixel unit.
Because the signal lines 13 of the fan-out circuit structure 10 are arranged in multiple layers, and the arrangement distance between the signal lines 13 is greater than or equal to the safe distance, the requirement on the exposure precision can be greatly reduced, the probability of short circuit caused by too close distance between the adjacent signal lines 13 is greatly reduced, and meanwhile, the precision requirement of manufacturing equipment is also reduced, even if the manufacturing equipment is aged, and the precision is reduced to a certain degree, the quality of a product can not be influenced by continuous use, the production cost is reduced, and the yield of the display panel is improved.
The above description is only an alternative embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the structure, which can be directly or indirectly applied to other related technical fields within the spirit of the present application are included in the scope of the present application.
Claims (10)
1. A fan-out wiring structure, comprising:
at least two routing layers;
and the insulating layers are filled between the adjacent signal wires, and the adjacent signal wires are positioned on different routing layers.
2. The fan-out wiring structure of claim 1, wherein the signal lines comprise straight portions and bent portions, and the bent portions of the signal lines are longer closer to a center position of the fan-out wiring structure.
3. The fan-out wiring structure of claim 2, wherein the bent portion is integrally formed with the straight portion.
4. The fanout line structure of claim 1, wherein the number of signal lines are the same length.
5. A fan-out wiring structure, comprising:
at least two routing layers;
the signal lines comprise a plurality of signal sections, the adjacent signal sections are located on different routing layers on the same signal line, and the adjacent signal sections in the signal line routing direction are perpendicular to the different routing layers.
6. The fan-out wiring structure of claim 5, wherein a signal line comprises a straight portion and a bent portion, the bent portion comprising a plurality of signal segments.
7. The fan-out wiring structure of claim 5, wherein the bend of the signal line closer to the center of the fan-out wiring structure is longer.
8. The fan-out wiring structure of claim 5, wherein the lengths of the plurality of signal lines are the same.
9. A display panel comprising the fan-out line structure of any one of claims 1-8, the display panel further comprising a driver chip and a pixel unit, wherein an input of the fan-out line structure is connected to the driver chip, and an output of the fan-out line structure is connected to the pixel unit.
10. The display panel of claim 9, wherein the driving chip comprises a scan driver and a source driver, the pixel comprises a thin film transistor and a pixel electrode, the scan driver is connected to the thin film transistor through the fan-out line structure, and the source driver is connected to the pixel electrode through the fan-out line structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921023014.XU CN210052737U (en) | 2019-06-27 | 2019-06-27 | Fan-out circuit structure and display panel with same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921023014.XU CN210052737U (en) | 2019-06-27 | 2019-06-27 | Fan-out circuit structure and display panel with same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210052737U true CN210052737U (en) | 2020-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921023014.XU Active CN210052737U (en) | 2019-06-27 | 2019-06-27 | Fan-out circuit structure and display panel with same |
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| Country | Link |
|---|---|
| CN (1) | CN210052737U (en) |
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2019
- 2019-06-27 CN CN201921023014.XU patent/CN210052737U/en active Active
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