CN210052532U - Multi-layer unit NAND flash memory - Google Patents

Abstract

The utility model provides a multi-layer unit NAND flash memory, the NAND string that is connected with different bit lines is connected to different source lines, source line connection to corresponding source voltage selector, and all source voltage selector's voltage input end is connected to one or more source voltage generater. The input parameter terminal of the source voltage selector may be connected to the latch module of the corresponding bit line sensing circuit.

Description

Multi-layer unit NAND flash memory

Technical Field

The utility model relates to an integrated circuit field especially relates to a multilayer unit NAND flash memory.

Background

A NAND flash memory is a widely used nonvolatile semiconductor memory. Regarding the basic structure, basic principle and sensing circuit of NAND Flash memory, in the book Rino Micheloni, Luca Crippa, Alessia Marelli (2010) "Inside NAND Flash Memories" New York: chapter 2, chapter 8, chapter 10, and chapter 16 of Springer Science + Business Media, are discussed in detail. These sections of the book are incorporated by reference into this text.

In general, a NAND flash memory includes a flash cell array 102, a read/write circuit 103, an input-output buffer 104, a control circuit 101, a column decoder 105, and a row decoder 106, as shown in fig. 1. The flash cell array 102 includes a plurality of NAND strings 201(NAND strings), and the NAND strings 201 are composed of two select gates and flash cells 310 (cells) connected in series between the two select gates. In the prior art scheme, the bit line 202 and source line 203 in the read/write circuit 103 are connected to the NAND string 201 as shown in FIG. 2. The drain terminal of the NAND string 201 is connected to one of the bit lines 202, and the source terminals of all of the NAND strings 201 are connected to the same source line 203. A plurality of NAND strings 201 make up one block 210. In one block 210, a plurality of flash memory cells 310 in the NAND string 201, which are in the same relative position, constitute one word line 204(word line).

Circuits in the flash cell array 102 and the read/write circuit 103 related to one block 210 are shown in fig. 3. Bit line 202 is coupled to sense circuit 303, and sense circuit 303 is coupled to latch module 302. The gates of the flash memory cells 310 in the same wordline 204 are connected to the same gate voltage selector 301, and each gate voltage selector 301 is connected to a gate voltage generator 300.

Fig. 4 illustrates a flash memory cell 310. Note that the voltage at source 403 is V _SThe voltage at drain 402 is V _DThe voltage of the gate 401 is V _G. In general, V _D>V _S，V _G>V _S. Note V _GS＝V _G-V _S. Threshold voltage V of cell _THIs determined by the amount of charge in the memory layer 400. When V is _GS>V _THWhen so, the cell is turned on. For a Floating Gate Flash (Floating Gate Flash), the storage layer 400 corresponds to a Floating Gate; for a Charge Trap type Flash memory (Charge Trap Flash), the storage Layer 400 corresponds to a Charge Trap Layer (Charge Trap Layer).

SLC NAND flash can store 1 bit per cell. And one cell of the multi-level cell NAND flash memory can store a plurality of bits, wherein each cell in the MLC NAND flash memory can store 2 bits, each cell in the TLC NAND flash memory can store 3 bits, and each cell in the QLC NAND flash memory can store 4 bits.

In the NAND flash memory, the principle of data read and write operations of the cells is as follows. For a NAND flash memory cell storing n bits, the range of possible threshold voltages is 2 ⁿ1 reference threshold voltage, split into 2 ⁿAnd a threshold voltage interval. Each threshold voltage interval corresponds toThe unit can store one data. When data is written into a cell, the amount of charge on the memory layer can be adjusted in accordance with the data so that the threshold voltage of the cell is in a threshold voltage range corresponding to the data. By setting V _GSEqual to a certain reference threshold voltage and the conductivity of the cell is measured, the threshold voltage of the cell can be compared with the reference threshold voltage. When reading data in the cell, the threshold voltage may be compared with a plurality of reference threshold voltages for a plurality of times, and a threshold voltage interval in which the threshold voltage of the cell is located is determined, thereby determining the data to be read stored in the cell. One comparison of the cell threshold voltage and the reference voltage is referred to as a Single Read Operation (SRO).

The gate voltage generator 300 generates one reference threshold voltage (V) in one sensing operation of the flash memory storing n bits per cell _READ) And a voltage V slightly larger than all threshold voltage intervals _PASSThe gate voltage selector 301 corresponding to the word line to be tested selects V _READThe gate voltage selectors 301 corresponding to the other word lines select V _PASS。

In the current solution, all the cells in the word line to be tested have the same gate voltage and the same source voltage, so that the threshold voltage of each cell can only be compared with the same reference threshold voltage in one sensing operation. Since the data stored in each cell in the word line to be tested is not necessarily the same, all the reference threshold voltages need to be sequentially applied to the gate line of the word line to be tested in one reading operation of all the bits stored in the word line to be tested. That is, in a flash memory storing n bits per cell, one read operation for reading all bits of one cell or one verify operation in writing data requires 2 ⁿ1 sensing operation. Thus, as n increases, read and write performance decreases rapidly, while average latency and power consumption increase rapidly.

SUMMERY OF THE UTILITY MODEL

To the problem that exists among the prior art, the utility model provides a multi-layer unit NAND flash memory. In the multi-level cell NAND flash memory, the sources of NAND strings connected to different bit lines are connected to different source lines. When the multi-layer unit NAND flash memory is sensed, the source voltages of the NAND strings connected with different bit lines can take different values.

The multi-layer unit NAND flash memory comprises a flash memory unit array, a read/write circuit, an input/output buffer area, a control circuit, a row decoder and a column decoder.

The flash memory cell array comprises a plurality of NAND strings, wherein each NAND string comprises two selection gates and flash memory cells connected between the two selection gates in series.

The input/output buffer includes one or more page buffers for temporary storage during data reading and writing.

The control circuit includes an on-chip address decoder and a state machine for providing the required hardware address and control signals.

The row decoder and the column decoder are used for addressing the flash memory unit array through given hardware addresses.

The multi-level cell NAND flash memory includes a voltage generator, and the read/write circuit includes a plurality of bit lines, source voltage selectors, bit line sensing circuits, and latch modules in equal number. The voltage generator provides a plurality of output voltages, and the output voltages comprise the difference between the grid voltage of the word line to be tested and the reference threshold voltage. The bit lines, the source lines, the voltage selectors, the sensing circuits and the latch modules all have a one-to-one correspondence relationship. The source terminal of any of the NAND strings is connected to a source line and the drain terminal is connected to a corresponding bit line. The voltage input end of any voltage selector is connected with the output end of the voltage generator, and the output end of the voltage selector is connected with the source line.

In another embodiment of the present invention, the input parameter terminal of any one of the voltage selectors is connected to the output terminal of the latch module.

In another embodiment of the present invention, the multi-level cell NAND flash memory is a 3D multi-level cell NAND flash memory.

The beneficial effects of the utility model are that, through increasing a voltage generator and a plurality of source voltage selector for the source voltage of each NAND string that is connected to different bit lines can independently be adjusted, therefore make the gate voltage of each unit of word line that awaits measuring and the difference of source voltage can independently be adjusted, and then make the sensing relevant with the unit state and the verification relevant with the programming target value become possible, the sensing relevant with the unit state and the verification relevant with the programming target value can increase substantially the throughput of flash memory, reduce the average delay and the energy consumption of flash memory.

Drawings

FIG. 1 is a block diagram of a NAND flash memory device.

FIG. 2 is a schematic diagram of the connections of bit lines, word lines and NAND strings in a prior art scheme.

Fig. 3 is a simplified illustration of the circuitry associated with one block in a prior art scheme.

FIG. 4 is an exemplary diagram of a NAND flash memory cell.

FIG. 5 is a schematic diagram of the connections of bit lines, word lines and NAND strings in a multi-level cell NAND flash memory.

FIG. 6 is a simplified example diagram of circuitry associated with one block in a multi-level cell NAND flash memory.

FIG. 7 is a schematic diagram of the connections of bit lines, word lines and NAND strings in a 3D multi-level cell NAND flash memory.

Detailed Description

To the problem that exists among the prior art, the embodiment of the utility model provides a multi-layer unit NAND flash memory.

Fig. 1 is an exemplary diagram of a NAND flash memory according to an embodiment of the present invention. The NAND flash memory includes a flash cell array 102, a read/write circuit 103, an input-output buffer 104, a control circuit 101, a column decoder 105, and a row decoder 106. Input-output buffer 104 includes one or more page buffers for temporary storage during data read and write processes. The control circuit 101 comprises an on-chip address decoder and a state machine for providing the required hardware address and control signals. A column decoder 105 and a row decoder 106 for addressing the flash memory cell array 102 by a given hardware address.

Fig. 5 illustrates a connection relationship of a NAND string 501 with a bit line 502 and a source line 503 in the flash memory cell array 102 according to the present embodiment. The flash cell array 102 includes a plurality of NAND strings 501, the NAND strings 501 being composed of two select gates and flash cells connected in series between the two select gates. In the prior art scheme, the bit line 502 and source line 503 in the read/write circuit 103 are connected to the NAND string 501 as shown in FIG. 5. The drain terminal of the NAND string 501 is connected to a certain bit line 502, the source terminal is connected to a corresponding source line 503, the source line 503 is connected to a corresponding source voltage selector 521, and all the source voltage selectors 521 are connected to one source voltage generator 522. Multiple NAND strings 501 make up one block 510. In one block 510, a plurality of cells in the NAND string 501, which are identical in relative position, constitute one word line 504.

Fig. 6 illustrates a circuit related to one block 510 in the flash cell array 102 and the read/write circuit 103 according to the present embodiment. The bit line 502 is coupled to a sense circuit 603, and the sense circuit 603 is coupled to a latch module 602. The gates of the cells in the same word line 504 are connected to the same gate voltage selector 601, and each gate voltage selector 601 is connected to a gate voltage generator 600. The bit line 502, the source line 503, the source voltage selector 521, the sensing circuit 603 and the latch module 602 all have a one-to-one correspondence.

In a sensing operation of the flash memory storing n bits per cell, the gate voltage generator 600 generates a voltage V slightly larger than all threshold voltage intervals _READAnd one is slightly larger than V _READDouble voltage V _PASSThe gate voltage selector 601 corresponding to the word line to be tested selects V _READThe gate voltage selectors 601 corresponding to the other word lines select V _PASS. Source voltage generator 522 generates 2 including the difference between the wordline gate voltage under test and the respective reference threshold voltages ⁿ1 voltage, the source voltage selector 521 selects the voltage generated by one of the source voltage generators 522.

In the multi-level cell NAND flash memory described in this embodiment, the differences between the gate voltages and the source voltages of all the cells in the word line to be tested are not necessarily equal, and thus the threshold voltages of the cells can be compared with different reference threshold voltages in one sensing operation.

In another embodiment of the present invention, the input parameter terminal of any of the source voltage selectors 521 is connected to the output terminal of its corresponding latch module 602.

The present embodiment can perform sensing related to the cell state, as follows. In multiple sensing operations of a multi-level cell NAND flash memory, the adjustment of the source voltage of each NAND string is determined by the previous sensing result of the NAND string, and at a given source voltage, if a NAND string is turned on, the NAND string selects only a higher source voltage than it in the subsequent sensing operation; if a NAND string is non-conductive, it will only select the lower source voltage than it in subsequent sense operations.

Cell-related sensing includes, but is not limited to, binary serial sensing, which is described in detail below. The difference between the given unit to be tested grid voltage and all possible reference voltages in the threshold voltage range forms a selection set of source voltage; setting the source voltage of the NAND string where the unit to be tested is positioned as the middle value of the selection set; performing a sensing operation to check whether the NAND string of each unit to be tested is conducted; if the NAND string where a unit to be tested is located is conducted, the threshold voltage of the unit is smaller than the current V _GSThus, the range of possible threshold voltages can be narrowed to less than V _GSThe selection set of the corresponding ground source voltage is also reduced to a half larger than the current intermediate value, and if the NAND string where a unit to be tested is located is not conducted, the threshold voltage of the unit is larger than the current V _GSThus, the range of possible threshold voltages can be narrowed to be larger than V _GSThe selection set of the corresponding ground source voltage is also reduced to a half smaller than the current intermediate value; and repeating the sensing operation until the data to be read in the unit to be tested is determined.

Under the condition of storing n bits per unit, the multi-layer unit NAND flash memory can determine the threshold voltage of each unit in the word line to be tested only by n times of sensing operation through a binary serial sensing method, and is required by the prior art2 of (2) ⁿCompared with 1 sensing operation, the read performance of the flash memory is greatly improved, and the average delay and the energy consumption of the flash memory are reduced.

The present invention can perform verification related to a programmed target value as follows. In one verify operation, the source voltage of each NAND string is determined by the target value of the cell to be written contained therein. If the NAND string is not conductive, where the cell to be written has reached the target threshold voltage, masking the NAND string in subsequent programming and verification operations; if the NAND string is turned on, where the cell to be written has not reached the target threshold voltage, the NAND string is not masked in subsequent program and verify operations.

In the case of storing n bits per cell, the multi-level cell NAND flash memory of the present invention can determine whether the cell to be written is to reach the target threshold voltage by programming the verification method associated with the target value only 1 sensing operation, 2 compared to the prior art ⁿCompared with 1 sensing operation, the writing performance of the flash memory is greatly improved, and the average delay and the energy consumption of the flash memory are reduced.

The embodiment of the invention provides a 3D multi-layer unit NAND flash memory. The circuitry associated with a block in the memory array is shown in fig. 7. Wherein the source line 703 and the bit line 702 are parallel to each other and to the substrate; the NAND strings 711 are all perpendicular to the substrate, with their source terminals connected to a source line 703 and their drain terminals connected to corresponding bit lines 702; flash memory cells located in the same plane parallel to the substrate are connected to the same gate line 701. The gate line 701 is connected to a gate voltage selector, and all the gate voltage selectors are connected to the output end of a gate voltage generator; the bit line 702 is connected to the sensing circuit, which is connected to the latch module; the source lines 503 are connected to corresponding source voltage selectors, all of which are connected to the output of one or more source voltage generators.

Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. It is therefore intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.

Claims (6)

1. A multi-layer unit NAND flash memory comprises a flash memory unit array, a read/write circuit, an input/output buffer area, a control circuit, a row decoder and a column decoder, and is characterized in that in the read/write circuit, the source electrodes of NAND strings connected with different bit lines are connected to independent source lines, and the source lines are in one-to-one correspondence with the bit lines.

2. The multi-level cell NAND flash memory of claim 1 wherein each source line is connected to an output of a corresponding voltage selector.

3. The multi-level cell NAND flash memory of claim 2 including one or more voltage generators providing a plurality of output voltages including the difference between the word line gate voltage to be tested and respective reference threshold voltages.

4. The multi-level cell NAND flash memory of claim 3 wherein the voltage selector has a plurality of voltage inputs coupled to the output of the voltage generator.

5. The MLC NAND flash memory of claim 4, wherein the input parameter of the voltage selector is coupled to the output of the latch module of the corresponding bit line sense circuit.

6. The MLC NAND flash memory of any of claims 1-5, wherein the MLC NAND flash memory is a 3D MLC NAND flash memory.

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