CN210041791U - Interface device and control circuit thereof - Google Patents
Interface device and control circuit thereof Download PDFInfo
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- CN210041791U CN210041791U CN201920931806.0U CN201920931806U CN210041791U CN 210041791 U CN210041791 U CN 210041791U CN 201920931806 U CN201920931806 U CN 201920931806U CN 210041791 U CN210041791 U CN 210041791U
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Abstract
The utility model discloses an interface device and a control circuit thereof, wherein the control circuit comprises a first switch control branch and a second switch control branch; one end of the first switch control branch is electrically connected with an interface end of the interface equipment and a first end of the second switch control branch respectively, and the other end of the first switch control branch is electrically connected with a second end of the second switch control branch; when the interface end is connected with an external high-voltage power supply, the first switch control branch is in a saturated state, and the second switch control branch is in a disconnected state. The utility model designs a reverse high-voltage protection circuit of a first switch control branch and a second switch control branch, when the interface end is connected with an external high-voltage power supply, the first switch control branch is in a saturated state while the second switch control branch is in a disconnected state, thereby the interface equipment has the function of preventing high voltage and the hardware cost of a high-voltage module is reduced; in addition, the device also has the advantages of high response speed, small volume and the like.
Description
Technical Field
The utility model relates to a circuit design technical field, in particular to interface device and control circuit thereof.
Background
In order to achieve the purpose of preventing high voltage, the conventional interface device generally adopts a high-voltage-prevention Load Switch (Load Switch), but the price of the high-voltage-prevention Load Switch is much more expensive (for example, 6 times) than that of the common Load Switch which is not high-voltage-prevention, so that the conventional interface device with the high-voltage-prevention function has the problem of high cost.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is to provide an interface device and control circuit thereof in order to overcome all there is the higher defect of cost for interface device among the prior art.
The utility model discloses an above-mentioned technical problem is solved through following technical scheme:
the utility model provides a control circuit of interface equipment, which comprises a first switch control branch and a second switch control branch;
one end of the first switch control branch is electrically connected with an interface end of the interface device and a first end of the second switch control branch respectively, and the other end of the first switch control branch is electrically connected with a second end of the second switch control branch;
when the interface end is connected with an external high-voltage power supply, the first switch control branch is in a saturated state, and the second switch control branch is in a disconnected state.
Optionally, the control circuit further includes a load switch and a control chip;
the load switch is electrically connected with the third end of the second switch control branch and the control chip respectively;
the load switch is also electrically connected with a first power supply end;
the control chip is used for controlling the load switch to be in a disconnected state when recognizing that the interface end is not connected with the external equipment;
the control chip is further used for identifying that the interface end is connected to the external device and controlling the load switch to be in a connection state.
Optionally, the control chip is electrically connected to the interface end and the enable end of the interface device, respectively;
the first switch control branch comprises a transistor and a first resistor;
the second switch control branch comprises a first MOS (metal-oxide-semiconductor field effect transistor);
a base electrode of the transistor is electrically connected with one end of the first resistor, an emitting electrode of the transistor is electrically connected with the interface end and a source electrode of the first MOS tube respectively, a collecting electrode of the transistor is electrically connected with a grid electrode of the first MOS tube, and a drain electrode of the first MOS tube is electrically connected with the load switch;
the other end of the first resistor is electrically connected with the interface end;
when the interface end is connected with an external high-voltage power supply, the control chip is used for recognizing that the interface end is connected with the external high-voltage power supply and controlling and adjusting the resistance value of the first resistor to enable the transistor to be in a saturated state and the first MOS tube to be in a disconnected state.
Optionally, the first switch control branch further includes a second resistor and a zener diode;
the other end of the first resistor is electrically connected with one end of the second resistor and one end of the voltage stabilizing diode respectively, and the other end of the second resistor is electrically connected with an interface end;
the other end of the voltage stabilizing diode is grounded.
Optionally, the control circuit further comprises a first capacitor;
one end of the first capacitor is electrically connected with the interface end, and the other end of the first capacitor is grounded.
Optionally, the control chip is electrically connected to the interface end and the enable end of the interface device, respectively;
the control circuit further comprises a third switch control branch;
one end of the third switch control branch is electrically connected with the enabling end of the interface device, and the other end of the third switch control branch is electrically connected with the grid electrode of the first MOS tube;
when the interface end is connected with an external device, the control chip is used for identifying that the interface end is connected with the external device;
the control chip is further configured to control an enable end of the interface device to input a low level, so that the other end of the third switch control branch outputs the low level, the first MOS transistor is in a conducting state, and the load switch inputs a first power source to the external device through the interface end.
Optionally, the third switch control branch includes a second MOS transistor and a third resistor;
the grid electrode of the second MOS tube is electrically connected with the enabling end of the interface device, the drain electrode of the second MOS tube is electrically connected with one end of the third resistor, the other end of the third resistor is electrically connected with the grid electrode of the first MOS tube, and the source electrode of the second MOS tube is grounded.
Optionally, the third switch control branch further includes a third MOS transistor and a second capacitor;
the grid electrode of the third MOS tube is electrically connected with the enabling end of the interface device, and the drain electrode of the third MOS tube is electrically connected with one end of the second capacitor and the grid electrode of the second MOS tube respectively;
and the source electrode of the third MOS tube and the other end of the second capacitor are grounded.
Optionally, the control circuit further comprises a fourth resistor, a second power supply terminal, and a fifth resistor;
one end of the fourth resistor is electrically connected with the second power supply end, and the other end of the fourth resistor is electrically connected with the drain electrode of the third MOS transistor;
one end of the fifth resistor is electrically connected with the interface end, and the other end of the fifth resistor is electrically connected with the other end of the third resistor.
Optionally, the control circuit further comprises a fourth switch control branch;
one end of the fourth switch control branch is electrically connected with the interface end, and the other end of the fourth switch control branch is grounded;
when the interface end is disconnected with the external equipment, the control chip is used for identifying that the interface end is disconnected with the external equipment;
the control chip is further configured to control an enable end of the interface device to input a high level, so that the fourth switch control branch is in a conducting state, and the residual charges in the interface end are discharged to the ground.
Optionally, the fourth switch control branch comprises a fourth MOS transistor and a sixth resistor;
the grid electrode of the fourth MOS tube is electrically connected with the enabling end of the interface equipment;
the drain electrode of the fourth MOS tube is electrically connected with one end of the sixth resistor, the source electrode of the fourth MOS tube is grounded, and the other end of the sixth resistor is electrically connected with the interface end;
and when the interface end is disconnected with the external equipment, the fourth MOS tube is conducted.
Optionally, the control circuit further comprises a third capacitor;
one end of the third capacitor is electrically connected with the grid electrode of the fourth MOS tube, and the other end of the third capacitor is grounded.
Optionally, the interface end is a Type-C interface (a kind of interface); and/or the presence of a gas in the gas,
the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are PMOS tubes.
The utility model also provides an interface device, interface device includes foretell interface device's control circuit.
The utility model discloses an actively advance the effect and lie in:
in the utility model, by designing a reverse high-voltage protection circuit of the first switch control branch and the second switch control branch, when the interface end is connected with an external high-voltage power supply, the first switch control branch is in a saturated state while the second switch control branch is in an off state, so that the interface equipment has a high-voltage prevention function, the hardware cost of the high-voltage module is reduced, and the market competitiveness of the interface equipment is effectively enhanced; in addition, the device also has the advantages of high response speed, small volume and the like.
Drawings
Fig. 1 is a circuit diagram of a control circuit of an interface device according to embodiment 1 of the present invention.
Fig. 2 is a circuit diagram of a control circuit of an interface device according to embodiment 2 of the present invention.
Fig. 3 is a schematic diagram of the high voltage protection of the control circuit of the interface device according to embodiment 2 of the present invention.
Fig. 4 is a first circuit diagram of a control circuit of an interface device according to embodiment 3 of the present invention.
Fig. 5 is a second circuit diagram of the control circuit of the interface device according to embodiment 3 of the present invention.
Fig. 6 is a first circuit diagram of a control circuit of an interface device according to embodiment 4 of the present invention.
Fig. 7 is a second circuit diagram of the control circuit of the interface device according to embodiment 4 of the present invention.
Detailed Description
The present invention is further illustrated by way of the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 1, the control circuit of the interface device of the present embodiment includes a first switch control branch L1 and a second switch control branch L2.
Specifically, one end of the first switch control branch L1 is electrically connected to the interface terminal CONN of the interface device and the first end of the second switch control branch L2, respectively, and the other end of the first switch control branch L1 is electrically connected to the second end of the second switch control branch L2;
when the interface terminal CONN is connected to the external high-voltage power supply, the first switch control branch L1 is in a saturated state, and the second switch control branch L2 is in a disconnected state.
In the embodiment, by designing the reverse high-voltage protection circuit of the first switch control branch and the second switch control branch, when the interface end is connected to the external high-voltage power supply, the first switch control branch is in a saturated state while the second switch control branch is in a disconnected state, so that the interface equipment has a high-voltage prevention function, the hardware cost of the high-voltage module is reduced, and the market competitiveness of the interface equipment is effectively enhanced; in addition, the device also has the advantages of high response speed, small volume and the like.
Example 2
The control circuit of the interface device of the present embodiment is a further improvement of embodiment 1, specifically:
as shown in fig. 2, the control circuit further includes a Load Switch and a control chip CC;
the Load Switch is electrically connected with the third end of the second Switch control branch L1 and the control chip 2 respectively;
the Load Switch is also electrically connected with the first power supply end;
the control chip 2 is used for controlling the Load Switch to be in a disconnected state when recognizing that the interface terminal CONN is not connected to the external equipment;
the control chip 2 is further configured to control the Load Switch to be in a connected state when recognizing that the interface terminal CONN is connected to the external device.
The control chip 2 is electrically connected with an interface terminal CONN and an enable terminal EN of the interface device respectively.
Specifically, the first switch control branch L1 includes a transistor Q1, a first resistor R1, a second resistor R2, a zener diode CR, and a first capacitor C1.
The second switch control branch L2 includes a first MOS transistor Q2;
a base electrode of the transistor Q1 is electrically connected with one end of the first resistor R1, an emitter electrode of the transistor Q1 is electrically connected with a interface end CONN and a source electrode of the first MOS transistor Q2 respectively, a collector electrode of the transistor Q1 is electrically connected with a gate electrode of the first MOS transistor Q2, and a drain electrode of the first MOS transistor Q2 is electrically connected with a Load Switch;
the other end of the first resistor R1 is electrically connected to the interface terminal CONN;
when the interface terminal CONN is connected to the external high-voltage power supply, the control chip 2 is configured to recognize that the interface terminal CONN is connected to the external high-voltage power supply, and control and adjust the resistance of the first resistor R1 so that the transistor Q1 is in a saturated state, and the first MOS transistor Q2 is in a disconnected state.
The other end of the first resistor R1 is electrically connected with one end of the second resistor R2 and one end of the zener diode CR, respectively, and the other end of the second resistor R2 is electrically connected with the interface terminal CONN;
the other end of the zener diode CR is grounded.
One end of the first capacitor C1 is electrically connected to the interface terminal CONN, and the other end of the first capacitor C1 is grounded.
In this embodiment, when the interface terminal CONN is connected to a high voltage, the transistor Q1 can be turned on quickly and in a saturation state by adjusting the resistance of the first resistor R1, so that the voltage VGS of the gate and the source of the first MOS transistor Q2 is 0, and at this time, the first MOS transistor Q2 is turned off, so as to isolate the high voltage and perform a high voltage protection function.
The transistor Q1 is adopted to guarantee the response speed, the voltage change situation can be quickly responded, and the reaction time is effectively shortened.
In addition, compared with the existing high-voltage-resistant load switch, the price of the reverse high-voltage protection circuit module formed by the first switch control branch and the second switch control branch is skillfully combined by using low-price components, so that the high voltage is isolated by quick response, and the design cost and the input cost of the circuit are effectively reduced.
Specifically, as shown in fig. 3, the abscissa represents time t (unit s) and the ordinate represents voltage U (unit V). The curve a represents the voltage change curve corresponding to the load switch, the curve b represents the voltage change curve in the interface end, and the curve c represents the voltage change curve of the accessed external voltage, wherein the voltage gradually rises in the section d of the curve c, and meanwhile, the corresponding voltage in the curve a is pulled down, so that the function of high-voltage protection is achieved.
In the embodiment, by designing the reverse high-voltage protection circuit of the first switch control branch and the second switch control branch, when the interface end is connected to the external high-voltage power supply, the first switch control branch is in a saturated state while the second switch control branch is in a disconnected state, so that the interface equipment has a high-voltage prevention function, the hardware cost of the high-voltage module is reduced, and the market competitiveness of the interface equipment is effectively enhanced; in addition, the device also has the advantages of high response speed, small volume and the like.
Example 3
As shown in fig. 4, the control circuit of the interface device of the present embodiment is a further improvement of embodiment 2, specifically:
the control circuit further comprises a third switch control branch L3;
one end of the third switch control branch L3 is electrically connected to the enable end EN of the interface device, and the other end of the third switch control branch L3 is electrically connected to the gate of the first MOS transistor Q2;
when the CONN is connected to the external device, the control chip 2 is used for recognizing that the CONN is connected to the external device;
the control chip 2 is further configured to control an enable end EN of the interface device to input a low level, so that the other end of the third Switch control branch L3 outputs the low level, the first MOS transistor Q2 is in a conducting state, and the Load Switch inputs the first power supply to the external device through the interface end CONN.
Specifically, as shown in fig. 5, the third switch control branch L3 includes a second MOS transistor Q3, a third resistor R3, a third MOS transistor Q4, and a second capacitor C2.
The gate of the second MOS transistor Q3 is electrically connected to the enable terminal EN of the interface device, the drain of the second MOS transistor Q3 is electrically connected to one end of the third resistor R3, the other end of the third resistor R3 is electrically connected to the gate of the first MOS transistor Q2, and the source of the second MOS transistor Q3 is grounded.
The gate of the third MOS transistor Q4 is electrically connected to the enable end EN of the interface device, and the drain of the third MOS transistor Q4 is electrically connected to one end of the second capacitor C2 and the gate of the second MOS transistor Q3, respectively;
the source of the third MOS transistor Q4 and the other end of the second capacitor C2 are both grounded.
The control circuit further comprises a fourth resistor R4, a second power supply terminal and a fifth resistor R5;
one end of the fourth resistor R4 is electrically connected to the second power supply terminal 2, and the other end of the fourth resistor R4 is electrically connected to the drain of the third MOS transistor Q4;
one end of the fifth resistor R5 is electrically connected to the interface terminal CONN, and the other end of the fifth resistor R5 is electrically connected to the other end of the third resistor R3.
In the control circuit of this embodiment, when the interface terminal CONN is connected to the external device, the enable terminal EN of the interface device inputs a low level, the third MOS transistor Q4 is turned off, the second MOS transistor Q3 is turned on, the first MOS transistor Q2 is turned on, and the load switch outputs the +5V power input by the first power supply terminal to the interface terminal CONN through the first MOS transistor Q2 to supply power to the external device.
In this embodiment, by designing a reverse high-voltage protection circuit of the first switch control branch and the second switch control branch, when the interface end is connected to the external high-voltage power supply, the first switch control branch is in a saturated state while the second switch control branch is in a disconnected state, so that the interface device has a high-voltage prevention function; the hardware cost of the high-voltage module is reduced, and the market competitiveness of the interface equipment is effectively enhanced; in addition, the device also has the advantages of high response speed, small volume and the like; meanwhile, the third switch controls the branch circuit to realize the normal charging function of the interface equipment to the external equipment.
Example 4
The control circuit of the interface device of the present embodiment is a further improvement of embodiment 3, specifically:
as shown in fig. 6, the control circuit further includes a fourth switch control branch L4;
one end of the fourth switch control branch L4 is electrically connected to the interface end CONN, and the other end of the fourth switch control branch L4 is grounded;
when the CONN is disconnected with the external equipment, the control chip 2 is used for recognizing that the CONN is disconnected with the external equipment;
the control chip 2 is further configured to control the enable terminal EN of the interface device to input a high level, so that the fourth switch control branch L4 is in a conducting state, and discharge the residual charges in the interface terminal CONN to ground.
Specifically, as shown in fig. 7, the fourth switch control branch L4 includes a fourth MOS transistor Q5 and a sixth resistor R6;
the grid electrode of the fourth MOS tube Q5 is electrically connected with an enable end EN of the interface device;
the drain of the fourth MOS transistor Q5 is electrically connected to one end of a sixth resistor R6, the source of the fourth MOS transistor Q5 is grounded, and the other end of the sixth resistor R6 is electrically connected to an interface terminal CONN;
when the interface terminal CONN is disconnected from the external device, the fourth MOS transistor Q5 is turned on.
The control circuit further comprises a third capacitor C3;
one end of the third capacitor C3 is electrically connected to the gate of the fourth MOS transistor Q5, and the other end of the third capacitor C3 is grounded.
The first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are PMOS tubes.
Additionally, the interface end includes, but is not limited to, a Type-C interface.
In the control circuit of this embodiment, after the external device is pulled out from the interface terminal CONN, the interface terminal CONN may have residual charges, and the residual charges need to be discharged in consideration of the influence of the interface terminal of the residual charges on the initialization operation of the external device that is accessed next time; specifically, a high level is input through an enable terminal EN of the interface device, so that the first MOS transistor Q2 and the second MOS transistor Q3 are both turned off, the fourth MOS transistor Q5 is turned on, and the residual charges are directly and rapidly discharged to the ground.
In addition, the circuit in the embodiment has flexible design, and the protection point can be adjusted by changing the resistance value of the external resistor.
In this embodiment, by designing a reverse high-voltage protection circuit of the first switch control branch and the second switch control branch, when the interface end is connected to the external high-voltage power supply, the first switch control branch is in a saturated state while the second switch control branch is in a disconnected state, so that the interface device has a high-voltage prevention function; the hardware cost of the high-voltage module is reduced, and the market competitiveness of the interface equipment is effectively enhanced; in addition, the device also has the advantages of high response speed, small volume and the like; meanwhile, the normal charging mode of the interface equipment is realized through the third switch control branch; in addition, the fourth switch control branch circuit is used for discharging residual charges at the interface end when the external equipment is pulled out of the interface end, so that normal initialization can be guaranteed when the external equipment is connected again.
Example 5
The interface device of this embodiment includes the control circuit of the interface device in any one of embodiments 1 to 4.
The interface device in the embodiment can not only supply power to the external device, but also has the function of high voltage prevention; in addition, when the external equipment is pulled out of the interface end, residual charges of the interface end are discharged, so that the external equipment can be normally initialized when being connected again.
Although specific embodiments of the present invention have been described above, it will be understood by those skilled in the art that this is by way of example only and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and the principles of the present invention, and these changes and modifications are all within the scope of the present invention.
Claims (14)
1. A control circuit for an interface device, the control circuit comprising a first switch control branch and a second switch control branch;
one end of the first switch control branch is electrically connected with an interface end of the interface device and a first end of the second switch control branch respectively, and the other end of the first switch control branch is electrically connected with a second end of the second switch control branch;
when the interface end is connected with an external high-voltage power supply, the first switch control branch is in a saturated state, and the second switch control branch is in a disconnected state.
2. The control circuit of an interface device of claim 1, wherein the control circuit further comprises a load switch and a control chip;
the load switch is electrically connected with the third end of the second switch control branch and the control chip respectively;
the load switch is also electrically connected with a first power supply end;
the control chip is used for controlling the load switch to be in a disconnected state when recognizing that the interface end is not connected with the external equipment;
the control chip is further used for identifying that the interface end is connected to the external device and controlling the load switch to be in a connection state.
3. The control circuit of the interface device according to claim 2, wherein the control chip is electrically connected to an interface terminal and an enable terminal of the interface device, respectively;
the first switch control branch comprises a transistor and a first resistor;
the second switch control branch comprises a first MOS tube;
a base electrode of the transistor is electrically connected with one end of the first resistor, an emitting electrode of the transistor is electrically connected with the interface end and a source electrode of the first MOS tube respectively, a collecting electrode of the transistor is electrically connected with a grid electrode of the first MOS tube, and a drain electrode of the first MOS tube is electrically connected with the load switch;
the other end of the first resistor is electrically connected with the interface end;
when the interface end is connected with an external high-voltage power supply, the control chip is used for recognizing that the interface end is connected with the external high-voltage power supply and controlling and adjusting the resistance value of the first resistor to enable the transistor to be in a saturated state and the first MOS tube to be in a disconnected state.
4. The control circuit of the interface device of claim 3 wherein said first switch control branch further comprises a second resistor and a zener diode;
the other end of the first resistor is electrically connected with one end of the second resistor and one end of the voltage stabilizing diode respectively, and the other end of the second resistor is electrically connected with an interface end;
the other end of the voltage stabilizing diode is grounded.
5. The control circuit of an interface device of claim 1, wherein the control circuit further comprises a first capacitor;
one end of the first capacitor is electrically connected with the interface end, and the other end of the first capacitor is grounded.
6. The control circuit of the interface device according to claim 3, wherein the control chip is electrically connected to an interface terminal and an enable terminal of the interface device, respectively;
the control circuit further comprises a third switch control branch;
one end of the third switch control branch is electrically connected with the enabling end of the interface device, and the other end of the third switch control branch is electrically connected with the grid electrode of the first MOS tube;
when the interface end is connected with an external device, the control chip is used for identifying that the interface end is connected with the external device;
the control chip is further configured to control an enable end of the interface device to input a low level, so that the other end of the third switch control branch outputs the low level, the first MOS transistor is in a conducting state, and the load switch inputs a first power source to the external device through the interface end.
7. The control circuit of the interface device of claim 6 wherein said third switch control branch comprises a second MOS transistor and a third resistor;
the grid electrode of the second MOS tube is electrically connected with the enabling end of the interface device, the drain electrode of the second MOS tube is electrically connected with one end of the third resistor, the other end of the third resistor is electrically connected with the grid electrode of the first MOS tube, and the source electrode of the second MOS tube is grounded.
8. The control circuit of the interface device of claim 7 wherein said third switch control branch further comprises a third MOS transistor and a second capacitor;
the grid electrode of the third MOS tube is electrically connected with the enabling end of the interface device, and the drain electrode of the third MOS tube is electrically connected with one end of the second capacitor and the grid electrode of the second MOS tube respectively;
and the source electrode of the third MOS tube and the other end of the second capacitor are grounded.
9. The control circuit for an interface device of claim 8, wherein said control circuit further comprises a fourth resistor, a second power supply terminal, and a fifth resistor;
one end of the fourth resistor is electrically connected with the second power supply end, and the other end of the fourth resistor is electrically connected with the drain electrode of the third MOS transistor;
one end of the fifth resistor is electrically connected with the interface end, and the other end of the fifth resistor is electrically connected with the other end of the third resistor.
10. The control circuit of an interface device of claim 8, wherein the control circuit further comprises a fourth switch control branch;
one end of the fourth switch control branch is electrically connected with the interface end, and the other end of the fourth switch control branch is grounded;
when the interface end is disconnected with the external equipment, the control chip is used for identifying that the interface end is disconnected with the external equipment;
the control chip is further configured to control an enable end of the interface device to input a high level, so that the fourth switch control branch is in a conducting state, and the residual charges in the interface end are discharged to the ground.
11. The control circuit of the interface device of claim 10 wherein said fourth switch control branch comprises a fourth MOS transistor and a sixth resistor;
the grid electrode of the fourth MOS tube is electrically connected with the enabling end of the interface equipment;
the drain electrode of the fourth MOS tube is electrically connected with one end of the sixth resistor, the source electrode of the fourth MOS tube is grounded, and the other end of the sixth resistor is electrically connected with the interface end;
and when the interface end is disconnected with the external equipment, the fourth MOS tube is conducted.
12. The control circuit of an interface device of claim 11, wherein the control circuit further comprises a third capacitor;
one end of the third capacitor is electrically connected with the grid electrode of the fourth MOS tube, and the other end of the third capacitor is grounded.
13. The control circuit of an interface device of claim 11, wherein the interface port is a Type-C interface; and/or the presence of a gas in the gas,
the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are PMOS tubes.
14. An interface device, characterized in that it comprises a control circuit of an interface device according to any one of claims 1 to 13.
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| CN201920931806.0U CN210041791U (en) | 2019-06-20 | 2019-06-20 | Interface device and control circuit thereof |
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| CN201920931806.0U CN210041791U (en) | 2019-06-20 | 2019-06-20 | Interface device and control circuit thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110113040A (en) * | 2019-06-20 | 2019-08-09 | 无锡睿勤科技有限公司 | Interface equipment and its control circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110113040A (en) * | 2019-06-20 | 2019-08-09 | 无锡睿勤科技有限公司 | Interface equipment and its control circuit |
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| GR01 | Patent grant |