CN210007622U - IP lock-forbidden circuit - Google Patents
IP lock-forbidden circuit Download PDFInfo
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- CN210007622U CN210007622U CN201920984681.8U CN201920984681U CN210007622U CN 210007622 U CN210007622 U CN 210007622U CN 201920984681 U CN201920984681 U CN 201920984681U CN 210007622 U CN210007622 U CN 210007622U
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Abstract
The utility model relates to a circuit of kinds of IP forbidden locks, including grade step-down circuit and network interface seat or network transformer connection, be used for getting the electricity from network interface seat or network transformer and step down and export for the 12V direct current, grade step-down circuit still is connected with a plurality of second grade step-down circuits, second grade step-down circuit is used for stepping down the 12V direct current that grade step-down circuit output and exports for 5V direct current or 3.3V direct current, grade step-down circuit is connected with the power end of network interface seat or network transformer and realizes getting the electricity, step down the standard voltage that supplies power through POE power supply mode and exports for the 12V direct current, and second grade step-down circuit step-down the 12V direct current that grade step-down circuit output and exports for 5V or 3.3V direct current, in order to adapt to different circuit practical demands, and still be equipped with a plurality of second grade step-down circuits, in order to adapt to the demand of different components and parts.
Description
Technical Field
The utility model relates to an forbids lock technical field, more specifically says, relates to kind of IP forbids circuit of locking.
Background
Most of current IP forbidden locks use the POE mode to supply power, and voltage is about 48V generally, and its vary voltage circuit uses the transformer to step down mostly, causes the product volume great, and is with high costs, and calorific capacity is big, can't satisfy people's user demand.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in, to prior art's above-mentioned defect, it is simple, with low costs to provide kinds of circuits, and small IP forbids the circuit of lock.
The utility model provides a technical scheme that its technical problem adopted is:
the circuit for constructing IP forbidden locks comprises a -level step-down circuit, wherein the -level step-down circuit is connected with a network interface seat or a network transformer and used for taking electricity from the network interface seat or the network transformer and reducing the electricity into 12V direct current for output, the -level step-down circuit is further connected with a plurality of secondary step-down circuits, the secondary step-down circuits are used for reducing the 12V direct current output by the -level step-down circuit into 5V direct current or 3.3V direct current for output, the positive electrode of the power output of the network interface seat or the positive electrode of the power output of the network transformer is the positive electrode of a power supply, and the negative electrode of the power output of the network interface seat or the negative electrode of the power output of the network transformer is the negative electrode.
The utility model discloses a circuit of IP forbidden lock, wherein, level step-down circuit includes the power conversion chip, the 7 th pin of power conversion chip is connected with resistance, the th resistance ends in addition with the power supply positive pole is connected and still is connected with field effect transistor, the drain electrode of field effect transistor with the power supply positive pole is connected, the grid of field effect transistor is connected with the second resistance, the ends in addition of second resistance with the 6 pin of power conversion chip is connected;
the 7 pin of the power conversion chip is also connected with a third resistor, an th capacitor and a second capacitor, the anode of the th capacitor is connected with the 7 pin of the power conversion chip, the other 0 end of the second capacitor is connected with the cathode of the 1 th capacitor and is also connected with a 2 th diode, the cathode of the 3 th diode is respectively connected with the other end of the second capacitor, the cathode of the th capacitor and the 5 pin of the power conversion chip, the anode of the th diode is connected with the cathode of the power supply, the other end of the third resistor is connected with a fourth resistor, a fifth resistor and a third capacitor and is also connected with the 2 pin of the power conversion chip, the other end of the fourth resistor is connected with the cathode of the th diode, and the other end of the fifth resistor and the other end of the third capacitor are both connected with the 1 pin of the power conversion chip;
the power conversion device comprises a power conversion chip, a field effect transistor, a power conversion chip, a power source, a power conversion chip, a power source and a power supply, wherein a sixth resistor, a seventh resistor, a fourth capacitor and a fifth capacitor are connected to a pin 3 of the power conversion chip, the other end of the sixth resistor is connected with a source electrode of the field effect transistor, the other end of the fourth capacitor is connected with a pin 4 of the power conversion chip, the other end of the seventh resistor is connected with a pin 8 of the power conversion chip, the pin 4 of the power conversion chip is further connected with the sixth capacitor, the pin 8 of the power conversion chip is further connected with a seventh capacitor in parallel, and a pin 4 and a pin 8 of the power conversion chip are further connected with an eighth;
the grid of the field effect transistor is further connected with a ninth resistor, the other end of the ninth resistor is connected with the cathode of the diode, the source of the field effect transistor is further connected with a tenth resistor, the other 0 end of the tenth resistor is connected with the cathode of the 1 diode and is further connected with a 2 th inductor, the other 4 end of the 3 inductor is connected with a tenth resistor, an eighth capacitor and a second diode, the other ends of the tenth resistor and the eighth capacitor are both connected with the cathode of the power supply, the anode of the second diode is connected with the other end of the inductor, the cathode of the second diode is connected with a 7 pin of the power supply conversion chip, and the other end of the inductor is a 12V anode output end of the -level voltage reduction circuit.
IP forbidding circuit of lock, wherein, second grade step-down circuit includes the step-down chip, the VIN end of step-down chip be connected with twelfth resistance and ninth electric capacity and still with level step-down circuit's the anodal output of 12V is connected, the other end of twelfth resistance with the step-down chip's the positive output of 
The LX end of the voltage reduction chip is connected with a tenth capacitor and a second inductor, the other end of the tenth capacitor is connected with the BST end of the voltage reduction chip, and the other end of the second inductor is the positive electrode output end of the secondary voltage reduction circuit;
the FB end of the voltage reduction chip is also connected with a thirteenth resistor and a fourteenth resistor, the other end of the thirteenth resistor is connected with the other end of the second inductor, the other end of the fourteenth resistor is connected with the negative electrode of the power supply, the GND end of the voltage reduction chip is also connected with the negative electrode of the power supply, the other end of the second inductor is also connected with a tenth capacitor, and the other end of the tenth capacitor is connected with the negative electrode of the power supply.
IP forbidden circuit of lock, wherein, the resistance of thirteenth resistance is 30.9K omega, the resistance of fourteenth resistance is 5.76K omega, the inductance value of second inductance is 4.7uH, just the voltage of second grade step-down circuit's anodal output is 5V.
IP forbidden circuit of lock, wherein, the resistance of thirteenth resistance is 30.9K omega, the resistance of fourteenth resistance is 9.76K omega, the inductance value of second inductance is 4.7uH, just the voltage of second grade step-down circuit's positive output end is 3.3V.
IP forbidding circuit of lock, wherein, the model of power conversion chip is TD 3845A.
The circuit of IP forbidden lock, wherein, the model of step-down chip is PL 5920.
The beneficial effects of the utility model reside in that level step-down circuit is connected with network interface seat or network transformer's power end and is realized getting the electricity to the standard voltage step-down that will supply power through POE power supply mode exports for the 12V direct current, and the 12V direct current step-down that second grade step-down circuit exported level step-down circuit is exported for 5V or 3.3V direct current, in order to adapt to different circuit practical demands, and still be equipped with a plurality of second grade step-down circuits, in order to adapt to the demand of different components and parts to different voltages, it is simple to realize the circuit, and is with low costs, small, and suitability is general.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be described below with reference to the accompanying drawings and embodiments in steps, the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts:
fig. 1 is a circuit diagram of a level voltage step-down circuit of the IP disable lock circuit of the preferred embodiment of the present invention;
fig. 2 is a circuit diagram of a two-stage voltage-dropping circuit of the IP lock-disable circuit according to the preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, a clear and complete description will be given below with reference to the technical solutions of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
The IP lock-forbidden circuit of the preferred embodiment of the utility model is shown in figure 1, refer to figure 2 at the same time, comprises a -level step-down circuit 100, a -level step-down circuit 100 is connected with a network interface seat (not shown in the figure) or a network transformer (not shown in the figure) (the -level step-down circuit 100 is connected with the network interface seat to be suitable for a mode of using an idle signal line for power supply, and the -level step-down circuit 100 is connected with the network transformer to be suitable for a mixed power supply mode, namely, a power supply and a signal are separated through the network transformer) for taking power from the network interface seat or the network transformer and reducing the power into 12V direct current for output;
the -level voltage reduction circuit 100 is connected with a power supply end of a network interface seat or a network transformer to achieve power taking so as to reduce standard voltage supplied by a POE power supply mode into 12V direct current to be output, the secondary voltage reduction circuit 200 reduces the 12V direct current output by the -level voltage reduction circuit 100 into 5V or 3.3V direct current to be output so as to meet practical requirements of different circuits, the secondary voltage reduction circuit 200 is further provided so as to meet the requirements of different components on different voltages, and the power supply circuit is simple in implementation, low in cost, small in size and wide in applicability .
As shown in fig. 1 and fig. 2, the -stage voltage reduction circuit 100 includes a power conversion chip U1, a 7 th pin of the power conversion chip U1 is connected with a th resistor R1, another end of the th resistor R1 is connected with a positive electrode of a power supply and is also connected with a field effect transistor Q1, a drain of the field effect transistor Q1 is connected with the positive electrode of the power supply, a gate of the field effect transistor Q1 is connected with a second resistor R2, and another end of the second resistor R2 is connected with a 6 th pin of the power conversion chip U1;
the other end of the third resistor R is connected with a fourth resistor R, a fifth resistor R and a third capacitor C, and is also connected with the pin 2 of the power conversion chip U, the other end of the fourth resistor R is connected with the negative electrode of the second diode D, and the other end of the fifth resistor R and the other end of the third capacitor C are both connected with the pin 1 of the power conversion chip U;
a pin 3 of the power conversion chip U1 is connected with a sixth resistor R9, a seventh resistor R8, a fourth capacitor C5 and a fifth capacitor C8, the other end of the sixth resistor R9 is connected with the source electrode of the field effect transistor Q1, the other end of the fourth capacitor C5 is connected with a pin 4 of the power conversion chip U1, the other end of the seventh resistor R8 is connected with a pin 8 of the power conversion chip U1, the pin 4 of the power conversion chip U1 is also connected with the sixth capacitor C7, the pin 8 is connected with the seventh capacitor C6, the pin 4 and the pin 8 of the power conversion chip U1 are also connected with an eighth resistor R7 in parallel, and the cathode of a diode D1 is also connected with the other ends of the fifth capacitor C8, the sixth capacitor C7 and the seventh capacitor C6 respectively;
the grid of the field-effect tube Q is further connected with a ninth resistor R, the other end of the ninth resistor R is connected with the cathode of a second diode D, the source of the field-effect tube Q is further connected with a tenth resistor R, the other 0 end of the tenth resistor R is connected with the cathode of the 1 st diode D and is further connected with a 2 nd inductor L, the other 4 end of the 3 rd inductor L is connected with a tenth resistor R, an eighth capacitor C and a second diode D, the other ends of the tenth resistor R and the eighth capacitor C are both connected with the cathode of a power supply, the anode of the second diode D is connected with the other end of the second inductor L, the cathode of the second diode D is connected with a 7 pin of a power supply conversion chip U, the other end of the second inductor L is a 12V anode output end of the stage voltage reduction circuit 100, and the circuit is simple, low in cost, small in size and 5-wide applicability.
As shown in fig. 1 and fig. 2, the two-stage buck circuit 200 includes a buck chip U2, a VIN terminal of the buck chip U2 is connected to a twelfth resistor R21 and a ninth capacitor C22, and is further connected to a 12V positive output terminal of the -stage buck circuit 100, another terminal of the twelfth resistor R21 is connected to a positive output terminal of the buck chip U2
The LX end of the voltage reduction chip U2 is connected with a tenth capacitor C24 and a second inductor L2, the other end of the tenth capacitor C24 is connected with the BST end of the voltage reduction chip U2, and the other end of the second inductor L2 is the anode output end of the secondary voltage reduction circuit 200;
the FB end of the voltage reduction chip U2 is further connected with a thirteenth resistor R22 and a fourteenth resistor R23, the other end of the thirteenth resistor R22 is connected with the other end of the second inductor L2, the other end of the fourteenth resistor R23 is connected with the negative electrode of a power supply, the GND end of the voltage reduction chip U2 is also connected with the negative electrode of the power supply, the other end of the second inductor L2 is further connected with a tenth capacitor C23, the other end of the tenth capacitor C23 is connected with the negative electrode of the power supply, and the voltage reduction chip U2 is simple in circuit, low in cost, small in size and high in applicability .
As shown in fig. 1 and fig. 2, the resistance of the thirteenth resistor R22 is 30.9K Ω, the resistance of the fourteenth resistor R23 is 5.76K Ω, the inductance of the second inductor L2 is 4.7uH, and the voltage at the positive output terminal of the secondary buck circuit 200 is 5V; the resistance values of the thirteenth resistor R22 and the fourteenth resistor R23 affect the output voltage.
As shown in fig. 1 and fig. 2, the resistance of the thirteenth resistor R22 is 30.9K Ω, the resistance of the fourteenth resistor R23 is 9.76K Ω, the inductance of the second inductor L2 is 4.7uH, and the voltage at the positive output terminal of the secondary buck circuit 200 is 3.3V; the resistance values of the thirteenth resistor R22 and the fourteenth resistor R23 affect the output voltage.
As shown in fig. 1 and fig. 2, the power conversion chip U1 has a model TD 3845A; small volume and simple use.
As shown in FIG. 1 and FIG. 2, the buck chip U2 has model number PL5920, and the output voltage is wide.
It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are considered to be within the scope of the invention as defined by the following claims.
Claims (7)
- The circuit for the IP forbidden locks of 1 and types comprises a -level step-down circuit, and is characterized in that the -level step-down circuit is connected with a network interface seat or a network transformer and used for taking electricity from the network interface seat or the network transformer and reducing the electricity into 12V direct current for output, the -level step-down circuit is further connected with a plurality of secondary step-down circuits, the secondary step-down circuits are used for reducing the 12V direct current output by the -level step-down circuit into 5V direct current or 3.3V direct current for output, the power output positive pole of the network interface seat or the power output positive pole of the network transformer is the power supply positive pole, and the power output negative pole of the network interface seat or the power output negative pole of the network transformer is the power supply negative pole.
- 2. The IP disable-lock circuit of claim 1, wherein the level voltage-reducing circuit comprises a power conversion chip, a th resistor is connected to a 7 th pin of the power conversion chip, the other end of the th resistor is connected to the positive power supply electrode and is further connected to a field effect transistor, a drain of the field effect transistor is connected to the positive power supply electrode, a gate of the field effect transistor is connected to a second resistor, and the other end of the second resistor is connected to a 6 th pin of the power conversion chip;the 7 pin of the power conversion chip is also connected with a third resistor, an th capacitor and a second capacitor, the anode of the th capacitor is connected with the 7 pin of the power conversion chip, the other 0 end of the second capacitor is connected with the cathode of the 1 th capacitor and is also connected with a 2 th diode, the cathode of the 3 th diode is respectively connected with the other end of the second capacitor, the cathode of the th capacitor and the 5 pin of the power conversion chip, the anode of the th diode is connected with the cathode of the power supply, the other end of the third resistor is connected with a fourth resistor, a fifth resistor and a third capacitor and is also connected with the 2 pin of the power conversion chip, the other end of the fourth resistor is connected with the cathode of the th diode, and the other end of the fifth resistor and the other end of the third capacitor are both connected with the 1 pin of the power conversion chip;the power conversion device comprises a power conversion chip, a field effect transistor, a power conversion chip, a power source, a power conversion chip, a power source and a power supply, wherein a sixth resistor, a seventh resistor, a fourth capacitor and a fifth capacitor are connected to a pin 3 of the power conversion chip, the other end of the sixth resistor is connected with a source electrode of the field effect transistor, the other end of the fourth capacitor is connected with a pin 4 of the power conversion chip, the other end of the seventh resistor is connected with a pin 8 of the power conversion chip, the pin 4 of the power conversion chip is further connected with the sixth capacitor, the pin 8 of the power conversion chip is further connected with a seventh capacitor in parallel, and a pin 4 and a pin 8 of the power conversion chip are further connected with an eighth;the grid of the field effect transistor is further connected with a ninth resistor, the other end of the ninth resistor is connected with the cathode of the diode, the source of the field effect transistor is further connected with a tenth resistor, the other 0 end of the tenth resistor is connected with the cathode of the 1 diode and is further connected with a 2 th inductor, the other 4 end of the 3 inductor is connected with a tenth resistor, an eighth capacitor and a second diode, the other ends of the tenth resistor and the eighth capacitor are both connected with the cathode of the power supply, the anode of the second diode is connected with the other end of the inductor, the cathode of the second diode is connected with a 7 pin of the power supply conversion chip, and the other end of the inductor is a 12V anode output end of the -level voltage reduction circuit.
- 3. The IP latch-inhibiting circuit of claim 2, wherein the secondary voltage-reducing circuit comprises a voltage-reducing chip, a terminal VIN of the voltage-reducing chip is connected with a twelfth resistor and a ninth capacitor and is further connected with a 12V positive output terminal of the -level voltage-reducing circuit, and the other terminal of the twelfth resistor is connected with the positive output terminal of the voltage-reducing chipThe LX end of the voltage reduction chip is connected with a tenth capacitor and a second inductor, the other end of the tenth capacitor is connected with the BST end of the voltage reduction chip, and the other end of the second inductor is the positive electrode output end of the secondary voltage reduction circuit;
the FB end of the voltage reduction chip is also connected with a thirteenth resistor and a fourteenth resistor, the other end of the thirteenth resistor is connected with the other end of the second inductor, the other end of the fourteenth resistor is connected with the negative electrode of the power supply, the GND end of the voltage reduction chip is also connected with the negative electrode of the power supply, the other end of the second inductor is also connected with a tenth capacitor, and the other end of the tenth capacitor is connected with the negative electrode of the power supply. - 4. The IP latch-inhibiting circuit according to claim 3, wherein the thirteenth resistor has a resistance of 30.9K Ω, the fourteenth resistor has a resistance of 5.76K Ω, the second inductor has an inductance of 4.7uH, and the voltage at the positive output terminal of the secondary buck circuit is 5V.
- 5. The IP disable-lock circuit of claim 3, wherein the thirteenth resistor has a resistance of 30.9K Ω, the fourteenth resistor has a resistance of 9.76K Ω, the second inductor has an inductance of 4.7uH, and the voltage at the positive output terminal of the secondary buck circuit is 3.3V.
- 6. The IP disable lock circuit of claim 2, wherein the power conversion chip has a model TD 3845A.
- 7. The IP latch disable circuit of claim 3, wherein the buck chip is model PL 5920.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920984681.8U CN210007622U (en) | 2019-06-27 | 2019-06-27 | IP lock-forbidden circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920984681.8U CN210007622U (en) | 2019-06-27 | 2019-06-27 | IP lock-forbidden circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210007622U true CN210007622U (en) | 2020-01-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920984681.8U Active CN210007622U (en) | 2019-06-27 | 2019-06-27 | IP lock-forbidden circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210007622U (en) |
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2019
- 2019-06-27 CN CN201920984681.8U patent/CN210007622U/en active Active
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