CN209982488U - Wireless transceiver - Google Patents

Abstract

The embodiment of the utility model discloses wireless transceiver, the device includes: a transmitter; the transmitter comprises a transmitter chip, and a transmitting antenna, a crystal frequency modulation circuit and a frequency doubling circuit which are respectively connected with the transmitter chip; the transmitter also comprises an analog signal modulation circuit and/or a digital signal modulation circuit which are connected with the transmitter chip; a receiver; the receiver comprises a receiver chip, and a receiving antenna, a first local oscillation signal generating circuit, a second mixing signal generating circuit, an orthogonal frequency discrimination circuit, an analog signal demodulation circuit and a digital signal demodulation circuit which are connected with the receiver chip. The embodiment of the utility model provides a wireless transceiver can effectively improve the efficiency to the analysis and the debugging of each circuit module.

Description

Wireless transceiver

Technical Field

The embodiment of the utility model provides a relate to wireless communication technology, especially relate to a wireless transceiver.

Background

The radio frequency transceiver system for wireless communication is the front-end part of the communication system and is also the basis for the normal operation of the communication system, and if the transceiver system is not operated smoothly, the communication effect of people can be affected, so that the radio frequency transceiver system has an important effect on the design and optimization of the radio frequency transceiver system.

At present, most of the existing wireless communication systems are integrated systems, which affect the efficiency of analysis and debugging of each circuit module.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides a wireless transceiver can effectively improve the efficiency to the analysis and the debugging of each circuit module.

In a first aspect, an embodiment of the present invention provides a wireless transceiver, including:

a transmitter; the transmitter comprises a transmitter chip, and a transmitting antenna, a crystal frequency modulation circuit and a frequency doubling circuit which are respectively connected with the transmitter chip; the transmitter also comprises an analog signal modulation circuit and/or a digital signal modulation circuit which are connected with the transmitter chip;

a receiver; the receiver comprises a receiver chip, and a receiving antenna, a first local oscillation signal generating circuit, a second mixing signal generating circuit, an orthogonal frequency discrimination circuit, an analog signal demodulation circuit and a digital signal demodulation circuit which are connected with the receiver chip.

Optionally, the crystal frequency modulation circuit includes a first inductor and a first crystal connected in series; a first end of the first inductor is electrically connected with a frequency modulation control first input pin of the transmitter chip, a second end of the first inductor is electrically connected with a first end of the first crystal, and a second end of the first crystal is electrically connected with a frequency modulation control second input pin of the transmitter chip;

the transmitter chip comprises a variable reactor and a radio frequency oscillation circuit, and the crystal frequency modulation circuit is connected with the variable reactor and the radio frequency oscillation circuit through the frequency modulation control first input pin.

Optionally, the analog signal modulation circuit includes a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a first single-pole switch, a second single-pole switch, a first adjustable resistor, and a second adjustable resistor, an input end of the analog signal modulation circuit is electrically connected to a first end of the first capacitor, a second end of the first capacitor is electrically connected to a first end of the first resistor, a second end of the first resistor is connected to a first end of the first adjustable resistor, a second end of the first adjustable resistor is grounded, an adjustable end of the first adjustable resistor is electrically connected to a first end of the second capacitor through the first single-pole switch, a second end of the second capacitor is electrically connected to a first end of the second resistor, a second end of the second resistor is electrically connected to a first end of the third capacitor, and a second end of the third capacitor is electrically connected to a second end of the third capacitor through the second single-pole switch and a modulation signal of the transmitter chip A first input pin is electrically connected, a second end of the third capacitor is electrically connected with a first end of the second adjustable resistor, a second end of the second adjustable resistor is electrically connected with a first end of the third resistor, a second end of the third resistor is grounded, an adjustable end of the second adjustable resistor is electrically connected with a first end of the third resistor, and a first end and a second end of the second resistor are respectively electrically connected with a second input pin of a modulation signal and a third input pin of the modulation signal of the transmitter chip;

the transmitter chip comprises a variable reactor, and the output end of the analog signal modulation circuit is connected with the variable reactor through a first input pin of a modulation signal of the transmitter chip.

Optionally, the digital signal modulation circuit includes a coding chip, a first dial switch, a second dial switch, a third single-pole switch, a third adjustable resistor, a fourth resistor, and a fifth resistor, and the first dial switch is electrically connected to an input pin of the coding chip correspondingly; the second dial switch is correspondingly electrically connected with an input pin of the coding chip, a first end of the third adjustable resistor is electrically connected with a coding signal output pin of the coding chip, a second end of the third adjustable resistor is grounded, and an adjustable end of the third adjustable resistor is electrically connected with a modulation signal first input pin of the transmitter chip through the third single-pole switch; the first end of the fourth resistor is electrically connected with the first grounding pin of the coding chip, the second end of the fourth resistor is grounded, the first end of the fifth resistor is electrically connected with the first end of the fourth resistor, and the second end of the fifth resistor is electrically connected with the second grounding pin of the coding chip.

Optionally, the frequency doubling circuit includes a second inductor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a first adjustable capacitor, a first end of the second inductor is electrically connected to a first end of the fourth capacitor, a second end of the fourth capacitor is electrically connected to a modulation signal output pin of the transmitter chip, a second end of the second inductor is grounded, a second end of the second inductor is electrically connected to a first end of the fifth capacitor, a second end of the fifth capacitor is electrically connected to a signal frequency doubling first input pin of the transmitter chip, a first end of the sixth capacitor is electrically connected to a second end of the fifth capacitor, and a second end of the sixth capacitor is electrically connected to a second end of the first crystal; the first end of the fourth capacitor is electrically connected with the first end of the seventh capacitor, the second end of the seventh capacitor is electrically connected with the first end of the first adjustable capacitor, the second end of the first adjustable capacitor is electrically connected with the first end of the eighth capacitor, the second end of the eighth capacitor is electrically connected with the first end of the second inductor, the second end of the first adjustable capacitor is grounded, the first end of the second inductor is electrically connected with the first end of the ninth capacitor, and the second end of the ninth capacitor is electrically connected with the signal frequency doubling second input pin of the transmitter chip.

Optionally, the first local oscillator signal generating circuit includes a frequency synthesizing chip, a first operational amplifier chip, a second operational amplifier chip, a third dial switch, a fourth dial switch, a second crystal, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a sixth resistor, a seventh resistor, and a fourth single-pole switch, the third dial switch is correspondingly and electrically connected with the input pin of the frequency synthesis chip, the fourth dial switch is correspondingly and electrically connected with the input pin of the frequency synthesis chip, the first end of the second crystal is electrically connected with the signal input pin of the frequency synthesis chip, the second end of the second crystal is electrically connected with the first end of the tenth capacitor, a second end of the tenth capacitor is grounded, a first end of the eleventh capacitor is electrically connected with a grounding pin of the frequency synthesis chip, and a second end of the eleventh capacitor is grounded; the first end of the sixth resistor is electrically connected with the signal input pin of the first operational amplifier chip, the second end of the sixth resistor is electrically connected with the signal output pin of the frequency synthesis chip, the first end of the seventh resistor is electrically connected with the signal amplification output pin of the first operational amplifier chip, the second end of the seventh resistor is electrically connected with the signal amplification input pin of the frequency synthesis chip, the signal amplification output pin of the frequency synthesis chip is electrically connected with the signal input pin of the second operational amplification chip, the first end of the fourth single-pole switch is electrically connected with the signal amplification output pin of the second operational amplification chip, a second end of the fourth single-pole switch is electrically connected with a first end of the twelfth capacitor, and a second end of the twelfth capacitor is electrically connected with a signal input pin of the receiver chip;

the receiver chip comprises a first frequency mixer, and the output end of the first local oscillation signal generating circuit is connected with the first frequency mixer through a first signal input pin of the receiver chip.

Optionally, the second mixed signal generating circuit includes a first ceramic filter, a fifth single-pole switch, a third crystal, a thirteenth capacitor and a fourteenth capacitor, the first end of the first ceramic filter is electrically connected with the signal second input pin of the receiver chip, the second end of the first ceramic filter is electrically connected with the first signal output pin of the receiver chip through the fifth single-pole switch, the first end of the third crystal is electrically connected with the signal second output pin of the receiver chip, a second end of the third crystal is electrically connected with a first end of the fourteenth capacitor, a second end of the thirteenth capacitor is electrically connected with a signal third input pin of the receiver chip, a first end of the fourteenth capacitor is electrically connected to the second end of the thirteenth capacitor, and a second end of the fourteenth capacitor is electrically connected to the first end of the third crystal.

Optionally, the quadrature frequency discriminator circuit includes a first adjustable inductor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, a second adjustable capacitor, and an eighth resistor, the first end of the first adjustable inductor is electrically connected with a signal phase shift input pin of the receiver chip, the second end of the first adjustable inductor is grounded through the fifteenth capacitor, the first end of the sixteenth capacitor is electrically connected with the first end of the first adjustable inductor, a second end of the sixteenth capacitor is electrically connected to the second end of the first adjustable inductor, a first end of the eighth resistor is electrically connected to the first end of the sixteenth capacitor, the second end of the eighth resistor is electrically connected with the second end of the sixteenth capacitor, the first end of the sixteenth capacitor is electrically connected with the first end of the first adjustable inductor, and the second end of the sixteenth capacitor is grounded through the second adjustable capacitor.

Optionally, the receiver further includes a filter, and an output of the quadrature frequency discriminator circuit is connected to the filter.

Optionally, the analog signal modulation circuit and the digital signal modulation circuit are both electrically connected to the transmitter chip through a jumper or a switch.

The embodiment of the utility model provides a wireless transceiver, crystal frequency modulation circuit and frequency doubling circuit on the transmitter carry out frequency modulation and amplification with the modulation signal who gets into the transmitter chip, and through transmitting antenna transmitting signal, the receiving antenna of receiver receives the signal that the transmitter sent, the signal mixing that the signal of receipt and first local oscillator signal production circuit produced obtains mixing signal, mixing signal obtains former modulation signal through second mixing signal production circuit and quadrature frequency discrimination circuit, former modulation signal lets in analog signal demodulation circuit or digital signal demodulation circuit and demodulates, each circuit realizes modular function, can effectively improve the efficiency to the analysis of each circuit module and debugging.

Drawings

Fig. 1 is a schematic structural diagram of a wireless transceiver device according to an embodiment of the present invention;

fig. 2 is a schematic block diagram of a transmitter according to an embodiment of the present invention;

fig. 3 is a schematic block diagram of a receiver according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a crystal frequency modulation circuit according to an embodiment of the present invention;

fig. 5 is a schematic diagram of an analog signal modulation circuit according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a digital signal modulation circuit according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a frequency multiplier circuit according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a first local oscillator signal generating circuit according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a second mixed signal generating circuit according to an embodiment of the present invention;

fig. 10 is a schematic diagram of an orthogonal frequency discrimination circuit according to an embodiment of the present invention

Fig. 11 is a schematic diagram of an analog signal demodulation circuit according to an embodiment of the present invention;

fig. 12 is a schematic diagram of a digital signal demodulation circuit according to an embodiment of the present invention;

fig. 13 is a schematic diagram of a peripheral circuit of a receiver chip according to an embodiment of the present invention;

fig. 14 is a schematic diagram of the internal composition and pin distribution of a transmitter chip according to an embodiment of the present invention;

fig. 15 is a schematic diagram of an internal composition and a pin distribution of a receiver chip according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Based on the problem that the existing wireless communication system is not convenient for analyzing and debugging each circuit module, the embodiment provides a wireless transceiver. Exemplarily, referring to fig. 1, fig. 1 is a schematic structural diagram of a wireless transceiver device according to an embodiment of the present invention, where the wireless transceiver device specifically includes: a transmitter 100 and a receiver 200; wherein the content of the first and second substances,

the transmitter 100 comprises a transmitter chip 110, and a transmitting antenna 120, a crystal frequency modulation circuit 130 and a frequency multiplication circuit 140 which are respectively connected with the transmitter chip 110; the transmitter 100 further includes an analog signal modulation circuit 150 and/or a digital signal modulation circuit 160 connected to the transmitter chip 110;

the receiver 200 includes a receiver chip 210, and a receiving antenna 220, a first local oscillator signal generating circuit 230, a second mixed signal generating circuit 240, a quadrature frequency discrimination circuit 250, an analog signal demodulation circuit 260, and a digital signal demodulation circuit 270 connected to the receiver chip 210.

Specifically, fig. 2 is a schematic block diagram of a transmitter that the embodiment of the present invention provides, transmitter 100 adopts crystal frequency modulation, the range of crystal frequency modulation can be 16M-16.9M, the modulation signal of transmitter 100 can be analog signal or digital signal, the analog signal is generated by analog signal modulation circuit 150, the digital signal is generated by digital signal modulation circuit 160, the modulation signal is amplified through amplitude limiting and passes through crystal frequency modulation, frequency doubling circuit 140 can be tuned on the third harmonic of crystal frequency modulation circuit 130, realize the third harmonic amplification of modulation signal, make frequency deviation and center frequency all enlarge three times, the signal after the frequency doubling is amplified through the two-stage frequency selection again, after matching, radiate by transmitting antenna 120, the transmitting frequency can be 50 MHz. The analog signal modulation circuit 150 and the digital signal modulation circuit 160 are electrically connected to the transmitter chip 110 by jumpers or switches.

Fig. 3 is a schematic block diagram of a receiver according to an embodiment of the present invention, a signal received by a receiving antenna 220 of the receiver 200 is frequency-selected and matched, and then mixed with a first local oscillator signal generated by a first local oscillator signal generating circuit 230 to obtain a first mixed signal, the first mixed signal is filtered by a first intermediate frequency filter and then mixed with a second local oscillator signal to obtain a second mixed signal, i.e. the first mixed signal is filtered by a second mixed signal generating circuit 240 to obtain a second mixed signal, the second mixed signal is filtered by a second intermediate frequency filter and then filtered by a quadrature frequency discrimination circuit 250 to obtain a frequency discrimination output signal, the frequency discrimination output signal is filtered to obtain a recovered original modulation signal, for the original modulation signal of the analog signal, demodulation of the analog signal is performed by an analog signal demodulating circuit 260 to obtain an analog signal in the form of an audio signal, for the original modulation signal of the digital signal, the digital signal is demodulated by a data shaping/digital signal demodulation circuit 270 to obtain a digital signal. The frequency of the first local oscillator signal may be 37MHz-41MHz and the frequency of the second local oscillator signal may be 10.245 MHz.

In the wireless transceiver provided by this embodiment, the crystal frequency modulation circuit and the frequency doubling circuit on the transmitter modulate and amplify the modulated signal entering the transmitter chip, and transmit the signal through the transmitting antenna, the receiving antenna of the receiver receives the signal transmitted by the transmitter, the received signal is mixed with the signal generated by the first local oscillator signal generating circuit to obtain the mixing signal, the mixing signal obtains the original modulated signal through the second mixing signal generating circuit and the orthogonal frequency discrimination circuit, the original modulated signal is introduced into the analog signal demodulation circuit or the digital signal demodulation circuit to be demodulated, each circuit realizes the modularized function, and the analysis and debugging efficiency of each circuit module can be effectively improved

Fig. 4 is a schematic diagram of a crystal frequency modulation circuit according to an embodiment of the present invention, and in addition to the above technical solution, optionally, referring to fig. 4, the crystal frequency modulation circuit 130 includes a first inductor L1 and a first crystal X1 connected in series; a first end of the first inductor L1 is electrically connected to a frequency modulation control first input pin, i.e., pin 1, of the transmitter chip 110, i.e., M1, a second end of the first inductor L1 is electrically connected to a first end of the first crystal X1, and a second end of the first crystal X1 is electrically connected to a frequency modulation control second input pin, i.e., pin 16, of the transmitter chip 110;

the transmitter chip 110 includes a varactor and a radio frequency oscillation circuit, and the crystal frequency modulation circuit 130 is connected to the varactor and the radio frequency oscillation circuit through a frequency modulation control first input pin. The type of the transmitter chip 110 may be MC2833, the frequency of the modulated signal is first modulated by the crystal frequency modulation circuit 130 after entering the transmitter chip 110, the center frequency of the modulated wave is determined by the crystal frequency, the crystal frequency can be finely adjusted by the adjustment inductor, i.e., the first inductor L1, and the frequency of the first crystal X1 may be 16.6 MHz. Specifically, the first crystal X1, the first inductor L1, the capacitors Cl6 and C17 connected to pins 1, 16 and 15 of the MC2833 chip, and the resistors and capacitors connected to pins 2 and 3, together with the variable reactor and the radio frequency oscillation circuit inside the transmitter chip, form a crystal frequency modulation circuit, the center frequency of the frequency modulation wave is determined by the crystal frequency, the modulation signal is sent to the variable reactor inside the chip by pin 3, so that the reactance value of the variable reactor changes with the amplitude of the modulation signal, thereby controlling the change of the oscillation frequency to realize frequency modulation, the frequency modulation signal is output from pin 14 through the internal frequency multiplier, the LC parallel resonance circuit on pin 14 is tuned on the third harmonic of the crystal oscillator to realize the triple frequency multiplication function, and the frequency deviation and the center frequency are both tripled. The frequency-doubled signal is amplified and matched by two stages of frequency selection, and then radiated by an antenna, and the transmitting frequency is about 50 MHz.

Fig. 5 is a schematic diagram of an analog signal modulation circuit according to an embodiment of the present invention, and referring to fig. 5, optionally, based on the above technical solution, the analog signal modulation circuit 150 includes a first resistor R8, a second resistor R2, a third resistor R1, a first capacitor C26, a second capacitor C3, a third capacitor C2, a first single-pole switch JP4, a second single-pole switch JP1, a first adjustable resistor Rw1, and a second adjustable resistor Rw2, an input terminal IN of the analog signal modulation circuit 150 is electrically connected to a first terminal of the first capacitor C26, a second terminal of the first capacitor C26 is electrically connected to a first terminal of the first resistor R8, a second terminal of the first resistor R8 is connected to a first terminal of the first adjustable resistor Rw1, a second terminal of the first adjustable resistor Rw1 is grounded, an adjustable terminal of the first adjustable resistor Rw1 is electrically connected to a second terminal of the second capacitor C3984 through the first single-pole switch JP4, and a second terminal of the first adjustable resistor R2, a second end of the second resistor R2 is electrically connected to a first end of a third capacitor C2, a second end of the third capacitor C2 is electrically connected to a first input pin, i.e., pin 3, of a modulation signal of the transmitter chip 110 through a second single-pole switch JP1, a second end of the third capacitor C2 is electrically connected to a first end of a second adjustable resistor Rw2, a second end of a second adjustable resistor Rw2 is electrically connected to a first end of a third resistor R1, a second end of the third resistor R1 is grounded, an adjustable end of a second adjustable resistor Rw2 is electrically connected to a first end of the third resistor R1, and a first end and a second end of the second resistor R2 are electrically connected to a second input pin, i.e., pin 4, of a modulation signal of the transmitter chip 110 and a third input pin, i.e., pin 5, respectively;

the transmitter chip 110 includes a varactor, and an output terminal of the analog signal modulation circuit is connected to the varactor through a first input pin, i.e., pin 3, of a modulation signal of the transmitter chip 110.

The 2 pin of the transmitter chip 110 is grounded through a capacitor C1, the switch JP5 is connected to a 5V power supply, and the capacitor C27 is electrically connected to the second end of the first adjustable resistor Rw1 through a microphone MIC. The analog modulation signal adopts sine, voice or music signal, the voice or music signal enters the analog signal modulation circuit 150 through the microphone MIC, specifically, the sine signal is supplied by the function generator, the voice or music signal is supplied by the microphone or MP3, and these analog modulation signals are amplified by the on-chip audio limiting amplifier and then sent to the 3 pins. The audio modulation signal is input from an IN end, is added to a pin 5 through a C26, an R8, an Rw1, a JP4 jumper and a capacitor C3, is sent to an on-chip audio limiting amplifier, is output from a pin 4 after being amplified, and is coupled to a pin 3 through a capacitor C2. Rw1 can adjust the amplitude of the audio input signal, adjust Rw2 externally connected with a pin 3, and change the slope of the modulation characteristic. The limiting amplifier consists of an operational amplifier in a chip, an external resistor R2 with 4 and 5 pins and the like, wherein R2 is a feedback resistor, and the voltage gain of the amplifier can be changed by adjusting R2. The two diodes connected to the output end and the input end of the operational amplifier are bidirectional amplitude limiting elements, when the amplitude of the output signal reaches an amplitude limiting level, the two diodes are conducted, the amplitude of the output signal of the operational amplifier is limited to the conducting level of the diodes, and the purpose is to control the amplitude of the modulation voltage applied to the variable reactance end so as to avoid the frequency modulation characteristic from being too nonlinear.

Fig. 6 is a schematic diagram of a digital signal modulation circuit provided in an embodiment of the present invention, on the basis of the above technical solution, optionally, referring to fig. 6, the digital signal modulation circuit 160 includes a coding chip PT2262, a first dial switch SW1, a second dial switch SW2, a third single-pole switch JP6, a third adjustable resistor Rw3, a fourth resistor R16 and a fifth resistor R14, and the first dial switch SW1 is electrically connected to an input pin of the coding chip PT 2262; the second dial switch SW2 is electrically connected with an input pin of the coding chip PT2262 correspondingly, the first end of the third adjustable resistor Rw3 is electrically connected with a coding signal output pin of the coding chip, i.e., a pin 17, the second end of the third adjustable resistor Rw3 is grounded, and the adjustable end of the third adjustable resistor Rw3 is electrically connected with a first input pin of a modulation signal, i.e., a pin 3, of the transmitter chip 110 through a third single-pole switch JP 6; a first end of the fourth resistor R16 is electrically connected to a first ground pin, i.e., pin 14, of the encoder chip PT2262, a second end of the fourth resistor R16 is grounded, a first end of the fifth resistor R14 is electrically connected to a first end of the fourth resistor R16 through a switch RESET, and a second end of the fifth resistor R14 is electrically connected to a second ground pin, i.e., pin 18, of the encoder chip.

Specifically, a resistor R15 is connected between the 15 pin and the 16 pin of the coding chip, and the input ends of the light emitting diodes D1, D2, D3 and D4 are respectively connected with a power supply V through resistors R9, R10, R11 and R12_CCThe output terminals are grounded through resistors R17, R18, R19 and R20, respectively, the port H1 is a transmission port of a digital signal, the digital signal transmitted through the port H1 is a 2FSK (Frequency Shift Keying) signal, i.e., a binary digital Frequency modulation signal, and the pin 7 of the transmitter chip 110 is grounded through resistors R3 and C4. The digital signal adopts square wave or data, and when the square wave is modulated, the square wave signal is supplied by a function generator. If data transmission is required, the data coding signal is generated by the data coding circuit where the coding chip PT2262 is located. The analog modulation signal and the digital modulation signal are both added to the on-chip variable reactor through a pin 3 of the MC2833 chip. When an analog Modulation signal is adopted, the transmitter transmits a common Frequency Modulation signal, namely an FM (Frequency Modulation) signal, and when an encoding signal output by the encoder (or a square wave signal output by the function generator) is added to the Hl port, a 2FSK signal is transmitted.

Fig. 7 is a schematic diagram of a frequency doubling circuit according to an embodiment of the present invention, and referring to fig. 7, optionally, the frequency doubling circuit 140 includes a second inductor L2, a fourth capacitor C15, a fifth capacitor C16, a sixth capacitor C17, a seventh capacitor C22, an eighth capacitor C14, a ninth capacitor C13, and a first adjustable capacitor C23, a first end of the second inductor L2 is electrically connected to a first end of the fourth capacitor C15, a second end of the fourth capacitor C15 is electrically connected to a modulation signal output pin, i.e., a 14 pin, a second end of the second inductor L2 is grounded, a second end of the second inductor is electrically connected to a first end of the fifth capacitor C16, a second end of the fifth capacitor C16 is electrically connected to a first input pin, i.e., a 15 pin, a first end of the sixth capacitor C17 is electrically connected to a second end of the fifth capacitor C16, and a second end of the sixth capacitor C17 is electrically connected to a second end of the frequency doubling crystal X1, i.e., to the 16 pins of the transmitter chip 110; a first end of the fourth capacitor C15 is electrically connected to a first end of the seventh capacitor C22, a second end of the seventh capacitor C22 is electrically connected to a first end of the first adjustable capacitor C23, a second end of the first adjustable capacitor C23 is electrically connected to a first end of the eighth capacitor C14, a second end of the eighth capacitor C14 is electrically connected to a first end of the second inductor L2, a second end of the first adjustable capacitor C23 is grounded, a first end of the second inductor L2 is electrically connected to a first end of the ninth capacitor C13, and a second end of the ninth capacitor C13 is electrically connected to a signal frequency doubling second input pin, i.e., pin 13, of the transmitter chip 110.

Specifically, the circuit shown in fig. 7 further includes a peripheral circuit connected to the transmitter chip 110, where a resistor R7 and a capacitor C11 are connected in parallel, an inductor L3 and a capacitor C10 are connected in parallel and then connected in series with the resistor R6, a capacitor C5 is connected with a capacitor C21 and an adjustable capacitor C24 and is connected with a resistor R5, a capacitor C6 and a capacitor C19, the capacitors C18, C9 and C12 are all connected to the same pin of the transmitter chip 110 and grounded, the capacitor C20 is connected in series with the adjustable capacitor C25, the capacitors C7 and C8 are connected in series and then connected in parallel with the inductor L4, the switches JP2, JP3 and the resistor R4 are connected, and the ports H3, H4 and H5 are signal output ports. The frequency of the modulation signal is amplified by the frequency doubling circuit 140 after the modulation signal is subjected to frequency modulation by the crystal frequency modulation circuit 130, and the frequency doubling circuit 140 can be tuned on the third harmonic of the crystal frequency modulation circuit 130 to realize the triple frequency doubling function, so that the frequency deviation and the central frequency are both enlarged by three times.

Fig. 8 is a schematic diagram of a first local oscillator signal generating circuit according to an embodiment of the present invention, and optionally, referring to fig. 8, the first local oscillator signal generating circuit 230 includes a frequency synthesizing chip M3, a first operational amplifier chip M4, a second operational amplifier chip M5, a third dial switch SW4, a fourth dial switch SW5, a second crystal X2, a tenth capacitor C31, an eleventh capacitor C32, a twelfth capacitor C36, a sixth resistor R21, a seventh resistor R22, and a fourth one-pole switch JP7, the third dial switch SW4 is electrically connected to an input pin of the frequency synthesizing chip M3, the fourth dial switch SW5 is electrically connected to an input pin of the frequency synthesizing chip M3, a first end of the second crystal X2 is electrically connected to a 26 pin serving as a signal input pin of the frequency synthesizing chip M3, a second end of the second crystal X2 is electrically connected to a first end of a tenth capacitor C31, and a second end of the tenth capacitor 31 is grounded, a first end of the eleventh capacitor C32 is electrically connected with a grounding pin, namely a pin 26, of the frequency synthesis chip M3, and a second end of the eleventh capacitor C32 is grounded; a first end of the sixth resistor R21 is electrically connected to a signal input pin, i.e., a 2-pin, of the first operational amplifier chip M4, a second end of the sixth resistor R21 is electrically connected to a signal output pin, i.e., a 7-pin, of the frequency synthesizing chip M3, a first end of the seventh resistor R22 is electrically connected to a signal amplification output pin, i.e., a 3-pin, of the first operational amplifier chip M4, a second end of the seventh resistor R22 is electrically connected to a signal amplification input pin, i.e., an 8-pin, of the frequency synthesizing chip M3, a signal amplification output pin, i.e., a 1-pin, of the frequency synthesizing chip 3 is electrically connected to a signal input pin, i.e., a 2-pin, of the second operational amplifier chip M5, a first end of the fourth single-pole switch JP7 is electrically connected to a signal amplification output pin, i.e., a 5-pin, of the second operational amplifier chip M5, a second end of the fourth single-pole switch JP7 is electrically connected to a; the receiver chip 210 includes a first mixer, and an output terminal of the first local oscillation signal generating circuit is connected to the first mixer through a first signal input pin of the receiver chip.

The first operational amplifier chip M4 is further connected with a 5V power supply, capacitors C58, C59, C61 and C44, resistors R23, R29 and R44, a switch JP8, a resistor Rw4, and a resistor Rw4 are further connected to pins 23 of the M2-23, i.e., the receiver chip 210, through a switch JP8, the second operational amplifier chip M5 is connected with capacitors C62 and C63 and an inductor L5, the frequency synthesis chip M3 is connected with a capacitor C33 and a capacitor C43, resistors R30 and R31, a triode Q2 and a light emitting diode LED2, FRFIN, and M2-20, i.e., the 20 pins of the receiver chip 210, and also is connected with a signal input pin of the receiver chip 210. The first local oscillator signal generating circuit 230 may generate a first local oscillator signal, where a frequency of the first local oscillator signal may be 37MHz to 41MHz, the first local oscillator signal may be filtered by a first intermediate frequency filter and then mixed with a signal received by the receiver to obtain a first mixed frequency signal, and a frequency of the first intermediate frequency filter may be 10.7 MHz. The transmitter chip may be of the type MC3362, and the first local oscillator signal may be generated by a phase-locked frequency synthesizer formed by a VCO in the MC3362 chip. An FM signal or an FSK signal received by a receiving antenna is coupled to one input end of a first frequency mixer of an MC3362 chip through an input frequency-selective matching network, a first local oscillation signal generated by a phase-locked frequency synthesizer is added to the other input end of the first frequency mixer, the first local oscillation frequency is 37-41 MHz, and the first local oscillation signal is generated by the phase-locked frequency synthesizer.

Fig. 9 is a schematic diagram of a second mixed-frequency signal generating circuit according to an embodiment of the present invention, and referring to fig. 9, optionally, the second mixed-frequency signal generating circuit 240 includes a first ceramic filter CERF2, a fifth single-pole switch JP9, a third crystal X3, a thirteenth capacitor C64, and a fourteenth capacitor C65, a first end of the first ceramic filter CERF2 is electrically connected to the second signal input pin, i.e., the 7 pin, of the receiver chip 210, a second end of the first ceramic filter CERF2 is electrically connected to the first signal output pin, i.e., the 5 pin, of the receiver chip 210, i.e., the M2, a first end of the third crystal X3 is electrically connected to the second signal output pin, i.e., the 4 pin, a second end of the third crystal X3 is electrically connected to a first end of the thirteenth capacitor C64, a second end of the thirteenth capacitor C64 is electrically connected to the third signal input pin, i.e., the 3 pin, of the receiver chip 210, a first terminal of the fourteenth capacitor C65 is electrically connected to a second terminal of the thirteenth capacitor C64, and a second terminal of the fourteenth capacitor C65 is electrically connected to a first terminal of the third transistor X3.

The receiver chip 210 is further connected with capacitors C66, C67, C68 and C48, the resistor R32 is electrically connected with the receiver chip through JP2, ports BP2-IN and BP2OUT are input and output ends of signals, respectively, and the first mixing signal is mixed with the second local oscillation signal through the second mixing signal generating circuit 240 to obtain a second mixing signal. Specifically, after buffering and amplifying the signal after the first frequency mixing, the signal is filtered by an external second ceramic filter CERF1 to obtain a first intermediate frequency signal, and then the first intermediate frequency signal is sent back to the second frequency mixer in the chip to be subjected to second frequency mixing with a second local oscillator signal. The frequency of the second ceramic filter CERF1 may be 10.7MHz, the frequency of the second local oscillator signal may be 10.245MHz, which is generated by a crystal oscillator composed of an on-chip oscillation circuit and an external third crystal X3, a C64, a C65 capacitor, etc., and the frequency of the third crystal X3 may be 10.245 MHz.

Fig. 10 is a schematic diagram of a quadrature frequency discrimination circuit according to an embodiment of the present invention, and with reference to fig. 10, optionally, the quadrature frequency discrimination circuit 250 includes a first adjustable inductor L6, a fifteenth capacitor C46, a sixteenth capacitor C37, a seventeenth capacitor C38, a second adjustable capacitor C30, and an eighth resistor R33, a first end of the first adjustable inductor L6 is electrically connected to the signal phase shift input pin of the receiver chip 210, a second end of the first adjustable inductor L6 is grounded through the fifteenth capacitor C46, a first end of the sixteenth capacitor C37 is electrically connected to a first end of the first adjustable inductor L6, a second end of the sixteenth capacitor C37 is electrically connected to a second end of the first adjustable inductor L6, a first end of the eighth resistor R33 is electrically connected to a first end of the sixteenth capacitor C37, a second end of the eighth resistor R33 is electrically connected to a second end of the sixteenth capacitor C37, a second end of the seventeenth capacitor C38 is electrically connected to a first end of the first adjustable inductor L6, a second terminal of the seventeenth capacitor C38 is coupled to ground via the second tunable capacitor C30.

M2-12, i.e., a 12-pin of the receiver chip 210, i.e., a signal phase shift input pin of the receiver chip 210, a resistor R34 is connected with M2-11, i.e., electrically connected with an 11-pin of the receiver chip 210, a capacitor C69 and an adjustable resistor Rw5 are connected with M2-10, i.e., electrically connected with a 10-pin of the receiver chip 210, a resistor R34 is connected with a resistor R35, capacitors C45, C46, a transistor Q1, and a light emitting diode LED, the second mixing signal can be filtered by a second intermediate frequency filter, then phase-shifted and filtered by a quadrature frequency discrimination circuit 250, so as to obtain a recovered original modulation signal, and the frequency of the second intermediate frequency filter can be 455 kHz. Specifically, the output signal after the second mixing is filtered by a first ceramic filter CERF2 to obtain a second intermediate frequency signal, which is then applied to a frequency discriminator after amplitude limiting and amplification. The frequency of the first ceramic filter CERF2 can be 455kHz, the frequency discriminator is a typical 90 ℃ phase shift network plus a quadrature frequency discriminator of a multiplier, and a phase shift network is formed by small capacitors in a chip, a 12-pin external inductor L6, parallel capacitors C37 and C30, a parallel resistor R33 and the like. And after the frequency discrimination output signal is filtered, the restored original modulation signal is obtained at an AUDIO port. For speech or music signals, the low-pass filtered output signal is fed to an audio power amplifier M6(LM386) for further amplification in order to drive the speaker. If the FSK signal is received, the demodulated output signal is sent back to the chip, and the digital signal is regenerated by a decision shaping circuit such as a comparator, then enters a PT2272 chip for decoding and is indicated by a light-emitting diode.

Fig. 11 is a schematic diagram of an analog signal demodulation circuit according to an embodiment of the present invention, and in addition to the above technical solution, optionally, referring to fig. 11, the analog signal demodulation circuit 260 includes an AUDIO power amplifier M6, the M6 is connected to a +5V power supply and capacitors C70, C71, C72, C39, C40, C41, C42, C49, and C50, resistors R36, R37, Rw6, and switches JP10 and JP11, the capacitor C70 is electrically connected to M2-14, that is, electrically connected to 14 pins of the receiver chip 210, the resistor R36 is electrically connected to M2-13, that is, electrically connected to 13 pins of the receiver chip 210, if the original recovered modulation signal is an analog modulation signal, the obtained analog modulation signal is demodulated by the analog signal demodulation circuit 260 through the AUDIO port and output through the speaker SP.

Fig. 12 is a schematic diagram of a digital signal demodulation circuit provided in an embodiment of the present invention, and on the basis of the above technical solution, optionally, referring to fig. 12, the digital signal demodulation circuit 270 includes a decoding chip PT2272 and a power supply V connected to the decoding chip PT2272_CCThe dial switch SW3, the resistors R24, R25, R26, R27, R28, the capacitor C60, and the light emitting diodes D1, D2, D3 and D4, wherein the switch JP12 is connected to the M2-15, that is, to the 15 pin of the receiver chip 210, and the switch JP12 is also connected to the port DATA, and if the obtained modulation signal is a digital modulation signal, the obtained digital modulation signal is demodulated by the digital signal demodulation circuit 270 and output through the DATA port.

Fig. 13 is a schematic diagram of a peripheral circuit of a receiver chip according to an embodiment of the present invention, the receiver chip 210 receives a signal transmitted by the transmitter 100 through the receiving antenna 220 connected to the switch JP13, the received signal enters the receiver chip 210 through the capacitors C47 and C35, the switch JP10 is connected to the capacitors C51, C52, C53 and the switch JP14, the capacitors C54 and C55 are connected to the inductor L9 in parallel, the capacitors C56 and C57 are connected to the inductor L10 in parallel, the inductor L7 and the capacitor C28 are connected to the 5V power supply and connected to the transmitter chip 210 through the switch JP15, the resistors R38 and R39 and the capacitors C73 and C74 are connected to the switch JP15, the adjustable inductor L11 is connected to the capacitor C35, the capacitor C34 is connected to the resistor R40, the resistor R40 is connected to the transistor Q3 and the resistor R3, the capacitor C3 is connected to the pin of the transmitter chip 210, the adjustable capacitor C8672 and the transistor C3, the capacitor C79 and the adjustable capacitor C80 are connected in series with pin 21 of the transmitter chip 210, the resistor R42 is connected with pin 20 of the transmitter chip 210, the resistor R43 is connected with pin 15 of the transmitter chip 210, and the second ceramic filter CERF1 is electrically connected with the resistor R44 and the capacitor C79 through the switch JP 16. The triode Q3 and the resistors R38-R41 form a buffer amplifier for measuring the frequency of the first local oscillation signal and the frequency of the second local oscillation signal.

Fig. 14 is a schematic diagram of the internal components and pin distribution of a transmitter chip provided in an embodiment of the present invention, the type of the transmitter chip may be MC2833, and the internal circuit and the external circuit of the chip jointly implement transmission of signals. Fig. 15 is a schematic diagram of the internal components and pin distribution of a receiver chip provided in an embodiment of the present invention, where the type of the receiver chip may be MC3362, and the internal circuit and the external circuit of the chip jointly implement signal reception.

Transmitter and receiver joint modulation: the transmitter transmits FM/FSK signals from the transmitting antenna and the receiver receives the signals through the receiving antenna.

(1) Square wave transmission

Square wave signals (direct current coupling) with the frequency of lkHz, the amplitude of 2V and the direct current offset of 1V are added into an Hl port of a transmitter by a function generator, and a waveform after demodulation output shaping similar to the waveform of an input modulation signal can be observed at a receiving end.

(2) Data transmission

Binary codes to be transmitted (the indicator light is on when 1) and address codes are set through dial switches SW1 and SW2 electrically connected with a coding chip PT2262, the binary codes and the address codes are applied to an H1 port of the transmitter, and Rw3 is adjusted to enable the amplitude of a digital modulation signal to be 2V. The address code on the decoding chip (which is identical with the address code of the coding chip of the transmitter) is set, and the output signal of the receiver is added to the input end of the decoding chip PT2272, and the on-off change of the indicator light of the decoding chip PT2272 is identical with the on-off change of the indicator light of the coding chip.

(3) Voice or music transmission

The microphone (or MP3) is added with voice or music at the MIC end of the transmitter, the signal demodulated and output by the receiver is added to the input end of the audio power amplifier, and the input music signal can be heard through the trial listening of the sound effect of the loudspeaker SP.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims (10)

1. A wireless transceiver device, comprising:

a transmitter; the transmitter comprises a transmitter chip, and a transmitting antenna, a crystal frequency modulation circuit and a frequency doubling circuit which are respectively connected with the transmitter chip; the transmitter also comprises an analog signal modulation circuit and/or a digital signal modulation circuit which are connected with the transmitter chip;

a receiver; the receiver comprises a receiver chip, and a receiving antenna, a first local oscillation signal generating circuit, a second mixing signal generating circuit, an orthogonal frequency discrimination circuit, an analog signal demodulation circuit and a digital signal demodulation circuit which are connected with the receiver chip.

2. The apparatus of claim 1, wherein the crystal frequency tuning circuit comprises a first inductor and a first crystal connected in series; a first end of the first inductor is electrically connected with a frequency modulation control first input pin of the transmitter chip, a second end of the first inductor is electrically connected with a first end of the first crystal, and a second end of the first crystal is electrically connected with a frequency modulation control second input pin of the transmitter chip;

the transmitter chip comprises a variable reactor and a radio frequency oscillation circuit, and the crystal frequency modulation circuit is connected with the variable reactor and the radio frequency oscillation circuit through the frequency modulation control first input pin.

3. The apparatus of claim 1, wherein the analog signal modulation circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a first single-pole switch, a second single-pole switch, a first adjustable resistor, and a second adjustable resistor, wherein an input terminal of the analog signal modulation circuit is electrically connected to a first terminal of the first capacitor, a second terminal of the first capacitor is electrically connected to a first terminal of the first resistor, a second terminal of the first resistor is connected to a first terminal of the first adjustable resistor, a second terminal of the first adjustable resistor is grounded, an adjustable terminal of the first adjustable resistor is electrically connected to a first terminal of the second capacitor through the first single-pole switch, a second terminal of the second capacitor is electrically connected to a first terminal of the second resistor, and a second terminal of the second resistor is electrically connected to a first terminal of the third capacitor, a second end of the third capacitor is electrically connected with a first modulation signal input pin of the transmitter chip through the second single-pole switch, a second end of the third capacitor is electrically connected with a first end of the second adjustable resistor, a second end of the second adjustable resistor is electrically connected with a first end of the third resistor, a second end of the third resistor is grounded, an adjustable end of the second adjustable resistor is electrically connected with a first end of the third resistor, and a first end and a second end of the second resistor are respectively electrically connected with a second modulation signal input pin and a third modulation signal input pin of the transmitter chip;

the transmitter chip comprises a variable reactor, and the output end of the analog signal modulation circuit is connected with the variable reactor through a first input pin of a modulation signal of the transmitter chip.

4. The device of claim 1, wherein the digital signal modulation circuit comprises a coding chip, a first dial switch, a second dial switch, a third single-pole switch, a third adjustable resistor, a fourth resistor and a fifth resistor, and the first dial switch is electrically connected with an input pin of the coding chip correspondingly; the second dial switch is correspondingly electrically connected with an input pin of the coding chip, a first end of the third adjustable resistor is electrically connected with a coding signal output pin of the coding chip, a second end of the third adjustable resistor is grounded, and an adjustable end of the third adjustable resistor is electrically connected with a modulation signal first input pin of the transmitter chip through the third single-pole switch; the first end of the fourth resistor is electrically connected with the first grounding pin of the coding chip, the second end of the fourth resistor is grounded, the first end of the fifth resistor is electrically connected with the first end of the fourth resistor, and the second end of the fifth resistor is electrically connected with the second grounding pin of the coding chip.

5. The apparatus according to claim 2, wherein the frequency doubling circuit includes a second inductor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a first adjustable capacitor, a first end of the second inductor is electrically connected to a first end of the fourth capacitor, a second end of the fourth capacitor is electrically connected to a modulation signal output pin of the transmitter chip, a second end of the second inductor is grounded, a second end of the second inductor is electrically connected to a first end of the fifth capacitor, a second end of the fifth capacitor is electrically connected to a signal frequency doubling first input pin of the transmitter chip, a first end of the sixth capacitor is electrically connected to a second end of the fifth capacitor, and a second end of the sixth capacitor is electrically connected to a second end of the first crystal; the first end of the fourth capacitor is electrically connected with the first end of the seventh capacitor, the second end of the seventh capacitor is electrically connected with the first end of the first adjustable capacitor, the second end of the first adjustable capacitor is electrically connected with the first end of the eighth capacitor, the second end of the eighth capacitor is electrically connected with the first end of the second inductor, the second end of the first adjustable capacitor is grounded, the first end of the second inductor is electrically connected with the first end of the ninth capacitor, and the second end of the ninth capacitor is electrically connected with the signal frequency doubling second input pin of the transmitter chip.

6. The apparatus according to claim 1, wherein the first local oscillator signal generating circuit comprises a frequency synthesizing chip, a first operational amplifying chip, a second operational amplifying chip, a third toggle actuator, a fourth toggle actuator, a second crystal, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a sixth resistor, a seventh resistor, and a fourth single-pole switch, the third toggle actuator is electrically connected to an input pin of the frequency synthesizing chip, the fourth toggle actuator is electrically connected to an input pin of the frequency synthesizing chip, a first end of the second crystal is electrically connected to a signal input pin of the frequency synthesizing chip, a second end of the second crystal is electrically connected to a first end of the tenth capacitor, a second end of the tenth capacitor is grounded, and a first end of the eleventh capacitor is electrically connected to a ground pin of the frequency synthesizing chip, a second end of the eleventh capacitor is grounded; the first end of the sixth resistor is electrically connected with the signal input pin of the first operational amplifier chip, the second end of the sixth resistor is electrically connected with the signal output pin of the frequency synthesis chip, the first end of the seventh resistor is electrically connected with the signal amplification output pin of the first operational amplifier chip, the second end of the seventh resistor is electrically connected with the signal amplification input pin of the frequency synthesis chip, the signal amplification output pin of the frequency synthesis chip is electrically connected with the signal input pin of the second operational amplification chip, the first end of the fourth single-pole switch is electrically connected with the signal amplification output pin of the second operational amplification chip, a second end of the fourth single-pole switch is electrically connected with a first end of the twelfth capacitor, and a second end of the twelfth capacitor is electrically connected with a signal input pin of the receiver chip;

the receiver chip comprises a first frequency mixer, and the output end of the first local oscillation signal generating circuit is connected with the first frequency mixer through a first signal input pin of the receiver chip.

7. The apparatus of claim 1, wherein the second mixed signal generating circuit comprises a first ceramic filter, a fifth single-pole switch, a third crystal, a thirteenth capacitor, and a fourteenth capacitor, wherein a first end of the first ceramic filter is electrically connected to the signal second input pin of the receiver chip, a second end of the first ceramic filter is electrically connected to the signal first output pin of the receiver chip through the fifth single-pole switch, a first end of the third crystal is electrically connected to the signal second output pin of the receiver chip, a second end of the third crystal is electrically connected to a first end of the thirteenth capacitor, a second end of the thirteenth capacitor is electrically connected to the signal third input pin of the receiver chip, and a first end of the fourteenth capacitor is electrically connected to a second end of the thirteenth capacitor, a second end of the fourteenth capacitor is electrically connected to the first end of the third crystal.

8. The apparatus according to claim 1, wherein the quadrature frequency discrimination circuit comprises a first tunable inductor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, a second tunable capacitor and an eighth resistor, a first end of the first tunable inductor is electrically connected to a signal phase shift input pin of the receiver chip, a second end of the first tunable inductor is grounded via the fifteenth capacitor, a first end of the sixteenth capacitor is electrically connected to a first end of the first tunable inductor, a second end of the sixteenth capacitor is electrically connected to a second end of the first tunable inductor, a first end of the eighth resistor is electrically connected to a first end of the sixteenth capacitor, a second end of the eighth resistor is electrically connected to a second end of the sixteenth capacitor, and a first end of the seventeenth capacitor is electrically connected to a first end of the first tunable inductor, a second terminal of the seventeenth capacitor is grounded through the second adjustable capacitor.

9. The apparatus of claim 1, wherein the receiver further comprises a filter, and wherein the output of the quadrature frequency discrimination circuit is coupled to the filter.

10. The apparatus of claim 1, wherein the analog signal modulation circuit and the digital signal modulation circuit are both electrically connected to the transmitter chip by jumpers or switches.

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