CN209982337U - Three-level Boost circuit and multi-output parallel system - Google Patents
Three-level Boost circuit and multi-output parallel system Download PDFInfo
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- CN209982337U CN209982337U CN201920881389.3U CN201920881389U CN209982337U CN 209982337 U CN209982337 U CN 209982337U CN 201920881389 U CN201920881389 U CN 201920881389U CN 209982337 U CN209982337 U CN 209982337U
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Abstract
The application discloses three-level Boost circuit, multiplexed output parallel system have prevented switching device overvoltage damage. The circuit comprises capacitors Cin, C1-C2, an inductor L1, switches K1-K2, diodes D1-D2 and D11-D13, and an output series capacitor group Co; co has nodes P1 and P2 inside; the cathode of the Cin is connected with a low potential end of Co; the Cin anode is connected with a Co high potential end through one end of L1, two ends of L1, a D1 anode, a D1 cathode, a D2 anode and a D2 cathode in sequence; two ends of L1 are connected with the Cin cathode through one end of K1, two ends of K1, one end of K2 and two ends of K2 in sequence; the D1 cathode is connected with the Cin cathode through a C1 anode, a D11 anode, a D11 cathode and C2 in sequence; the second end of K1 is connected with the anode D11; the cathode of D12 is connected with the anode of D2, and the anode of D12 is connected with the anode of P2; the cathode of D13 is connected with P1, and the anode of D13 is connected with the cathode of D11; k1 and K2 are alternately turned on.
Description
Technical Field
The utility model relates to a power electronic technology field, more specifically say, relate to three level Boost circuit, multiplexed output parallel system.
Background
With the rise of the system voltage of the power electronic converter, the voltage withstanding requirement on the related switching devices is gradually raised, but due to the influence of the semiconductor process performance and the like, the development of the high-cost performance device has certain hysteresis, and the related voltage withstanding requirement cannot be met in a short period, so that how to realize the high-voltage power change by using the device with a lower voltage level and with a lower cost becomes a research hotspot, and the problem can be better solved by the multi-level technology.
Electric power changes including step-up transform, step-down transform, step-up and step-down transform etc, the utility model discloses only be dedicated to and prevent switching device overvoltage damage when stepping up the transform.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a three-level Boost circuit, multiplexed output parallel system to prevent switching device overvoltage damage.
The utility model provides a three-level Boost circuit, includes input capacitance, inductance, first switch, second switch, first freewheel diode, second freewheel diode, flying capacitor, balance capacitor, charging diode, clamping diode, discharge diode and output series capacitance group, wherein:
the output series capacitor group is formed by connecting a plurality of output capacitors in series, a first node and a second node are arranged in the output series capacitor group, the potential of the first node is higher than the potential of the cathode of the charging diode, and the potential difference between the cathode of the second freewheeling diode and the potential of the second node does not exceed the withstand voltage value of the second freewheeling diode;
the input capacitor is connected in parallel to the input power supply; the negative electrode of the input capacitor is connected to the low potential end of the output series capacitor bank; the anode of the input capacitor is connected to the high potential end of the output series capacitor bank through the first end of the inductor, the second end of the inductor, the anode of the first freewheeling diode, the cathode of the first freewheeling diode, the anode of the second freewheeling diode and the cathode of the second freewheeling diode in sequence;
the second end of the inductor is connected to the negative electrode of the input capacitor through the first end of the first switch, the second end of the first switch, the first end of the second switch and the second end of the second switch in sequence;
the cathode of the first fly-wheel diode is connected to the cathode of the input capacitor through one end of the flying capacitor, the other end of the flying capacitor, the anode of the charging diode, the cathode of the charging diode, one end of the balance capacitor and the other end of the balance capacitor in sequence;
a second terminal of the first switch is connected to an anode of the charging diode;
a cathode of the clamping diode is connected to an anode of the second freewheeling diode, and an anode of the clamping diode is connected to the second node;
a cathode of the discharge diode is connected to the first node, and an anode of the discharge diode is connected to a cathode of the charge diode;
the difference between the capacitance values of the flying capacitor and the balance capacitor does not exceed a preset value;
the first switch and the second switch are alternately conducted.
Optionally, the output series capacitor bank includes a first output capacitor, a second output capacitor, a third output capacitor and a fourth output capacitor which are sequentially connected in series between the positive electrode and the negative electrode of the output; the capacitance values of the first output capacitor, the second output capacitor, the third output capacitor and the fourth output capacitor are equal;
the first node is an anode of the first output capacitor or an anode of the second output capacitor, and the second node is an anode of the fourth output capacitor.
The utility model provides a three-level Boost circuit, includes input capacitance, inductance, first switch, second switch, first freewheel diode, second freewheel diode, flying capacitor, balance capacitor, charging diode, clamping diode, discharge diode and output series capacitance group, wherein:
the output series capacitor group is formed by connecting a plurality of output capacitors in series, a first node and a second node are arranged in the output series capacitor group, the potential of the first node is lower than the potential of the anode of the charging diode, and the difference between the potential of the second node and the potential of the anode of the second freewheeling diode does not exceed the withstand voltage value of the second freewheeling diode;
the input capacitor is connected in parallel to the input power supply; the anode of the input capacitor is connected to the high potential end of the output series capacitor bank; the negative electrode of the input capacitor is connected to the low potential end of the output series capacitor bank through the first end of the inductor, the second end of the inductor, the cathode of the first freewheeling diode, the anode of the first freewheeling diode, the cathode of the second freewheeling diode and the anode of the second freewheeling diode in sequence;
the second end of the inductor is connected to the anode of the input capacitor through the first end of the first switch, the second end of the first switch, the first end of the second switch and the second end of the second switch in sequence;
the anode of the first fly-wheel diode is connected to the anode of the input capacitor through one end of the flying capacitor, the other end of the flying capacitor, the cathode of the charging diode, the anode of the charging diode, one end of the balance capacitor and the other end of the balance capacitor in sequence;
a second terminal of the first switch is connected to a cathode of the charging diode;
an anode of the clamping diode is connected to a cathode of the second freewheeling diode; a cathode of the clamping diode is connected to the second node;
an anode of the discharge diode is connected to the first node; the cathode of the discharge diode is connected to the anode of the charge diode;
the difference between the capacitance values of the flying capacitor and the balance capacitor does not exceed a preset value;
the first switch and the second switch are alternately conducted.
Optionally, the output series capacitor bank includes a first output capacitor, a second output capacitor, a third output capacitor and a fourth output capacitor which are sequentially connected in series between the output negative electrode and the output positive electrode; the capacitance values of the first output capacitor, the second output capacitor, the third output capacitor and the fourth output capacitor are equal;
the first node is the cathode of the first output capacitor or the cathode of the second output capacitor;
the second node is a cathode of the fourth output capacitor.
Optionally, the first switch and the second switch are mechanical switches or reverse conducting transistors.
A multiple output parallel system comprising: a plurality of paths of any one of the three-level Boost circuits disclosed above; each three-level Boost circuit has independent input and parallel output.
Optionally, each three-level Boost circuit has an independent output series capacitor bank.
Optionally, the at least two three-level Boost circuits share one output series capacitor bank.
Optionally, the multi-output parallel system is provided with an overvoltage protection device for each output series capacitor bank;
in a three-level Boost circuit where the output series capacitor bank is located, one end of the overvoltage protection device is connected to a junction point of the output series capacitor bank and the second freewheeling diode, and the other end of the overvoltage protection device is connected to the second node; the overvoltage protection device comprises a resistor and a third switch which are connected in series; the third switch operates according to a preset switch control strategy so that the absolute value of the potential difference between the junction point and the second node does not exceed the withstand voltage value of the second freewheeling diode.
Optionally, the third switch is a mechanical switch or a reverse conducting transistor.
It can be seen from the above technical solutions that when the output voltage of the three-level Boost circuit is not established, the voltage division of the flying capacitor C1 and the voltage division of the balance capacitor C2 are equal and increase with the accumulation of the working time, when the voltages of C1 and C2 increase to near Vout/2, the charging diode D11 is turned off in the reverse direction, and the output voltage Vout is established; after the output voltage Vout is established, the C1 changes along with the Vout, the C2 voltage is stabilized near Vout/2, the C2 only plays a voltage supporting role, the current cannot flow into the C2, and when the high voltage is input, the C1 and the C2 are basically equal in voltage division only by ensuring that the capacitance values of the C1 and the C2 are equal, so that overvoltage damage of the first switch K1 and the second switch K2 is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a three-level Boost circuit structure disclosed in an embodiment of the present invention;
FIG. 2 is a timing diagram of K1, K2 in the three-level Boost circuit of FIG. 1;
fig. 3a, 3b, and 3c are schematic diagrams of current trend in three different modes of the circuit shown in fig. 1 when the output voltage is not established;
fig. 4a and 4b are schematic diagrams of current trends of the circuit shown in fig. 1 in two different modes after the output voltage is established;
fig. 5 is a schematic structural diagram of another three-level Boost circuit disclosed in the embodiment of the present invention;
fig. 6 is a schematic structural diagram of another three-level Boost circuit disclosed in the embodiment of the present invention;
fig. 7 is a schematic structural diagram of another three-level Boost circuit disclosed in the embodiment of the present invention;
fig. 8 is a schematic structural diagram of a multiple output parallel system according to an embodiment of the present invention;
fig. 9 is a resistance-capacitance voltage-dividing equivalent circuit formed by a three-level Boost circuit in which a b-path does not work and an input short circuit or a very low voltage is disclosed in the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, the embodiment of the utility model discloses a three-level Boost circuit, including input capacitance Cin, inductance L1, first switch K1, second switch K2, first free wheel diode D1, second free wheel diode D2, flying capacitor C1, balance capacitor C2, charging diode D11, clamp diode D12, discharging diode D13 and output series capacitor group Co (reference numeral "Co" is not shown in fig. 1), wherein:
the output series capacitor group Co is formed by connecting a plurality of output capacitors in series, and has a first node P1 and a second node P2 inside, the potential of the first node P1 is higher than that of the cathode of D11, and the difference between the potentials of the cathode of D2 and the second node P2 does not exceed the withstand voltage value of D2 (fig. 1 only takes the output series capacitor group Co as an example, which includes a first output capacitor Co1, a second output capacitor Co2, a third output capacitor Co3 and a fourth output capacitor Co4 connected in series in sequence between the output positive and negative electrodes, and Co 1-Co 2-Co 3-Co 4, the first node P1 may be set as the positive electrode of Co1, and the second node P2 may be set as the positive electrode of Co 4);
cin is connected in parallel with an input power supply; the cathode of the Cin is connected to the low potential end of the output series capacitor group Co; the positive electrode of Cin is connected to the high-potential end of the output series capacitor group Co through the first end of L1, the second end of L1, the anode of D1, the cathode of D1, the anode of D2 and the cathode of D2 in sequence; outputting the potential difference of the high and low potential ends of the series capacitor group Co as an output voltage Vout;
the second end of the L1 is connected to the cathode of the Cin through the first end of the K1, the second end of the K1, the first end of the K2 and the second end of the K2 in sequence;
the cathode of D1 passes through one end of C1, the other end of C1, the anode of D11, the cathode of D11, one end of C2 and the other end of C2 in sequence and is connected to the cathode of Cin;
the second end of K1 was connected to the anode of D11;
the cathode of D12 was connected to the anode of D2; the anode of D12 is connected to a second node P2;
the cathode of D13 is connected to a first node P1; the anode of D13 was connected to the cathode of D11;
the difference between the capacitance values of C1 and C2 does not exceed a preset value so as to ensure that the capacitance values of C1 and C2 are equal or approximately equal;
k1 and K2 are alternately turned on.
The principle of operation of the circuit shown in fig. 1 is as follows:
k1 and K2 are alternately turned on, the duty ratio is D, and if 0< D <0.5, the timing diagrams of K1 and K2 are shown in fig. 2: in one switching period T, when 0< T < D T, K1 is turned on and K2 is turned off; k1, K2 are turned off when D T < 0.5T and 0.5T + D T < T; when 0.5 × T <0.5 × T + D × T, K2 is turned on and K1 is turned off.
When the circuit shown in fig. 1 is started but the output voltage is not established, the circuit shown in fig. 1 sequentially operates the following modes 1 to 3 in one switching period T:
mode 1: k1 is turned on, K2 is turned off, and the loop current is charged as Cin → L1 → K1 → D11 → C2 → Cin, C2 as shown in fig. 3 a;
mode 2: k1 and K2 are turned off, and the loop current is Cin → L1 → D1 → C1 → D11 → C2 → Cin, C1 and C2 are charged at the same time as shown in fig. 3 b;
modality 3: when K2 is turned on and K1 is turned off, the loop current is charged as shown in fig. 3C, namely Cin → L1 → D1 → C1 → K2 → Cin, and C1.
Since the on-times of K1 and K2 in one switching period T are both D × T, when the circuit shown in fig. 1 is started but the output voltage is not established, the divided voltages of C1 and C2 are equal and increase with the accumulation of the operating time T.
At the moment when the voltages of C1 and C2 rise to Vout/2, in the operation mode 1, C2 is charged, the voltage of C2 rises slightly higher than Vout/2, and the voltage of the cathode of C1 is still Vout/2, so that D11 is cut off reversely. That is, with D11 turned off in the reverse direction, the circuit output voltage shown in fig. 1 builds up.
After the output voltage of the circuit shown in fig. 1 is established, the circuit shown in fig. 1 sequentially operates the following modes 4 to 6 in one switching period T:
modality 4: k1 is turned on, K2 is turned off, and at this time, the loop current is shown in fig. 4a, namely Cin → L1 → K1 → C1 → D2 → Co → Cin, and C1 discharges, and the voltage across the inductor L1 is Vin + Vc1-Vout, where Vin represents the input power voltage, Vc1 represents the C1 voltage, and Vout represents the output voltage, regardless of the forward conduction voltage drop of the diode and the switch and the fluctuation of the capacitor voltage.
Mode 5: when K1 and K2 are turned off, the loop current is Cin → L1 → D1 → D2 → Co → Cin as shown in fig. 4b, and the voltage across the inductor L1 is Vin-Vout when the forward conduction voltage drop of the diode and the switch and the voltage fluctuation of the capacitor are neglected.
Modality 6: when the voltage across the inductor L1 is Vin-Vc1, the loop current is Cin → L1 → D1 → C1 → K2 → Cin, and C1 is charged as shown in fig. 3C, and the voltage across the inductor L1 is Vin-Vc1 regardless of the forward conduction voltage drop of the diode and the switch and the voltage fluctuation of the capacitor.
Based on modes 4 to 6, according to the volt-second balance principle, the method comprises
(Vin+Vc-Vout)*D*T+(Vin-Vout)*(0.5-D)＝0
Is calculated from the aboveA boost conversion is achieved.
In one switching period T, the same conduction time of K1 and K2 is D T, and the average current value of the inductor L1 is fixed, so that Vin + Vc 1-Vout-Vin-Vc 1 is obtained, Vc 1-Vout/2 is obtained through calculation, and it can be seen that the voltage stress of K1 and K2 after the output voltage is established is Vout/2.
From the above description, when the output voltage of the circuit shown in fig. 1 is not established, the divided voltages of C1 and C2 are equal and increase with the accumulation of the working time t, and when the voltages of C1 and C2 increase to near Vout/2, the D11 is turned off reversely, and the output voltage is established; after the output voltage is established, C1 follows Vout to change, and C2 only plays a voltage supporting role, and current can not flow into C2, and when the input high voltage can be ensured only by ensuring that the capacitance values of C1 and C2 are equal, the divided voltages of C1 and C2 are basically equal, so that overvoltage damage of K1 and K2 is avoided, namely damage of K1 or K2 caused by overhigh voltage bearing due to serious uneven divided voltage of C1 and C2 is avoided.
The above analysis is performed only by taking 0< D <0.5 as an example, and the analysis results are the same when 0.5< D <1 (i.e. the voltage of each component in the circuit is not changed), which is not described herein again.
It should be noted that, the circuit shown in fig. 1 can also avoid overvoltage damage of K1 and K2 in a situation where the output voltage fluctuates, and the specific analysis is as follows:
assume that the output voltage Vout initially stabilizes at Vo 1; the output voltage Vout of the next stage is stabilized at Vo2, and Vo1< Vo2, where Vc 1-Vc 2-Vo2/2 and Vc2 represents the voltage of C2; the output voltage Vout of the next stage is stabilized at Vo1 again, at this time, Vc1 is Vo1/2, and C2 is hardly discharged, so that Vc2 is kept as Vo 2/2; the output voltage Vout of the next stage is stabilized at Vo2 again, the Vc1 rises to Vo2/2 along with the output change, and the voltage of C2 rises to Vo2/2+ (Vo2-Vo1/2-Vo2/2)/2 ═ 3 × Vo2/4-Vo 1/4; the output voltage Vout stabilizes at Vo1, … … again in the next stage, and after the above circulation, the voltage of C2 will gradually increase and finally stabilize at Vo2-Vo 1/2. Therefore, the voltage of the C2 can not rise unlimitedly, and the high-voltage-resistant capacitor is selected to ensure that the C2 can not be damaged by overvoltage; although the voltage of the C2 is higher, the voltage of the C1 can timely follow the change of the output voltage Vout/2, and the D11 is in a cut-off state, so that the high voltage of the C2 is not applied to the K2, the voltage stresses of the K1 and the K2 are still Vout/2, and the risk of overvoltage damage is avoided.
Finally, in the circuit shown in fig. 1, the position of the first node P1 is selected to ensure that the D13 realizes the function of providing a discharge path for the C2 only when the circuit is powered down, and the C2 does not discharge through the D13 at other times, so that the cathode connection of the D13 can be connected to the anode of the Co2 instead of the anode of the Co1 in fig. 1, as shown in fig. 5. The position of the second node P2 is selected to ensure that D12 is turned on without causing D2 over-voltage damage. Of course, fig. 1 and 5 only use the four output capacitors Co1 to Co4 as an example of the output series capacitor group Co, but the Co may be constructed by using a plurality of output capacitors with other numbers and other capacitance values instead of fig. 1 and 5 on the premise of ensuring the functions of D13 and D12. Moreover, the working principles of the three-level Boost circuits with different Co structures obtained correspondingly at this time are the same, and are not described in detail here.
Referring to fig. 6, the embodiment of the present invention also discloses another three-level Boost circuit, which is in mirror image relationship with fig. 1, and includes an input capacitor Cin, an inductor L1, a first switch K1, a second switch K2, a first freewheeling diode D1, a second freewheeling diode D2, a flying capacitor C1, a balance capacitor C2, a charging diode D11, a clamping diode D12, a discharging diode D13, and an output series capacitor group Co, wherein:
the output series capacitor group Co is formed by connecting a plurality of output capacitors in series, and has a first node P1 and a second node P2 inside, the potential of the first node P1 is lower than the anode potential of D11, and the difference between the anode potentials of the second nodes P2 and D2 does not exceed the withstand voltage value of D2 (fig. 1 only takes the output series capacitor group Co as an example, which includes a first output capacitor Co1, a second output capacitor Co2, a third output capacitor Co3 and a fourth output capacitor Co4 connected in series in sequence between the output negative and positive electrodes, and if Co1 ═ Co2 ═ Co3 ═ Co4, the first node P1 may be set to be the negative electrode of Co1, and the second node P2 may be set to be the negative electrode of Co 4);
cin is connected in parallel with an input power supply; the anode of Cin is connected to the high potential end of the output series capacitor group Co; the cathode of Cin is connected to the low potential end of the output series capacitor group Co through the first end of L1, the second end of L1, the cathode of D1, the anode of D1, the cathode of D2 and the anode of D2 in sequence;
the second end of L1 is connected to the positive pole of Cin through the first end of K1, the second end of K1, the first end of K2 and the second end of K2 in sequence;
the anode of D1 passes through one end of C1, the other end of C1, the cathode of D11, the anode of D11, one end of C2 and the other end of C2 in sequence to be connected to the anode of Cin;
the second end of K1 was connected to the cathode of D11;
the anode of D12 was connected to the cathode of D2; the cathode of D12 is connected to a second node P2;
the anode of D13 is connected to a first node P1; the cathode of D13 was connected to the anode of D11;
the difference between the capacitance values of C1 and C2 does not exceed a preset value so as to ensure that the capacitance values of C1 and C2 are equal or approximately equal;
k1 and K2 are alternately turned on.
The operation principle of the circuit shown in fig. 6 can be obtained by referring to the same analysis of the circuit shown in fig. 1, and the details are not repeated herein.
In the circuit shown in fig. 6, the position of the first node P1 is selected to ensure that the D13 realizes the function of providing a discharge path for the C2 only when the circuit is powered down, and the C2 does not discharge through the D13 at other times, so the anode connection of the D13 can be connected to the cathode of the Co2 instead of the cathode of the Co1 in fig. 6, as shown in fig. 7. The position of the second node P2 is selected to ensure that D12 is turned on without causing D2 over-voltage damage. Of course, fig. 6 and 7 only use the four output capacitors Co1 to Co4 as an example of the output series capacitor group Co, but the Co may be constructed by a plurality of output capacitors with other numbers and other capacitance values instead on the premise of ensuring the functions of D13 and D12, and is not limited to fig. 6 and 7. Moreover, the working principles of the three-level Boost circuits with different Co structures obtained correspondingly at this time are the same, and are not described in detail here.
Optionally, in any of the embodiments disclosed above, K1 and K2 may be mechanical switches or transistors of reverse conducting type, and are not limited.
Referring to fig. 8, the embodiment of the utility model also discloses a multiple output parallel system, including n way three level Boost circuits, n is more than or equal to 2, and each way three level Boost circuit input is independent, the output is parallelly connected, wherein three level Boost circuits are above-mentioned any kind of three level Boost circuit of disclosing. Fig. 8 is merely exemplary of a three-level Boost circuit including n-way fig. 1.
Optionally, in the multi-output parallel system with any one of the three-level Boost circuits disclosed above, each three-level Boost circuit may have an independent output series capacitor bank Co, or at least two three-level Boost circuits may share one output series capacitor bank Co, and fig. 8 only takes as an example that all three-level Boost circuits share one output series capacitor bank Co.
However, the multi-output parallel system with any one of the three-level Boost circuits disclosed above has a risk of overvoltage at D2 under certain operating conditions. The specific operating conditions are as follows: the circuit comprises a path of three-level Boost circuits which normally work, a path of three-level Boost circuits which do not work and input short circuit or low voltage (a is more than or equal to 1, b is more than or equal to 1, and a + b is less than or equal to n).
Taking fig. 8 as an example, under this specific condition, since the voltage equalizing resistors are respectively connected in parallel to Co 1-Co 4, C1 and C2 in practical application, Co4 in the b-way three-level Boost circuit charges C1 and C2 through D12, and the simplified equivalent circuit is as shown in fig. 9. The voltage of Co4 in the b-path three-level Boost circuit is determined by Co1 voltage-sharing resistors Ro1, Co2 voltage-sharing Ro2, Co3 voltage-sharing Ro3, Co4 voltage-sharing Ro4, C1 voltage-sharing R1 & ltb & gt and C2 voltage-sharing R2 & ltb & gt. In general, Ro1 is Ro2, Ro3, R1 is R2, and in this case, Ro1 is Ro4, and R1 is R2
D2 in the b-way three-level Boost circuit bears the voltage Vout-Vco4 > 3/4Vout, which easily causes D2 damage, so an extra overvoltage protection device is required to ensure that D2 cannot be damaged by overvoltage. Still referring to fig. 8, the overvoltage protection device is connected between the positive pole of Co1 and the positive pole of Co4, and comprises a resistor R0 and a third switch K0 which are connected in series, and the third switch K0 is controlled to be turned on and off so that the voltage value of Vout-Vco4 does not exceed the voltage withstanding value of D2. The on-off control strategy of the third switch K0 may be, for example: when the Vout-Vco4 is larger than P1(P1 is a preset voltage), the third switch K0 is closed, so that the Vco4 is increased, and D2 overvoltage damage of the b-path three-level Boost circuit is avoided; when Vout-Vco4 < P2 (P2 is a preset voltage, P1)>P2) opens the third switch K0, resulting in Vco4 reduction while reducing circuit losses.
The overvoltage protection device applied to fig. 8 is applied to the above-disclosed multi-output parallel system having any one of the three-level Boost circuits in an expanded manner, and the corresponding scheme is as follows: in the three-level Boost circuit with the Co, one end of the overvoltage protection device is connected to the connection point of the Co and D2, the other end of the overvoltage protection device is connected to the second node P2, the overvoltage protection device internally comprises a resistor R0 and a third switch K0 which are connected in series, and the third switch K0 is controlled to be switched on and off so that the absolute value of the potential difference between the connection point and the second node P2 does not exceed the withstand voltage value of D2. The on-off control strategy of the third switch K0 may be, for example, to close the third switch K0 when the absolute value of the potential difference is > P1(P1 is a preset voltage); when the absolute value of the potential difference is < P2 (P2 is a preset voltage, P1> P2), the third switch K0 is turned off.
Optionally, in the multi-output parallel system with any one of the three-level Boost circuits disclosed above, K0 may be a mechanical switch or a reverse conducting transistor, and is not limited.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, identical element in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the embodiments of the invention. Thus, the present embodiments are not intended to be limited to the embodiments shown herein but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (11)
1. The utility model provides a three-level Boost circuit which characterized in that, includes input capacitance, inductance, first switch, second switch, first freewheel diode, second freewheel diode, flying capacitor, balance capacitor, charging diode, clamping diode, discharge diode and output series capacitance group, wherein:
the output series capacitor group is formed by connecting a plurality of output capacitors in series, a first node and a second node are arranged in the output series capacitor group, the potential of the first node is higher than the potential of the cathode of the charging diode, and the potential difference between the cathode of the second freewheeling diode and the potential of the second node does not exceed the withstand voltage value of the second freewheeling diode;
the input capacitor is connected in parallel to the input power supply; the negative electrode of the input capacitor is connected to the low potential end of the output series capacitor bank; the anode of the input capacitor is connected to the high potential end of the output series capacitor bank through the first end of the inductor, the second end of the inductor, the anode of the first freewheeling diode, the cathode of the first freewheeling diode, the anode of the second freewheeling diode and the cathode of the second freewheeling diode in sequence;
the second end of the inductor is connected to the negative electrode of the input capacitor through the first end of the first switch, the second end of the first switch, the first end of the second switch and the second end of the second switch in sequence;
the cathode of the first fly-wheel diode is connected to the cathode of the input capacitor through one end of the flying capacitor, the other end of the flying capacitor, the anode of the charging diode, the cathode of the charging diode, one end of the balance capacitor and the other end of the balance capacitor in sequence;
a second terminal of the first switch is connected to an anode of the charging diode;
a cathode of the clamping diode is connected to an anode of the second freewheeling diode, and an anode of the clamping diode is connected to the second node;
a cathode of the discharge diode is connected to the first node, and an anode of the discharge diode is connected to a cathode of the charge diode;
the difference between the capacitance values of the flying capacitor and the balance capacitor does not exceed a preset value;
the first switch and the second switch are alternately conducted.
2. The three-level Boost circuit of claim 1, wherein the output series capacitor bank comprises a first output capacitor, a second output capacitor, a third output capacitor and a fourth output capacitor serially connected in sequence between an output positive and negative pole; the capacitance values of the first output capacitor, the second output capacitor, the third output capacitor and the fourth output capacitor are equal;
the first node is an anode of the first output capacitor or an anode of the second output capacitor, and the second node is an anode of the fourth output capacitor.
3. A three-level Boost circuit according to claim 1 or 2, wherein the first switch and the second switch are mechanical switches or transistors of the reverse conducting type.
4. The utility model provides a three-level Boost circuit which characterized in that, includes input capacitance, inductance, first switch, second switch, first freewheel diode, second freewheel diode, flying capacitor, balance capacitor, charging diode, clamping diode, discharge diode and output series capacitance group, wherein:
the output series capacitor group is formed by connecting a plurality of output capacitors in series, a first node and a second node are arranged in the output series capacitor group, the potential of the first node is lower than the potential of the anode of the charging diode, and the difference between the potential of the second node and the potential of the anode of the second freewheeling diode does not exceed the withstand voltage value of the second freewheeling diode;
the input capacitor is connected in parallel to the input power supply; the anode of the input capacitor is connected to the high potential end of the output series capacitor bank; the negative electrode of the input capacitor is connected to the low potential end of the output series capacitor bank through the first end of the inductor, the second end of the inductor, the cathode of the first freewheeling diode, the anode of the first freewheeling diode, the cathode of the second freewheeling diode and the anode of the second freewheeling diode in sequence;
the second end of the inductor is connected to the anode of the input capacitor through the first end of the first switch, the second end of the first switch, the first end of the second switch and the second end of the second switch in sequence;
the anode of the first fly-wheel diode is connected to the anode of the input capacitor through one end of the flying capacitor, the other end of the flying capacitor, the cathode of the charging diode, the anode of the charging diode, one end of the balance capacitor and the other end of the balance capacitor in sequence;
a second terminal of the first switch is connected to a cathode of the charging diode;
an anode of the clamping diode is connected to a cathode of the second freewheeling diode; a cathode of the clamping diode is connected to the second node;
an anode of the discharge diode is connected to the first node; the cathode of the discharge diode is connected to the anode of the charge diode;
the difference between the capacitance values of the flying capacitor and the balance capacitor does not exceed a preset value;
the first switch and the second switch are alternately conducted.
5. The three-level Boost circuit of claim 4, wherein the output series capacitor bank comprises a first output capacitor, a second output capacitor, a third output capacitor and a fourth output capacitor serially connected in sequence between an output negative electrode and an output positive electrode; the capacitance values of the first output capacitor, the second output capacitor, the third output capacitor and the fourth output capacitor are equal;
the first node is the cathode of the first output capacitor or the cathode of the second output capacitor;
the second node is a cathode of the fourth output capacitor.
6. A three-level Boost circuit according to claim 4 or 5, wherein the first switch and the second switch are mechanical switches or transistors of reverse conducting type.
7. A multiple output parallel system, comprising: multiplexing a three-level Boost circuit as claimed in any one of claims 1-6; each three-level Boost circuit has independent input and parallel output.
8. The multi-output parallel system according to claim 7, wherein each of the three-level Boost circuits has an independent output series capacitor bank.
9. The multi-output parallel system according to claim 7, wherein at least two three-level Boost circuits share one output series capacitor bank.
10. The multi-output parallel system according to claim 8 or 9, wherein the multi-output parallel system is provided with an overvoltage protection device for each output series capacitor set;
in a three-level Boost circuit where the output series capacitor bank is located, one end of the overvoltage protection device is connected to a junction point of the output series capacitor bank and the second freewheeling diode, and the other end of the overvoltage protection device is connected to the second node; the overvoltage protection device comprises a resistor and a third switch which are connected in series; the third switch operates according to a preset switch control strategy so that the absolute value of the potential difference between the junction point and the second node does not exceed the withstand voltage value of the second freewheeling diode.
11. The multi-output parallel system of claim 10, wherein the third switch is a mechanical switch or a reverse conducting transistor.
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| CN110165888A (en) * | 2019-06-11 | 2019-08-23 | 阳光电源股份有限公司 | Three level Boost circuits, multiple-channel output parallel system |
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