CN209982109U

CN209982109U - Charging signal detection device

Info

Publication number: CN209982109U
Application number: CN201920729266.8U
Authority: CN
Inventors: 王乐永; 雷贵州
Original assignee: Hengda Wisdom Charging Technology Co Ltd
Current assignee: Evergrande Hengchi New Energy Automobile Research Institute Shanghai Co Ltd
Priority date: 2019-05-17
Filing date: 2019-05-17
Publication date: 2020-01-21
Anticipated expiration: 2029-05-17

Abstract

The utility model provides a charging signal detection device, which comprises a charging signal input circuit, at least one power circuit, at least one voltage detection circuit and an analysis circuit; the voltage detection circuit is electrically connected with the charging signal input circuit and the power supply circuit respectively, and is used for receiving and comparing a first voltage output by the charging signal input circuit and a second voltage output by the power supply to obtain a detection voltage; the analysis circuit is electrically connected with the voltage detection circuit and is used for receiving the detection voltage and charging the charging state of the equipment. The charging device can output different detection voltages according to different charging signals, and analyze the charging state according to the detection voltages, so that the charging management intelligence is realized.

Description

Charging signal detection device

Technical Field

The utility model relates to a wisdom field of charging particularly, mainly relates to a charge signal detection device who detects battery charging outfit charge signal.

Background

With the continuous improvement of the scientific and technological level and the living standard of people, more and more people start to buy vehicles to improve the convenience of life and improve the quality of life. However, due to the increasing capacity of vehicles, the emission of vehicle exhaust has a great influence on the ecological environment. In order to improve the increasingly worsened ecological environment, electric automobiles are produced, the electric automobiles drive the vehicles to run through electric power, vehicle tail gas cannot be generated in the running process, and the electric automobiles have great effects on reducing the vehicle tail gas and improving the environmental pollution.

At present, the endurance mileage of the electric automobile is generally low, the electric automobile needs to be charged for vehicles in a community by using a charging pile more frequently so as to meet the endurance requirement, before the electric automobile is charged by the charging pile, a signal needs to be sent to the electric automobile, the electric automobile generates a charging signal according to the signal sent by the charging pile and feeds the charging signal back to the charging pile, and then the charging state of charging equipment, such as charging connection, non-connection and the like, is judged by the charging pile. The signal fed back to the charging pile by the electric automobile is generally a voltage signal, and the voltage signal needs to be detected and the charging state of the charging equipment needs to be analyzed according to the voltage signal, so how to design a detection device capable of conveniently detecting the charging signal of the electric automobile becomes an important subject for the development of the charging industry.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome prior art's defect, provide one kind can be according to the charge signal detection device that charges that detects the signal.

In order to achieve the above object, the utility model adopts the following technical scheme:

a charging signal input circuit, at least one power supply circuit, at least one voltage detection circuit and an analysis circuit,

the voltage detection circuit is electrically connected with the charging signal input circuit and the power supply circuit respectively, and is used for receiving and comparing a first voltage output by the charging signal input circuit and a second voltage output by the power supply to obtain a detection voltage;

the analysis circuit is electrically connected with the voltage detection circuit and is used for receiving the detection voltage and analyzing the charging state of the charging equipment.

The utility model has the advantages that:

the utility model provides a charge signal detection device can compare the voltage of voltage detection circuit and charge signal input circuit input and draw three routes detection voltage, the analysis of rethread analytical circuit thereby detection voltage analysis battery charging outfit's charged state has realized the intellectuality of charging.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention.

Fig. 1 is a block diagram of a charging signal detection device according to a preferred embodiment of the present invention;

fig. 2 is a circuit block diagram of the charging signal detection device shown in fig. 1.

Detailed Description

Hereinafter, various embodiments of the present invention will be described more fully. The present invention is capable of various embodiments and of being modified and varied therein. However, it should be understood that: there is no intention to limit the various embodiments of the invention to the specific embodiments disclosed herein, but on the contrary, the intention is to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the invention.

Hereinafter, the terms "includes" or "may include" used in various embodiments of the present invention indicate the presence of the disclosed functions, operations, or elements, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to refer only to the particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combination of the foregoing.

In various embodiments of the present invention, the expression "a or/and B" includes any or all combinations of the words listed simultaneously, e.g. may include a, may include B or may include both a and B.

Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.

It should be noted that: in the present invention, unless otherwise explicitly specified or defined, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium; there may be communication between the interiors of the two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In the present invention, it should be understood by those skilled in the art that the terms indicating orientation or positional relationship herein are based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.

The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the invention. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.

Referring to fig. 1, fig. 1 is a block diagram illustrating a charging signal detecting device according to a preferred embodiment of the present invention.

Specifically, the charging signal detection device 100 includes a charging signal input circuit 10, a filter circuit 20, at least one power supply circuit 30, at least one voltage detection circuit 40, and an analysis circuit 50, wherein the filter circuit 20 is electrically connected between the charging signal input circuit 10 and the voltage detection circuit 40, and the voltage detection circuit 40 is further electrically connected to the power supply circuit 30 and the analysis circuit 50. In the present embodiment, the charging signal input circuit 10 is used for inputting a charging signal of the charging device, such as an electric vehicle; the filter circuit 20 is configured to filter out an interference signal in the voltage signal transmitted to the voltage detection circuit; the power circuit 30 is configured to input an external voltage, the voltage detection circuit 40 is configured to receive and compare a first voltage input by the charging signal input circuit and a second voltage output by the power supply to obtain a detection voltage, and the analysis circuit 50 is configured to receive the detection voltage and analyze a charging state of the charging device. Further, the charging equipment can be an electric automobile, the power supply equipment can be an alternating current charging pile, and the power supply equipment charges the charging equipment according to the charging state of the charging equipment.

Referring to fig. 2, in the present embodiment, the number of the power circuits 30 is three, and the three power circuits respectively output different voltages to the voltage detection circuit 40; correspondingly, the number of the voltage detection circuits 40 is three, and one of the voltage detection circuits 40 is electrically connected to one of the power circuits 30 to receive the second voltage transmitted by the power circuit 30. In the present embodiment, the second voltages outputted from the three power supply circuits 30 are different, so that the voltage detection circuit 40 detects that the different second voltages are received and compared with the first voltage to detect the charging signal inputted from the charging signal input circuit 10. Further, the power circuit 30 includes a first power circuit 31, a second power circuit 32 and a third power circuit 33, the voltage detection circuit 40 includes a first voltage detection circuit 41, a second voltage detection circuit 42 and a third voltage detection circuit 43, the first power circuit 31 is electrically connected to the first voltage detection circuit 41, the second power circuit 32 is electrically connected to the second voltage detection circuit 42, and the third power circuit 33 is electrically connected to the third voltage detection circuit 43. In this embodiment, the first power circuit 31 is configured to input a second voltage lower than 12V and higher than 9V to the gate of the first mos transistor Q1, the second power circuit 32 is configured to input a second voltage lower than 9V and higher than 6V to the gate of the fourth mos transistor Q4, the third power circuit 33 is configured to input a second voltage lower than 6V to the gate of the seventh mos transistor Q7, and the first voltage detection circuit 41 is configured to receive the first voltage CP _ signal input by the charging signal input circuit 10 and the second voltage input by the first power circuit 31 and output a first detection voltage PWM _12to MCU; the second voltage detection circuit 42 is configured to receive the first voltage CP _ signal input by the charging signal input circuit 10 and the second voltage input by the second power supply circuit 32 and output a second detection voltage PWM _9to MCU; the third voltage detection circuit 43 is configured to receive the first voltage CP _ signal input by the charging signal input circuit 10 and the second voltage input by the third power supply circuit 33, and output a third detection voltage PWM _6 toMCU.

Further, in the present embodiment, the first voltage detection circuit 41, the second voltage detection circuit 42, and the third voltage detection circuit 43 have the same circuit configuration, and each of them has a combined structure including a capacitor, a resistor, and a metal oxide semiconductor tube element. Therefore, the structure and the operation principle of the voltage detection circuit are described below by taking the first voltage detection circuit 41 as an example.

Further, in this embodiment, the first voltage detection circuit 411 includes a comparison sub-circuit 411, a first isolation sub-circuit 412 and a first isolation sub-circuit 413, and the comparison sub-circuit 411, the first isolation sub-circuit 412 and the second isolation sub-circuit 413 are electrically connected in sequence.

Further, the comparison sub-circuit 411 includes a first metal oxide semiconductor transistor Q1 and a first resistor R3. The gate of the first metal oxide semiconductor transistor Q1 is electrically connected to the power circuit, the source of the first metal oxide semiconductor transistor is electrically connected to the charging signal input circuit through the filter circuit 20, and the drain of the first metal oxide semiconductor transistor Q1 is electrically connected to the first resistor R3.

Further, the first metal oxide semiconductor transistor Q1 is configured to compare a first voltage input by the charging signal input circuit with a second voltage input by the power supply circuit and provide a power supply for the first isolation sub-circuit. It is understood that the first mos transistor Q1 receives and compares the first voltage and the second voltage, and when the first voltage is smaller than the second voltage, the first mos transistor Q1 is in a conducting state and allows current to flow from the source of the first mos transistor Q1 to the drain of the first mos transistor Q1 and to the first isolation sub-circuit 412 via the first resistor R3, so as to provide power to the first isolation sub-circuit 412. When the first voltage is not less than the second voltage, the first metal oxide semiconductor transistor Q1 is in an off state, and current is not allowed to pass through the first metal oxide semiconductor transistor Q1. In summary, the first mos transistor Q1 can achieve the functions of comparing the first voltage with the second voltage and transmitting the compared voltage signal to the first isolation sub-circuit 412.

Further, the first isolation sub-circuit 412 includes a second metal oxide semiconductor transistor Q2, a second resistor R4, and a third resistor R5. One end of the second resistor R4 is electrically connected to the charging signal input circuit 10 through the filter circuit 20, and the other end is electrically connected to the gate of the second mos transistor Q2, the source of the second mos transistor Q2 is electrically connected to the drain of the first mos transistor Q1 through the first resistor R3, and the drain of the second mos transistor Q2 is electrically connected to the second isolation sub-circuit 42. One end of the third resistor R5 is electrically connected to the second resistor R4, and the other end is grounded to divide the voltage input to the second mos transistor Q2.

Further, the second mos transistor Q2 is used for isolating negative voltage noise interference and outputting a charging signal to the first isolation sub-circuit 413. It is understood that the second mos transistor Q2 is in a conducting state when the source voltage is greater than the gate voltage and allows current to flow from the source of the second mos transistor Q2 to the drain of the second mos transistor Q2 and output a voltage signal to the first isolation sub-circuit 413. When the source voltage of the second metal oxide semiconductor Q2 is not greater than the gate voltage, the second metal oxide semiconductor Q2 is in a cut-off state, and therefore when the gate of the second metal oxide semiconductor Q2 is a negative voltage, the second metal oxide semiconductor Q2 is in a cut-off state, so that the negative level signal of the charging signal input circuit 10 is converted into a 0 level signal, and external negative voltage noise and interference at the gate of the second metal oxide semiconductor Q2 can be isolated, thereby achieving the functions of isolating negative voltage noise interference and outputting a charging signal to the first isolating sub circuit 413.

The first isolation sub-circuit 413 comprises a third metal oxide semiconductor transistor Q3, a digital signal power supply DVDD, a fourth resistor R6, a fifth resistor R7, a sixth resistor R8, a seventh resistor R9 and a first capacitor C1. The gate of the third metal oxide semiconductor transistor Q3 is electrically connected to the digital signal power supply DVDD, the drain of the third metal oxide semiconductor transistor Q3 is electrically connected to the drain of the second metal oxide semiconductor transistor Q2 through a fourth resistor R6, one end of the sixth resistor R8 and one end of the first capacitor C1 are electrically connected to the fourth resistor R6, and the other end is grounded. Further, the fourth resistor R6 and the sixth resistor R8 are voltage dividing circuits for providing voltage to the third mos transistor Q3, and the first capacitor C1 is used for filtering the charging signal transmitted to the third mos transistor Q3. Further, the fifth resistor R7 is electrically connected to the digital signal power source DVDD and the source of the third mos transistor Q3, and one end of the seventh resistor R9 is electrically connected to the fifth resistor R7, and the other end is grounded. Further, in this embodiment, the resistance of the sixth resistor R8 is much smaller than the resistance of the fifth resistor R7, so that the first voltage detecting module 41 outputs the first detected voltage PWM _12to MCU according to the first voltage and the second voltage.

Further, the third mos transistor Q3 is used for isolating positive voltage noise interference and outputting a charging signal to the analysis circuit 50. It can be understood that when external positive voltage noise and interference exist at the drain of the third metal oxide semiconductor transistor Q3, the drain voltage of the third metal oxide semiconductor transistor Q3 is greater than the digital signal power source DVDD, and the third metal oxide semiconductor transistor Q3 is in an off state, so as to isolate the positive voltage noise interference and output a voltage signal to the analysis circuit 50 when the third metal oxide semiconductor transistor Q3526 is turned on.

Further, the filter circuit 20 includes an eighth resistor R12 and a second capacitor C2, the eighth resistor R12 is electrically connected to the charging signal input circuit 10, the other end of the eighth resistor R is electrically connected to the voltage detection circuit 40, and one end of the second capacitor C2 is electrically connected to the eighth resistor, and the other end of the second capacitor C2 is grounded. The filter circuit 20 is configured to filter an external interference signal in the charging signal input circuit 10, and generate a stable charging signal to the voltage detection circuit 40.

Further, in this embodiment, the components and the circuit structures of the second voltage detection circuit 42 and the third voltage detection circuit 43 are the same as those of the first voltage detection circuit 41, so the circuits of the second voltage detection circuit 42 and the third voltage detection circuit 43 are not repeated here, and the description may refer to the structure of the first voltage detection circuit 41. In addition, since the second voltage detection circuit 42 and the third voltage detection circuit 43 are configured to output different voltage detection signals, values of components, such as a resistor and a capacitor, in the second voltage detection circuit 42 and the third voltage detection circuit 43 may be set according to actual needs so that the voltage detection circuit 40 can output different detection voltages according to the voltage signal input by the charging signal input circuit 10, so that the analysis circuit 50 can analyze the charging signal to obtain the charging state of the charging device.

The operation principle of the charging signal detection apparatus 100 will be described below by taking the first voltage detection circuit 41 as an example. Further, the charging signal input circuit 10 inputs a first voltage CP _ signal to the first voltage detection circuit 41, and the first power circuit 31 is electrically connected to the first voltage detection circuit 41 to input a second voltage to the first voltage detection circuit 41. Further, in the present embodiment, the first voltage CP _ signal includes a 12V level, +12V/-12V pulse width modulation signal, a 9V level, +9V/-12V pulse width modulation signal, a 6V level, and a +6V/-12V pulse width modulation signal.

When the first voltage detection circuit 41 receives the first voltage and the second voltage of 12V level, the first metal oxide semiconductor transistor Q1 and the second metal oxide semiconductor transistor Q2 are in on state, the third metal oxide semiconductor transistor Q3 is in off state, the digital signal power supply DVDD and the fifth resistor R7 form a pull-up circuit, and the first detection voltage PWM _12to MCU is in high level.

When the first voltage detection circuit 41 receives the first voltage and the second voltage of the +12V/-12V pulse width modulation signal, when the first detection voltage is +12V, the first metal oxide semiconductor transistor Q1 and the second metal oxide semiconductor transistor Q2 are in an on state, the third metal oxide semiconductor transistor Q3 is in an off state, the digital signal power supply DVDD and the fifth resistor R7 form a pull-up circuit, and the first detection voltage PWM _12to MCU is at a high level; when the first voltage is-12V, the first metal oxide semiconductor transistor Q1 and the second metal oxide semiconductor transistor Q2 are in an off state, the drain voltage of the third metal oxide semiconductor transistor Q3 is at a low level, the voltages of the gate and the drain are positive, the third metal oxide semiconductor transistor Q3 is in a saturated conduction state, and since the resistance of the sixth resistor R8 is much smaller than the resistance of the fifth resistor R7, the first detection voltage PWM _12to MCU is at a low level, the first detection voltage PWM _12to MCU is a high level/low level pulse width modulation signal.

When the first voltage detection circuit 41 receives a first voltage and a second voltage of 9V level, the first metal oxide semiconductor transistor Q1 is in an off state, the source of the second metal oxide semiconductor transistor Q2 has no power supply loop, at this time, the drain voltage of the third metal oxide semiconductor transistor Q3 is low level, the voltage of the gate and the drain is positive, the third metal oxide semiconductor transistor Q3 is in saturated conduction, and the first detection voltage PWM _12to MCU is low level because the resistance of the sixth resistor R8 is much smaller than the resistance of the fifth resistor R7.

When the first voltage detection circuit 41 receives the first voltage and the second voltage of the +9V/-12V pulse width modulation signal, when the first voltage is 9V, the first metal oxide semiconductor transistor Q1 is in an off state, the source of the second metal oxide semiconductor transistor Q2 has no power supply loop, at this time, the drain voltage of the third metal oxide semiconductor transistor Q3 is low level, the gate and drain voltages are positive, the third metal oxide semiconductor transistor Q3 is in saturated conduction, and since the resistance of the sixth resistor R8 is far smaller than the resistance of the fifth resistor R7, the first detection voltage PWM _12to MCU is low level; when the first voltage is-12V, the first and second metal oxide semiconductor transistors Q1 and Q2 are in an off state, the drain voltage of the third metal oxide semiconductor transistor Q3 is at a low level, the voltages of the gate and the drain are positive, the third metal oxide semiconductor transistor Q3 is in a saturated conduction state, and since the resistance of the sixth resistor R8 is much smaller than the resistance of the fifth resistor R7, the first detection voltage PWM _12to MCU is at a low level.

When the first voltage detection circuit 41 receives a first voltage and a second voltage of 6V level, the first metal oxide semiconductor transistor Q1 is in an off state, the source of the second metal oxide semiconductor transistor Q2 has no power supply loop, at this time, the drain voltage of the third metal oxide semiconductor transistor Q3 is low level, the voltage of the gate and the drain is positive, the third metal oxide semiconductor transistor Q3 is in saturated conduction, and the first detection voltage PWM _12to MCU is low level because the resistance of the sixth resistor R8 is much smaller than the resistance of the fifth resistor R7.

When the first voltage detection circuit 41 receives a first voltage of +6V/-12V pulse width modulation signal and a second voltage lower than 12V, when the first voltage is 6V, the first metal oxide semiconductor transistor Q1 is in an off state, the source of the second metal oxide semiconductor transistor Q2 has no power supply loop, at this time, the drain voltage of the third metal oxide semiconductor transistor Q3 is low level, the voltages of the gate and the drain are positive, the third metal oxide semiconductor transistor Q3 is in saturated conduction, and since the resistance value of the sixth resistor R8 is much smaller than that of the fifth resistor R7, the first detection voltage PWM _12to MCU is low level; when the first voltage is-12V, the first and second metal oxide semiconductor transistors Q1 and Q2 are in an off state, the drain voltage of the third metal oxide semiconductor transistor Q3 is at a low level, the voltages of the gate and the drain are positive, the third metal oxide semiconductor transistor Q3 is in a saturated conduction state, and since the resistance of the sixth resistor R8 is much smaller than the resistance of the fifth resistor R7, the first detection voltage PWM _12to MCU is at a low level.

Further, when the second voltage detection circuit 42 receives the first voltage input by the charging signal input circuit 10 and the second voltage input by the second voltage circuit 32, the second detection voltage PWM _9to MCU can detect different level signals.

Further, when the third voltage detection circuit 43 receives the first voltage input by the charging signal input circuit 10 and the second voltage input by the third voltage circuit 33, the third detection voltage PWM _6to MCU can detect different level signals. It can be understood that the values of the resistors and the capacitors in the three voltage detection circuits 40 can be set according to actual needs, so that the three voltage detection circuits 40 can output different detection voltages according to the voltage signal input by the charging signal input circuit, thereby facilitating the analysis circuit 50 to analyze the charging signal to obtain the charging state of the charging device. Specifically, in this embodiment, the voltage signal input by the charging signal input circuit 10 and the voltage signal detected by the voltage detection circuit 40 may be as shown in the following table:

further, the analysis circuit 50 analyzes the charging status and transmits the charging status to the power supply device, so that the power supply device can charge the charging device according to the charging status.

Further, in the present embodiment, the detection voltage of the voltage detection circuit 40 is at least one of a high level, a low level, and a pulse width modulation signal.

Further, when the detection voltage is three high levels, the charge state is unconnected.

Further, when the detection voltage is three pwm signals and the charging state is three pwm signals, the charging state is unconnected.

Further, when the detection voltage is a low level signal and two high levels, the charging state is a charging connection state.

Further, when the detection voltage is a low level and two pwm signals, the charging state is a charging device ready state.

Further, when the detection voltage is a signal of two low levels and one high level, the charging state is a charging device ready state.

Further, when the detection voltage is two low levels and one pulse width modulation signal, the charging state is a charging state of the charging device.

Further, when the detection voltage is a signal of another level, the charging state is an abnormal state.

In summary, the charging signal detection apparatus of the present embodiment includes three power supply circuits and three voltage detection circuits, and sets different values of the resistor and the capacitor in the voltage detection circuits, so that when the charging signal input circuit inputs a 12V level, the three voltage detection circuits can detect three high level signals; when the charging signal input circuit inputs pulse width modulation signals of +12V and-12V, the three voltage detection circuits detect three pulse width modulation signals; when the charging signal input circuit inputs a 9V level, three voltage detection circuits detect a low level signal and two high level signals; when the charging signal input circuit inputs pulse width modulation signals of +9V and-12V, the three voltage detection circuits detect a low level signal and two pulse width modulation signals; when the charging signal input circuit inputs a 6V level, three voltage detection circuits detect two low level signals and one high level signal; when the charging signal input circuit inputs +6V and-12V pulse width modulation signals, two low level signals and one pulse width modulation signal are detected, so that different level signals can be output when the charging signal is received, the analyzing circuit can analyze the charging state of the charging equipment according to the level signals after receiving the level signals, and therefore the power supply equipment can be charged according to the charging state of the charging equipment, and intelligent charging management is achieved.

The division of the modules in the charging device is merely for illustration, and in other embodiments, the charging device may be divided into different modules as needed to complete all or part of the functions of the charging device. The modules in the charging apparatus may be implemented in whole or in part by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent of a processor in the computer device, and can also be stored in a memory of the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In all examples shown and described herein, any particular value should be construed as merely exemplary, and not as a limitation, and thus other examples of example embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and bus dynamic RAM (RDRAM).

The above-described embodiments are merely illustrative of several embodiments of the present invention, which are described in detail and specific, but not intended to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, other various changes and modifications can be made according to the above-described technical solutions and concepts, and all such changes and modifications should fall within the protection scope of the present invention.

Claims

1. A charging signal detection device is characterized by comprising a charging signal input circuit, at least one power supply circuit, at least one voltage detection circuit and an analysis circuit;

2. The charging signal detection device according to claim 1, wherein the number of the voltage detection circuits is three, the number of the power supply circuits is three, one power supply circuit is electrically connected to one voltage detection circuit, and the analysis circuit is specifically configured to analyze the charging state according to the voltages output by the three voltage detection circuits.

3. The charging signal detection device according to claim 2, wherein one of the voltage detection circuits includes a comparator sub-circuit, a first isolation sub-circuit, and a second isolation sub-circuit, and the comparator sub-circuit, the first isolation sub-circuit, and the second isolation sub-circuit are electrically connected in sequence.

4. The charging signal detection device according to claim 3, wherein the comparator circuit comprises a first metal oxide semiconductor transistor Q1 and a first resistor R3, the gate of the first metal oxide semiconductor transistor Q1 is electrically connected to the power circuit, the source of the first metal oxide semiconductor transistor Q1 is electrically connected to the charging signal input circuit, and the drain of the first metal oxide semiconductor transistor Q1 is electrically connected to the first resistor R4; the first metal oxide semiconductor transistor Q1 is used for comparing a first voltage input by the charging signal input circuit with a second voltage input by the power supply circuit and providing power for the first isolation sub-circuit.

5. The charging signal detection device according to claim 4, wherein the first isolation sub-circuit includes a second metal oxide semiconductor transistor Q2, a second resistor R4 and a third resistor R5, one end of the second resistor R4 is electrically connected to the charging signal input circuit, the other end of the second resistor R4 is electrically connected to the gate of the second metal oxide semiconductor transistor Q2, the source of the second metal oxide semiconductor transistor Q2 is electrically connected to the drain of the first metal oxide semiconductor transistor Q1 through the first resistor R3, the drain of the second metal oxide semiconductor transistor Q2 is electrically connected to the second isolation sub-circuit, one end of the third resistor R5 is electrically connected to the second resistor R4, and the other end of the third resistor R5 is grounded; the second metal oxide semiconductor transistor Q2 is used for isolating negative voltage noise interference and outputting a charging signal to the second isolation sub-circuit.

6. The charging signal detection apparatus as claimed in claim 5, wherein the second isolation sub-circuit comprises a third MOS transistor Q3, a digital signal power supply, a fourth resistor R6, a fifth resistor R7, a sixth resistor R8, a seventh resistor R9 and a first capacitor C1, a gate of the third MOS transistor Q3 is electrically connected to the digital signal power supply, a drain of the third MOS transistor Q3 is electrically connected to a drain of the second MOS transistor Q2 through a fourth resistor R6, the fifth resistor R7 is electrically connected to the digital signal power supply and a source of the third MOS transistor Q3, one end of the sixth resistor R8 and one end of the first capacitor C1 are electrically connected to the fourth resistor R6, the other end of the sixth resistor R3535 is grounded, one end of the seventh resistor R9 is electrically connected to the fifth resistor R7, the other end is grounded; the third mos transistor Q3 is used to isolate the positive voltage noise interference and output a charging signal to the analysis circuit.

7. The charging signal detection device of claim 1, wherein the detection voltage is at least one of a high level, a low level, and a pulse width modulation signal.

8. The charging signal detection device according to claim 7, wherein the charging state is unconnected when the detection voltage is at three high levels.

9. The charging signal detection device of claim 7, wherein the charging state is unconnected when the detection voltage is three PWM signals.

10. The charging signal detection device according to claim 7, wherein the charging state is a charging connection state when the detection voltage is one low level and two high levels.

11. The charging signal detecting apparatus of claim 7, wherein the charging state is a ready state of a charging device when the detection voltage is a low level and two pwm signals.

12. The charging signal detection apparatus according to claim 7, wherein the charging state is a ready state of a charging device when the detection voltage is two low levels and one high level.

13. The charging signal detecting apparatus of claim 7, wherein the charging state is a charging state of a charging device when the detection voltage is two low levels and a pulse width modulation signal.

14. The charging signal detection apparatus according to claim 1, further comprising a filter circuit connected between the charging signal input circuit and the voltage detection circuit; the filter circuit is used for filtering interference signals in the voltage signals transmitted to the voltage detection circuit.

15. The charging signal detecting device of claim 14, wherein the filter circuit comprises an eighth resistor R12 and a second capacitor C2, one end of the eighth resistor R12 is electrically connected to the charging signal input circuit, the other end of the eighth resistor R12 is electrically connected to the voltage detecting circuit, one end of the second capacitor C2 is electrically connected to the eighth resistor R12, and the other end of the second capacitor C2 is grounded.