CN209881785U - Integrated chip - Google Patents
Integrated chip Download PDFInfo
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- CN209881785U CN209881785U CN201921022635.6U CN201921022635U CN209881785U CN 209881785 U CN209881785 U CN 209881785U CN 201921022635 U CN201921022635 U CN 201921022635U CN 209881785 U CN209881785 U CN 209881785U
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Abstract
The utility model relates to an integrated chip. The chip includes: the radio frequency controller is used for receiving a first signal with a specific frequency sent by the management platform or sending a second signal with the specific frequency to the management platform, and sending or receiving data with the baseband controller; the baseband controller is used for decoding the received signals and synthesizing the signals. The processor calls the program in the memory to process the data and sends the data to the main control board, and is also used for receiving the data sent by the main control board and sending the data to the baseband controller. The integrated chip has high integration level, simplifies peripheral circuits, can save the design space of a circuit board, is suitable for product application with smaller space volume, can be directly produced, greatly reduces the design cost of the whole hardware, saves the cost of most external processors, saves the cost of external electronic components related to the processors, and can meet the requirement of automatic equipment.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to an integrated chip.
Background
The processor, the controller, the communication module (such as a 2G communication module, a 4G communication module or a WIFI communication module), an external circuit and a serial port in the traditional intelligent toy machine are independent parts, the integration level is low, a peripheral circuit is complex, the cost is high, the occupied space is large, the universality in use is poor, and the requirement of an actual product cannot be matched.
SUMMERY OF THE UTILITY MODEL
In view of the above, it is necessary to provide an integrated chip in order to solve the above problems.
An integrated chip, comprising: the system comprises a radio frequency controller, a baseband controller, a processor, a memory and an operation memory.
The radio frequency controller is used for receiving a first signal of a specific frequency sent by the management platform or sending a second signal of the specific frequency to the management platform, and is connected with the baseband controller and used for sending the first signal of the specific frequency to the baseband controller or receiving the second signal of the specific frequency sent by the baseband controller.
The baseband controller is used for decoding the received first signal with the specific frequency to obtain first data, and the baseband controller is also used for synthesizing a second signal with the specific frequency.
The processor is respectively connected with the memory, the operating memory and the baseband controller, calls a program in the memory to process the first data to obtain second data and sends the second data to the main control board, is used for receiving third data sent by the main control board and sending the third data to the baseband controller, and is used for controlling the baseband controller to synthesize the third data into a second signal and send the second signal.
The memory is used for storing programs and data.
The operation memory is an operation space for the processor to process the first data.
In one embodiment, the processor performs data transmission with the main control board through a serial port.
In one embodiment, the integrated chip communicates with the management platform through 2G signals.
In one embodiment, the specific frequency is at least one of 850MHz, 900MHz, 1800MHz, and 1900 MHz.
In one embodiment, the integrated chip communicates with the management platform through 4G signals.
In one embodiment, the specific frequency is at least one of 850MHz, 900MHz, 1800MHz, and 2700 MHz.
In one embodiment, the integrated chip communicates with the management platform through WIFI signals.
In one embodiment, the specific frequency is 2.4 GHz.
The integrated chip integrates a radio frequency controller, a baseband controller, a processor, a memory and an operating memory, wherein the radio frequency controller receives a first signal with a specific frequency sent by a management platform or sends a second signal with the specific frequency to the management platform, and the radio frequency controller is connected with the baseband controller and is used for sending the first signal with the specific frequency to the baseband controller or receiving the second signal with the specific frequency sent by the baseband controller; the baseband controller decodes the received first signal with the specific frequency to obtain first data, and is used for synthesizing a second signal with the specific frequency; the processor is respectively connected with the operating memory, the memory and the baseband controller, calls a program in the memory to process first data to obtain second data and sends the second data to the main control board, is used for receiving third data sent by the main control board and sending a third data signal to the baseband controller, and is used for controlling the baseband controller to synthesize the third data into a second signal and send the second signal; the memory is used for storing programs and data; the operation memory is an operation space for the processor to process the first data. The integrated chip has high integration level, simplifies peripheral circuits, can save the design space of a circuit board, is suitable for product application with smaller space volume, can be directly produced, greatly reduces the design cost of the whole hardware, saves the cost of most external processors, saves the cost of external electronic components related to the processors, and can meet the requirement of automatic equipment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, drawings of other embodiments can be obtained according to the drawings without creative efforts.
Fig. 1 is a block diagram of an integrated chip according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating the operation of an integrated chip according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating an operation of the processor to process the first data immediately according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a subsequent processing of the first data by the processor according to an embodiment of the present invention;
fig. 5 is a flowchart illustrating an operation of the processor to process the third data according to an embodiment of the present invention.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, an embodiment of the present invention provides an integrated chip 100, including: an rf controller 102, a baseband controller 104, a processor 106, a memory 108, and an operating memory 110.
The rf controller 102 is configured to receive a first signal with a specific frequency sent by the management platform 112 or send a second signal with the specific frequency to the management platform 112, and the rf controller 102 is connected to the baseband controller 104 and configured to send the first signal with the specific frequency to the baseband controller 104 or receive the second signal with the specific frequency sent by the baseband controller 104.
The baseband controller 104 is configured to decode the received first signal with a specific frequency to obtain first data, and the baseband controller 104 is further configured to synthesize a second signal with a specific frequency.
The processor 106 is connected to the memory 108, the operating memory 110, and the baseband controller 104, the processor 106 calls a program in the memory 108 to process the first data to obtain second data and send the second data to the main control board 114, the processor 106 is configured to receive third data sent by the main control board 114 and send the third data to the baseband controller 104, and the processor 106 is configured to control the baseband controller 104 to synthesize the third data into a second signal and send the second signal.
The memory 108 is used to store programs and data.
The execution memory 110 is an execution space for the processor 106 to process the first data.
As shown in fig. 1-2, the working steps of the integrated chip 100 are:
and S102, the radio frequency controller receives a control signal sent by the management platform.
The rf controller 102 receives a first signal (i.e., a control signal) of a specific frequency transmitted by the management platform 112.
In one embodiment, the integrated chip 100 communicates with the management platform 112 via 2G signals, and in other embodiments, the integrated chip 100 communicates with the management platform 112 via 3G signals.
In one embodiment, the specific frequency is at least one of 850MHz, 900MHz, 1800MHz, 1900 MHz.
In one embodiment, the integrated chip 100 communicates with the management platform 112 via 4G signals.
In one embodiment, the specific frequency is at least one of 850MHz, 900MHz, 1800MHz, 2700 MHz.
In one embodiment, integrated chip 100 communicates with management platform 112 via WIFI signals.
In one embodiment, the specific frequency is 2.4 GHz.
And S104, the radio frequency controller sends the control signal to the baseband controller.
The rf controller 102 transmits the received first signal to the baseband controller 104.
And S106, the baseband controller decodes and transmits the control signal.
The baseband controller 104 first decodes and analyzes the received first signal to obtain first data, and then transmits the first data to the processor 106.
And S108, processing the first data by the processor to obtain second data.
As shown in fig. 3 to fig. 4, after receiving the first data, the processor 106 determines whether to immediately process the first data, and if so, executes the following steps:
s202, the processor transmits the first data to the running memory.
S204, the processor calls the program in the memory into the running memory to process the first data to obtain second data.
The processor 106 calls the corresponding program in the storage 108 into the operating memory, and processes the first data in the operating memory according to the logic design of the program to obtain second data.
If the judgment result is negative, the following steps are executed:
s206, the processor transmits the first data to the memory.
And S208, when the first data needs to be processed, the processor calls the first data and the program in the memory into the running memory to obtain second data.
After the processor 106 calls the first data and the corresponding program in the storage 108 into the operating memory, the first data is processed according to the logic design of the program to obtain second data.
And S110, the processor transmits the second data to the main control board.
The processor 106 transmits the obtained second data to the main control board 114, and controls the operation of the main control board through the second data.
In one embodiment, the processor performs data transmission with the main control board through a serial port.
And S112, the main control board transmits the third data to the processor.
The main control board 114 operates under the control of the second data to obtain third data, and then transmits the third data to the processor 106.
And S114, processing the third data by the processor.
As shown in fig. 5, after the processor 106 receives the third data, the step of processing the third data includes:
and S300, judging whether to send third data.
If yes, executing step S302-step S306; if the determination result is no, step S308 and step S310 are executed first, and then step S304 and step S306 are executed. The method comprises the following specific steps:
if the judgment result is yes, the following steps are executed:
and S302, the processor transmits the third data to the baseband controller.
And S304, the processor controls the baseband controller to synthesize a second signal and sends the second signal to the radio frequency controller.
After the processor 106 controls the baseband controller 104 to synthesize the third data to obtain the second signal, the processor 106 controls the baseband controller 104 to send the synthesized second signal to the rf controller 102.
S306, the radio frequency controller sends the second signal to the management platform.
After receiving the second signal, the rf controller 102 sends the second signal to the management platform 112.
If the judgment result is negative, executing the following steps:
s308, the processor transmits the third data to the memory.
And S310, the processor calls the third data in the memory to the baseband controller.
Then, step S304 and step S306 are executed.
The integrated chip adopts integrated hardware design and combines software embedding, and the integrated chip comprises: serial port, communication, external logic control, algorithm encryption and other functions. The integrated chip integrates a radio frequency controller, a baseband controller, a processor, a memory and an operating memory, wherein the radio frequency controller receives a first signal with a specific frequency sent by a management platform or sends a second signal with the specific frequency to the management platform, and the radio frequency controller is connected with the baseband controller and is used for sending the first signal with the specific frequency to the baseband controller or receiving the second signal with the specific frequency sent by the baseband controller; the baseband controller decodes the received first signal with the specific frequency to obtain first data, and is used for synthesizing a second signal with the specific frequency; the processor is respectively connected with the operating memory, the memory and the baseband controller, calls a program in the memory to process first data to obtain second data and sends the second data to the main control board, is used for receiving third data sent by the main control board and sending a third data signal to the baseband controller, and is used for controlling the baseband controller to synthesize the third data into a second signal and send the second signal; the memory is used for storing programs and data; the operation memory is an operation space for the processor to process the first data. The integrated chip has high integration level, simplifies peripheral circuits, can save the design space of a circuit board, is suitable for product application with smaller space volume, can be directly produced, greatly reduces the design cost of the whole hardware, saves the cost of most external processors, saves the cost of external electronic components related to the processors, and can meet the requirement of automatic equipment.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (8)
1. An integrated chip, comprising: the system comprises a radio frequency controller, a baseband controller, a processor, a memory and an operation memory;
the radio frequency controller is used for receiving a first signal of a specific frequency sent by a management platform or sending a second signal of the specific frequency to the management platform, and is connected with the baseband controller and used for sending the first signal of the specific frequency to the baseband controller or receiving the second signal of the specific frequency sent by the baseband controller;
the baseband controller is configured to decode the received first signal with the specific frequency to obtain first data, and the baseband controller is further configured to synthesize a second signal with the specific frequency;
the processor is respectively connected with the memory, the operating memory and the baseband controller, calls a program in the memory to process the first data to obtain second data and sends the second data to a main control board, is used for receiving third data sent by the main control board and sending the third data to the baseband controller, and is used for controlling the baseband controller to synthesize the third data into the second signal and send the second signal;
the memory is used for storing programs and data;
the running memory is a running space in which the processor processes the first data.
2. The integrated chip of claim 1, wherein the processor performs data transmission with the main control board through a serial port.
3. The integrated chip of claim 1, wherein the integrated chip communicates with the management platform via 2G signals.
4. The integrated chip of claim 3, wherein the specific frequency is at least one of 850MHz, 900MHz, 1800MHz, and 1900 MHz.
5. The integrated chip of claim 1, wherein the integrated chip communicates with the management platform via 4G signals.
6. The IC of claim 5, wherein the specific frequency is at least one of 850MHz, 900MHz, 1800MHz, and 2700 MHz.
7. The integrated chip of claim 1, wherein the integrated chip communicates with the management platform via WIFI signals.
8. The integrated chip of claim 7, wherein the specific frequency is 2.4 GHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921022635.6U CN209881785U (en) | 2019-07-02 | 2019-07-02 | Integrated chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921022635.6U CN209881785U (en) | 2019-07-02 | 2019-07-02 | Integrated chip |
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| CN209881785U true CN209881785U (en) | 2019-12-31 |
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| CN201921022635.6U Active CN209881785U (en) | 2019-07-02 | 2019-07-02 | Integrated chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110492900A (en) * | 2019-07-02 | 2019-11-22 | 广州乐摇摇信息科技有限公司 | Integrated chip and communication module and doll machine and money exchanger |
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2019
- 2019-07-02 CN CN201921022635.6U patent/CN209881785U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110492900A (en) * | 2019-07-02 | 2019-11-22 | 广州乐摇摇信息科技有限公司 | Integrated chip and communication module and doll machine and money exchanger |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 510000 Room 301, building 5, 28 Qinglan street, Xiaoguwei street, Panyu District, Guangzhou City, Guangdong Province Patentee after: Guangdong Xingyun Kaiwu Technology Co.,Ltd. Address before: 511400 b213-10, 22 zhongerheng Road, Xiaoguwei street, Panyu District, Guangzhou City, Guangdong Province Patentee before: GUANGZHOU LEYAOYAO INFORMATION TECHNOLOGY Co.,Ltd. |
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| CP03 | Change of name, title or address |