CN209880110U

CN209880110U - High-speed signal transmission device between multi-media navigation split host and display screen

Info

Publication number: CN209880110U
Application number: CN201920303226.7U
Authority: CN
Inventors: 张志福
Original assignee: DONGGUAN CITY YESSUN ELECTRONIC Co Ltd
Current assignee: DONGGUAN CITY YESSUN ELECTRONIC Co Ltd
Priority date: 2019-03-11
Filing date: 2019-03-11
Publication date: 2019-12-31
Anticipated expiration: 2029-03-11

Abstract

The utility model discloses a high-speed signal transmission device between a multimedia navigation split-type host machine and a display screen, which comprises a host machine end and a display screen end, wherein a serial port two-way controller as a sending end is arranged in the host machine end, a two-way control deserializer as a receiving end is arranged in the display screen end, and the serial port two-way controller and the two-way control deserializer are connected through a set of twisted-pair shielded wires; the host end integrates a plurality of paths of sending end signals into 1 group of differential signals through an FPD-Link III serializer by a serial port bidirectional controller, the differential signals are transmitted to the display screen end through an FPD-Link III protocol, and the display screen end receives the differential signals through a bidirectional control deserializer, restores the differential signals into a plurality of paths of receiving end signals and outputs the signals. The utility model discloses host computer end and display screen end connecting wire reduce to a set of two twisted-pair shielded wire, have reduced the fault rate, have promoted signal transmission's EMC interference killing feature, reduce the influence of the external radiation disturbance of signal to other equipment, simultaneously, reach remote signal transmission's purpose.

Description

High-speed signal transmission device between multi-media navigation split host and display screen

Technical Field

The utility model relates to a signal transmission technique especially relates to a high-speed signal transmission device between multi-media navigation components of a whole that can function independently host computer and display screen.

Background

Generally, 16 paths of signals including video signals, communication signals and display screen backlight control signals need to be transmitted between a host and a display screen of the multimedia navigation split machine, so that 16 wires are required to be connected between the host and the display screen to complete the transmission of the 16 paths of signals, and the 16 wires inevitably have the problem of excessive wire harness terminals, so that the problem of poor contact is easily caused. Meanwhile, the conventional wire has poor anti-electromagnetic interference capability, and has great influence on signal transmission.

SUMMERY OF THE UTILITY MODEL

To the above-mentioned not enough, the utility model aims to provide a high-speed signal transmission device between multi-media navigation components of a whole that can function independently host computer and the display screen, the host computer end is reduced into a set of twisted-pair shielded wire with the connecting wire of display screen end by 16, not only reduced because of the too much fault rate that produces contact failure of pencil terminal, and promoted each signal in transmission process EMC interference-free ability by a wide margin, and simultaneously, reduce the signal and disturb and influence other equipment normal work to external radiation, the high-speed transmission's of each signal distance has been prolonged, reach remote signal transmission's purpose.

The utility model discloses a reach the technical scheme that above-mentioned purpose adopted and be:

a high-speed signal transmission device between a multimedia navigation split-body host and a display screen comprises a host end and a display screen end, and is characterized in that a serial port bidirectional controller serving as a sending end is arranged in the host end, a bidirectional control deserializer serving as a receiving end is arranged in the display screen end, and the serial port bidirectional controller and the bidirectional control deserializer are connected through a set of twisted-pair shielded wires; the host end integrates a plurality of paths of sending end signals into 1 group of differential signals through an FPD-Link III serializer by a serial port bidirectional controller, the differential signals are transmitted to a display screen end through an FPD-Link III protocol, and the display screen end receives the differential signals through a bidirectional control deserializer, restores the differential signals into a plurality of paths of receiving end signals and outputs the signals.

As a further improvement of the utility model, still be provided with an ARM core plate and an MCU microprocessor in the host computer end, wherein, this ARM core plate exports 10 way LVDS high definition video signal and 4 way TP touch communication signals to serial ports bidirectional controller, and this MCU microprocessor exports 2 way display screen control signals in a poor light to serial ports bidirectional controller, constitutes to 10 way LVDS high definition video signal, 4 way TP touch communication signals and 2 way display screen control signals in a poor light of serial ports bidirectional controller output a plurality of ways of sending terminal signal.

As a further improvement of the utility model, the serial port bidirectional controller is a 24-bit color FPD-Link III serial port bidirectional controller, and the model is DS90UB 927Q-Q1.

As a further improvement of the present invention, the 10 channels of LVDS high-definition video signals outputted by the ARM core board are LVDS clock signal +, LVDS clock signal-, LVDS data signal 3+, LVDS data signal 3-, LVDS data signal 2+, LVDS data signal 2-, LVDS data signal 1+, LVDS data signal 1-, LVDS data signal 0+ and LVDS data signal 0-, respectively, wherein the LVDS clock signal + is inputted to the RXCKIN + pin of the serial bidirectional controller, the LVDS clock signal-is inputted to the RXCKIN-pin of the serial bidirectional controller, the LVDS data signal 3+ is inputted to the RXCKIN 3+ pin of the serial bidirectional controller, the LVDS data signal 3-is inputted to the RXCKIN 3-pin of the serial bidirectional controller, the LVDS data signal 2+ is inputted to the RXCIN 2+ pin of the serial bidirectional controller, the LVDS data signal 2-is inputted to the RXCIN 2-pin of the serial bidirectional controller, an LVDS data signal 1+ is input to an RXIN1+ pin of the serial bidirectional controller, an LVDS data signal 1-is input to an RXIN 1-pin of the serial bidirectional controller, an LVDS data signal 0+ is input to an RXIN0+ pin of the serial bidirectional controller, and an LVDS data signal 0-is input to an RXIN 0-pin of the serial bidirectional controller; the ARM core board outputs 4 paths of TP touch communication signals which are respectively TP _ CLK _ clock signals, TP _ DAT _ data signals, TP _ INT _ interrupt signals and TP _ RST _ reset signals, wherein the TP _ CLK _ clock signals are input to an I2C _ SCL pin of the serial port bidirectional controller, the TP _ DAT _ data signals are input to an I2C _ SDA pin of the serial port bidirectional controller, the TP _ INT _ interrupt signals are input to an IIS _ DC/GOIO2 pin of the serial port bidirectional controller, and the TP _ RST _ reset signals are input to a GPIO1 pin of the serial port bidirectional controller; the 2 paths of display screen backlight control signals output by the MCU microprocessor are respectively a display screen backlight PWM pulse control signal output by a PD0(HS)/TIM3_ CC2 pin of the MCU microprocessor and a display screen backlight enabling signal output by a PC4(HS)/TIM1_ CC4 pin of the MCU microprocessor, wherein the display screen backlight PWM pulse control signal is input to an IIS _ DD/GPIO3 pin of the serial port bidirectional controller, and the display screen backlight enabling signal is input to a GPIO0 pin of the serial port bidirectional controller.

As a further improvement of the utility model, still be provided with a high definition LVDS display screen and a TP electric capacity touch-sensitive screen in the display screen end, wherein, bidirectional control deserializer is to high definition LVDS display screen output 10 way LVDS high definition video signal and 2 way display screen control signals in a poor light, and this bidirectional control deserializer is to TP electric capacity touch-sensitive screen output 4 way TP touch communication signals, by 10 way LVDS high definition video signal, 4 way TP touch communication signals and 2 way display screen control signals in a poor light of bidirectional control deserializer output constitute a plurality of ways receiving end signal.

As a further improvement of the utility model, the bidirectional control deserializer is a 24-bit color FPD-Link III bidirectional control deserializer with a model of DS90UB928Q-Q1 chip.

As a further improvement of the present invention, the 10-channel LVDS high definition video signal outputted by the bi-directional control deserializer is LVDS clock signal outputted by TXCKOUT + pin of the bi-directional control deserializer +, LVDS clock signal outputted by TXCKOUT-pin of the bi-directional control deserializer, LVDS data signal 3 outputted by TXCKOUT 3+ pin of the bi-directional control deserializer, LVDS data signal 3 outputted by TXCKOUT 3-pin of the bi-directional control deserializer, LVDS data signal 2 outputted by TXCUT 2+ pin of the bi-directional control deserializer, LVDS data signal 2 outputted by TXCUT 2-pin of the bi-directional control deserializer, LVDS data signal 1+ outputted by TXCUT 1+ pin of the bi-directional control deserializer, LVDS data signal 1-outputted by TXCKOUT 1-pin of the bi-directional control deserializer, LVDS data signal 0+ output by TXOUT0+ pin of the bi-directional control deserializer and LVDS data signal 0-output by TXOUT 0-pin of the bi-directional control deserializer; the 4 paths of TP touch communication signals output by the bidirectional control deserializer are a TP _ CLK _ clock signal output by an SCL pin of the bidirectional control deserializer, a TP _ DAT _ data signal output by an SDA pin of the bidirectional control deserializer, a TP _ INT _ interrupt signal output by an I2S _ DC/GPI02 pin of the bidirectional control deserializer and a TP _ RST _ reset signal output by a GPIO1 pin of the bidirectional control deserializer respectively; the 2 paths of display screen backlight control signals output by the bidirectional control deserializer are a display screen backlight PWM pulse control signal output by an I2S _ DD/GPI03 pin of the bidirectional control deserializer and a display screen backlight enabling signal output by a GPIO0 pin of the bidirectional control deserializer respectively.

As the utility model discloses a further improvement, by the output of two-way control deserializer 2 way display screen control signal in a poor light is inputed to high definition LVDS display screen through a display screen drive circuit in a poor light.

As a further improvement, be connected with a display screen socket on the serial ports two-way controller be connected with a host computer socket on the two-way control deserializer, a set of two twisted-pair shielded wire is connected between display screen socket and host computer socket.

The utility model has the advantages that: the serial port bidirectional controller serving as a sending end is additionally arranged in a host end, the bidirectional control deserializer serving as a receiving end is additionally arranged in a display screen end, the serial port bidirectional controller and the bidirectional control deserializer are connected through only one set of twisted pair shielded wires, the serial port bidirectional controller integrates 16 paths of signal codes into 1 set of low-voltage differential signals, the 1 set of low-voltage differential signals are transmitted to the display screen end through an FPD-Link III protocol, and the bidirectional control deserializer decodes the 1 set of low-voltage differential signals into 16 paths of signals and outputs the 16 paths of signals to a high-definition LVDS display screen and a TP capacitive touch screen. Therefore, 16 paths of signals are integrated into a group of low-voltage differential signals and then transmitted by an FPD-Link III protocol, so that connecting lines between a host end and a display screen end are reduced into a group of twisted-pair shielded wires from 16 lines, the fault rate of poor contact caused by excessive wiring harness terminals is reduced, the anti-interference capacity of EMC (electro magnetic compatibility) of each signal (particularly LVDS high-definition video signals) in the transmission process is greatly improved, meanwhile, the influence of external radiation disturbance of the signal on normal work of other equipment is reduced, the high-speed transmission distance of each signal (particularly LVDS high-definition video signals) is prolonged, and the purpose of long-distance signal transmission is achieved.

The above is an overview of the technical solution of the present invention, and the present invention is further explained with reference to the accompanying drawings and the detailed description.

Drawings

FIG. 1 is a block diagram of the overall structure of the present invention;

FIG. 2 is a schematic diagram of a serial port bidirectional controller according to the present invention;

FIG. 3 is a schematic diagram of an ARM core board according to the present invention;

FIG. 4 is a schematic diagram of the MCU microprocessor of the present invention;

FIG. 5 is a schematic diagram of a two-way control deserializer of the present invention;

fig. 6 is a schematic diagram of a high definition LVDS display screen according to the present invention;

fig. 7 is a schematic diagram of a TP capacitive touch screen of the present invention;

fig. 8 is a schematic diagram of the backlight driving circuit of the display panel of the present invention.

Detailed Description

To further illustrate the technical means and effects of the present invention adopted to achieve the intended purpose, the following detailed description of the embodiments of the present invention is provided in conjunction with the accompanying drawings and preferred embodiments.

Referring to fig. 1, an embodiment of the present invention provides a high-speed signal transmission device between a main frame and a display screen of a multimedia navigation split main frame, which includes a main frame end and a display screen end, wherein a serial bidirectional controller is disposed in the main frame end as a transmitting end, a bidirectional control deserializer is disposed in the display screen end as a receiving end, and the serial bidirectional controller and the bidirectional control deserializer are connected by a set of twisted-pair shielded wires; the host end integrates a plurality of paths of sending end signals into 1 group of differential signals through an FPD-Link III serializer by a serial port bidirectional controller, the differential signals are transmitted to a display screen end through an FPD-Link III protocol, and the display screen end receives the differential signals through a bidirectional control deserializer, restores the differential signals into a plurality of paths of receiving end signals and outputs the signals.

In this embodiment, specifically, an ARM core board and an MCU microprocessor are further disposed in the host, wherein the ARM core board outputs 10 channels of LVDS high-definition video signals and 4 channels of TP touch communication signals to the serial bidirectional controller, the MCU microprocessor outputs 2 channels of display screen backlight control signals to the serial bidirectional controller, and the 10 channels of LVDS high-definition video signals, 4 channels of TP touch communication signals and 2 channels of display screen backlight control signals output to the serial bidirectional controller constitute the plurality of sending end signals.

In this embodiment, as shown in fig. 2, the serial bidirectional controller is a 24-bit color FPD-Link iii serial bidirectional controller, and the model is DS90UB 927Q-Q1.

How the 10-channel LVDS high-definition video signal, the 4-channel TP touch communication signal and the 2-channel display screen backlight control signal are connected and input to the serial port bidirectional controller will be described in detail with reference to fig. 2 to 4. As shown in fig. 3, the 10 channels of LVDS high-definition video signals output by the ARM core board in this embodiment are LVDS clock signal +, LVDS clock signal-, LVDS data signal 3+, LVDS data signal 3-, LVDS data signal 2+, LVDS data signal 2-, LVDS data signal 1+, LVDS data signal 1-, LVDS data signal 0+ and LVDS data signal 0-, respectively, wherein as shown in fig. 2, the LVDS clock signal + is input to the RXCLKIN + pin of the serial bidirectional controller, the LVDS clock signal-is input to the RXCLKIN-pin of the serial bidirectional controller, the LVDS data signal 3+ is input to the RXIN3+ pin of the serial bidirectional controller, the LVDS data signal 3-is input to the RXIN 3-pin of the serial bidirectional controller, the rxdata signal 2+ is input to the RXIN2+ pin of the serial bidirectional controller, the LVDS data signal 2-is input to the RXIN 2-pin of the serial bidirectional controller, LVDS data signals 1+ are input to an RXIN1+ pin of the serial bidirectional controller, LVDS data signals 1-are input to an RXIN 1-pin of the serial bidirectional controller, LVDS data signals 0+ are input to an RXIN0+ pin of the serial bidirectional controller, and LVDS data signals 0-are input to an RXIN 0-pin of the serial bidirectional controller.

Meanwhile, as shown in fig. 3, the 4 paths of TP touch communication signals output by the ARM core board are TP _ CLK _ clock signal, TP _ DAT _ data signal, TP _ INT _ interrupt signal and TP _ RST _ reset signal, respectively, where as shown in fig. 2, the TP _ CLK _ clock signal is input to an I2C _ SCL pin of the serial bidirectional controller, the TP _ DAT _ data signal is input to an I2C _ SDA pin of the serial bidirectional controller, the TP _ INT _ interrupt signal is input to an IIS _ DC/GOIO2 pin of the serial bidirectional controller, and the TP _ RST _ reset signal is input to a GPIO1 pin of the serial bidirectional controller.

Meanwhile, as shown in fig. 4, the 2 channels of display screen backlight control signals output by the MCU microprocessor are a display screen backlight PWM pulse control signal output by a PD0(HS)/TIM3_ CC2 pin of the MCU microprocessor and a display screen backlight enable signal output by a PC4(HS)/TIM1_ CC4 pin of the MCU microprocessor, respectively, where as shown in fig. 2, the display screen backlight PWM pulse control signal is input to an IIS _ DD/GPIO3 pin of the serial bidirectional controller, and the display screen backlight enable signal is input to a GPIO0 pin of the serial bidirectional controller.

In this embodiment, specifically, as shown in fig. 1, a high-definition LVDS display screen and a TP capacitive touch screen are further disposed in the display screen end, wherein the bidirectional control deserializer outputs 10 LVDS high-definition video signals and 2 display screen backlight control signals to the high-definition LVDS display screen, and outputs 4 TP touch communication signals to the TP capacitive touch screen, and the plurality of receiving end signals are composed of the 10 LVDS high-definition video signals, the 4 TP touch communication signals and the 2 display screen backlight control signals output by the bidirectional control deserializer.

In this embodiment, as shown in FIG. 5, the bi-directional control deserializer is a 24-bit color FPD-Link III bi-directional control deserializer, and is a DS90UB928Q-Q1 chip.

With reference to fig. 5 to fig. 7, how to output and access the 10-channel LVDS high-definition video signal, the 4-channel TP touch communication signal, and the 2-channel display screen backlight control signal to the high-definition LVDS display screen and the TP capacitive touch screen will be described in detail. As shown in FIG. 5, the 10 LVDS high-definition video signals output by the DCD deserializer according to the embodiment are LVDS clock signal output by a TXCKOUT + pin of the DCD deserializer +, LVDS clock signal output by a TXCKOUT-pin of the DCD deserializer, LVDS data signal 3 output by a TXCKOUT 3+ pin of the DCD deserializer, LVDS data signal 3 output by a TXOUT 3-pin of the DCD deserializer, LVDS data signal 2 output by a TXOUT2+ pin of the DCD deserializer, LVDS data signal 2 output by a TXOUT 2-pin of the DCD deserializer, LVDS data signal 1 output by an OUT TX 1+ pin of the DCD deserializer, LVDS data signal 1 output by an OUT TX3638-pin of the DCD deserializer, LVDS data signal 1-, and LVDS data signal output by a TXCKOUT 1-pin of the DCD deserializer, LVDS data signal 0+ output by TXOUT0+ pin of the bilateral control deserializer, and LVDS data signal 0-output by TXOUT 0-pin of the bilateral control deserializer. Meanwhile, with reference to fig. 6, 10 channels of LVDS high-definition video signals output by the bidirectional control deserializer are sequentially accessed to the high-definition LVDS display screen.

Meanwhile, as shown in fig. 5, the 4 paths of TP touch communication signals output by the bi-directional control deserializer are a TP _ CLK _ clock signal output by an SCL pin of the bi-directional control deserializer, a TP _ DAT _ data signal output by an SDA pin of the bi-directional control deserializer, a TP _ INT _ interrupt signal output by an I2S _ DC/GPI02 pin of the bi-directional control deserializer, and a TP _ RST _ reset signal output by a GPIO1 pin of the bi-directional control deserializer, respectively. Meanwhile, with reference to fig. 7, 4 paths of TP touch communication signals output by the bidirectional control deserializer are sequentially accessed to the TP capacitive touch screen.

Meanwhile, as shown in fig. 5, the 2-channel display screen backlight control signals output by the bidirectional control deserializer are the display screen backlight PWM pulse control signal output by the pin I2S _ DD/GPI03 of the bidirectional control deserializer and the display screen backlight enable signal output by the pin GPIO0 of the bidirectional control deserializer, respectively. Meanwhile, as shown in fig. 1, in the present embodiment, the 2-channel display screen backlight control signal output by the bidirectional control deserializer is input to the high-definition LVDS display screen through a display screen backlight driving circuit. Specifically, as shown in fig. 8, 2 paths of display screen backlight control signals output by the bidirectional control deserializer are sequentially accessed into the display screen backlight driving circuit and finally accessed into the high-definition LVDS display screen.

In this embodiment, as shown in fig. 2 and 5, a display screen socket is connected to the serial bidirectional controller, a host socket is connected to the bidirectional control deserializer, and the set of twisted pair shielded wires is connected between the display screen socket and the host socket to connect the host end and the display screen end.

Therefore, the working principle of the embodiment is as follows:

the host end adopts a DS90UB927Q-Q124 bit color FPD-Link III serial port bidirectional controller chip to integrate 10 paths of LVDS high-definition video signals output by an ARM core board, 4 paths of TP touch communication signals and 2 paths of display screen backlight control signals output by an MCU into 16 paths of signals, the signals are coded and integrated into 1 group of differential signals through an FPD-Link III serializer, and the signals are transmitted to a display screen end through an FPD-Link III protocol. The display screen end adopts a DS90UB928Q-Q124 bit color FPD-Link III bidirectional control deserializer to receive 1 group of differential signals after the host end is coded and integrated, and then the differential signals are decoded and restored into 10 paths of LVDS high-definition video signals, 16 paths of signals including 4 paths of TP touch communication signals and 2 paths of display screen backlight control signals, the 10 paths of LVDS high-definition video signals are output to a high-definition LVDS display screen for display, the 4 paths of TP touch communication signals are output to a TP capacitance touch screen for communication, and the 2 paths of display screen backlight control signals are output to display screen backlight control.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the technical scope of the present invention, so that other structures obtained by adopting the same or similar technical features as the above embodiments of the present invention are all within the protection scope of the present invention.

Claims

1. A high-speed signal transmission device between a multimedia navigation split-body host and a display screen comprises a host end and a display screen end, and is characterized in that a serial port bidirectional controller serving as a sending end is arranged in the host end, a bidirectional control deserializer serving as a receiving end is arranged in the display screen end, and the serial port bidirectional controller and the bidirectional control deserializer are connected through a set of twisted-pair shielded wires; the host end integrates a plurality of paths of sending end signals into 1 group of differential signals through an FPD-Link III serializer by a serial port bidirectional controller, the differential signals are transmitted to a display screen end through an FPD-Link III protocol, and the display screen end receives the differential signals through a bidirectional control deserializer, restores the differential signals into a plurality of paths of receiving end signals and outputs the signals.

2. The device for transmitting high-speed signals between a host and a display screen of a multi-media navigation split body of claim 1, wherein an ARM core board and an MCU microprocessor are further disposed in the host, wherein the ARM core board outputs 10 LVDS high-definition video signals and 4 TP touch communication signals to the serial bidirectional controller, the MCU microprocessor outputs 2 display screen backlight control signals to the serial bidirectional controller, and the 10 LVDS high-definition video signals, 4 TP touch communication signals and 2 display screen backlight control signals output to the serial bidirectional controller constitute the plurality of transmitting end signals.

3. The high-speed signal transmission device between the main machine and the display screen of the multi-media navigation split-body machine of claim 2, wherein the serial bidirectional controller is a 24-bit color FPD-Link iii serial bidirectional controller with a model number of DS90UB 927Q-Q1.

4. The high-speed signal transmission device between the multi-media navigation split host computer and the display screen according to claim 3, wherein the 10 LVDS high-definition video signals outputted from the ARM core board are LVDS clock signals +, LVDS clock signals-, LVDS data signals 3+, LVDS data signals 3-, LVDS data signals 2+, LVDS data signals 2-, LVDS data signals 1+, LVDS data signals 1-, LVDS data signals 0+, and LVDS data signals 0-, respectively, wherein the LVDS clock signals + are inputted to RXCLKIN + pins of the serial bidirectional controller, the LVDS clock signals-are inputted to RXIN-pins of the serial bidirectional controller, the LVDS data signals 3+ are inputted to RXIN3+ pins of the serial bidirectional controller, the data signals 3-are inputted to RXIN 3-pins of the serial bidirectional controller, the LVDS data signals 2+ are inputted to RXIN2+ pins of the serial bidirectional controller, an LVDS data signal 2-is input to an RXIN 2-pin of the serial bidirectional controller, an LVDS data signal 1+ is input to an RXIN1+ pin of the serial bidirectional controller, an LVDS data signal 1-is input to an RXIN 1-pin of the serial bidirectional controller, an LVDS data signal 0+ is input to an RXIN0+ pin of the serial bidirectional controller, and an LVDS data signal 0-is input to an RXIN 0-pin of the serial bidirectional controller; the ARM core board outputs 4 paths of TP touch communication signals which are respectively TP _ CLK _ clock signals, TP _ DAT _ data signals, TP _ INT _ interrupt signals and TP _ RST _ reset signals, wherein the TP _ CLK _ clock signals are input to an I2C _ SCL pin of the serial port bidirectional controller, the TP _ DAT _ data signals are input to an I2C _ SDA pin of the serial port bidirectional controller, the TP _ INT _ interrupt signals are input to an IIS _ DC/GOIO2 pin of the serial port bidirectional controller, and the TP _ RST _ reset signals are input to a GPIO1 pin of the serial port bidirectional controller; the 2 paths of display screen backlight control signals output by the MCU microprocessor are respectively a display screen backlight PWM pulse control signal output by a PD0(HS)/TIM3_ CC2 pin of the MCU microprocessor and a display screen backlight enabling signal output by a PC4(HS)/TIM1_ CC4 pin of the MCU microprocessor, wherein the display screen backlight PWM pulse control signal is input to an IIS _ DD/GPIO3 pin of the serial port bidirectional controller, and the display screen backlight enabling signal is input to a GPIO0 pin of the serial port bidirectional controller.

5. The device for transmitting high-speed signals between a main frame and a display screen of a multi-media navigation split body according to claim 2, wherein a high-definition LVDS display screen and a TP capacitive touch screen are further arranged in the display screen end, wherein the bidirectional control deserializer outputs 10 paths of LVDS high-definition video signals and 2 paths of display screen backlight control signals to the high-definition LVDS display screen, and outputs 4 paths of TP touch communication signals to the TP capacitive touch screen, and the plurality of paths of receiving end signals are composed of the 10 paths of LVDS high-definition video signals, the 4 paths of TP touch communication signals and the 2 paths of display screen backlight control signals output by the bidirectional control deserializer.

6. The apparatus of claim 5, wherein the bi-directional control deserializer is a 24-bit color FPD-Link III bi-directional control deserializer of DS90UB928Q-Q1 chip.

7. The apparatus for high-speed signal transmission between a multi-media navigation splitter main body and a display screen according to claim 6, wherein the 10 LVDS high-definition video signals outputted by the bi-directional control deserializer are LVDS clock signal outputted by a TXCKOUT + pin of the bi-directional control deserializer, LVDS clock signal outputted by a TXCKOUT-pin of the bi-directional control deserializer, LVDS data signal 3 outputted by a TXCKOUT 3+ pin of the bi-directional control deserializer, LVDS data signal 3 outputted by a TXCUT 3-pin of the bi-directional control deserializer, LVDS data signal 2 outputted by a TXCUT 2+ pin of the bi-directional control deserializer, LVDS data signal 2 outputted by a TXCUT 2-pin of the bi-directional control deserializer, LVDS data signal 1+ outputted by a TXCUT 1+ pin of the bi-directional control deserializer, respectively, LVDS data signal 1 output by TXOUT 1-pin of the bi-directional control deserializer, LVDS data signal 0+ output by TXOUT0+ pin of the bi-directional control deserializer, and LVDS data signal 0 output by TXOUT 0-pin of the bi-directional control deserializer; the 4 paths of TP touch communication signals output by the bidirectional control deserializer are a TP _ CLK _ clock signal output by an SCL pin of the bidirectional control deserializer, a TP _ DAT _ data signal output by an SDA pin of the bidirectional control deserializer, a TP _ INT _ interrupt signal output by an I2S _ DC/GPI02 pin of the bidirectional control deserializer and a TP _ RST _ reset signal output by a GPIO1 pin of the bidirectional control deserializer respectively; the 2 paths of display screen backlight control signals output by the bidirectional control deserializer are a display screen backlight PWM pulse control signal output by an I2S _ DD/GPI03 pin of the bidirectional control deserializer and a display screen backlight enabling signal output by a GPIO0 pin of the bidirectional control deserializer respectively.

8. The apparatus according to claim 5, wherein the 2-channel display backlight control signal outputted from the bi-directional control deserializer is inputted to the high-definition LVDS display through a display backlight driving circuit.

9. The apparatus according to claim 1, wherein the serial bidirectional controller is connected to a display socket, the bidirectional deserializer is connected to a host socket, and the twisted pair shield cable is connected between the display socket and the host socket.