CN209879297U - Control device for lifting national flag - Google Patents

Control device for lifting national flag Download PDF

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Publication number
CN209879297U
CN209879297U CN201920723729.XU CN201920723729U CN209879297U CN 209879297 U CN209879297 U CN 209879297U CN 201920723729 U CN201920723729 U CN 201920723729U CN 209879297 U CN209879297 U CN 209879297U
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pin
resistor
path
chip microcomputer
chip
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Chinese (zh)
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陈卉
文毅
陈李胜
胡云峰
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University of Electronic Science and Technology of China Zhongshan Institute
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University of Electronic Science and Technology of China Zhongshan Institute
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Abstract

The utility model discloses a control device for lifting national flag, including a main control module, the input end of the main control module is electrically connected with a power supply module, a crystal oscillator circuit, a reset circuit and a lifting control circuit, the output end of the main control module is electrically connected with a motor drive chip U2 and an audio play module P1, a motor drive chip U2 is electrically connected with a stepping motor M1, the main control module controls each module to coordinate, the power supply module is the main control module, the crystal oscillator circuit, the audio play module P1, a display module, a motor drive chip U2 and a stepping motor M1 to supply power, the crystal oscillator circuit provides the clock frequency required by the main control module, the lifting control circuit controls the national flag to lift, the output end of the main control module is electrically driven by the motor drive chip U2 to drive the stepping motor M1, meanwhile, the main control module controls the audio play module P1 to play audio, thereby realizing that the national flag, the national flag has uniform lifting speed, is not easy to miss, and creates the atmosphere of the Shensheng solemn.

Description

Control device for lifting national flag
Technical Field
The utility model relates to a controlling means, especially a controlling means of national flag goes up and down.
Background
The national flag is raised and played to show the love of the people, if the national songs cannot be played synchronously in the national flag raising process, the atmosphere of the heyday in the national flag raising process is destroyed, and when the national flag is manually raised and lowered, the flag hand needs to make the raising and lowering speed of the national flag as uniform as possible so as to ensure the ceremony feeling, but the raising and lowering speed of the national flag is difficult to control, and the flag hand is easy to make mistakes.
Disclosure of Invention
In order to overcome the defects of the prior art, the utility model provides a simple, practical and convenient to use control device for lifting national flags.
The utility model provides a technical scheme that its technical problem adopted is:
the utility model provides a controlling means of going up and down national flag, includes main control module, main control module electricity is connected with exclusion RP1, main control module's input electricity is connected with power module, crystal oscillator circuit, reset circuit and lift control circuit, main control module's output electricity is connected with motor drive chip U2 and audio playback module P1, motor drive chip U2 electricity is connected with step motor M1.
The main control module is a single chip microcomputer U1, pin 1 of the resistor RP1 is connected with pin 40 of the single chip microcomputer U1, pin 2 of the resistor RP1 is connected with pin 39 of the single chip microcomputer U1, pin 3 of the resistor RP1 is connected with pin 38 of the single chip microcomputer U1, pin 4 of the resistor RP1 is connected with pin 37 of the single chip microcomputer U1, pin 5 of the resistor RP1 is connected with pin 36 of the single chip microcomputer U1, pin 6 of the resistor RP1 is connected with pin 35 of the single chip microcomputer U1, pin 7 of the resistor RP1 is connected with pin 34 of the single chip microcomputer U1, pin 8 of the resistor RP1 is connected with pin 33 of the single chip microcomputer U1, and pin 9 of the resistor RP1 is connected with pin 32 of the single chip microcomputer U1.
The power module comprises a power interface IN1, a voltage reduction chip VR1, a switch S4, a voltage reduction chip VR2 and a capacitor C5, wherein a pin 1 of the voltage reduction chip VR1 is divided into two paths, one path is connected with an anode output end of the power interface IN1, the other path is connected with a pin 1 of the voltage reduction chip VR2, one end of the switch S4 is grounded, the other end of the switch S4 is connected with a pin 1 of the singlechip U1 and a pin 3 of the voltage reduction chip VR1 is divided into two paths, one path is connected with the reset circuit, the other path is connected with a pin 2 of the voltage reduction chip VR1 through the capacitor C4, a pin 2 of the voltage reduction chip VR2 is grounded, a pin 3 of the voltage reduction chip VR2 is divided into two paths, one path is connected with a node between the pin 2 of the voltage reduction chip VR2 and the ground through the capacitor C5, the other path is connected with the stepping motor M1, and a cathode.
The 1 pin of the audio playing module P1 is connected with the 3 pin of the voltage reduction chip VR1 and a node between the reset circuits, the 2 pin of the audio playing module P1 is connected with the 10 pin of the singlechip U1, the 3 pin of the audio playing module P1 is connected with the 11 pin of the singlechip U1, and the 4 pin of the audio playing module P1 is grounded.
The reset circuit comprises a switch S3, a resistor R3, a polar capacitor C1 and a resistor R4, one end of the switch S3 is divided into three paths, the first path is connected with a node between a capacitor C4 and a pin 3 of a voltage reduction chip VR1, the second path is connected with the anode of the polar capacitor C1, the third path is connected with a pin 1 of the audio playing module P1, the other end of the switch S3 is sequentially grounded through the resistor R3 and the resistor R4, the cathode of the polar capacitor C1 is divided into two paths, one path is connected with a pin 9 of the singlechip U1, and the other path is connected with a node between the resistor R3 and the resistor R4.
The lifting control circuit comprises a switch S1 and a switch S2, one end of the switch S1 is connected with a pin 6 of the singlechip U1, one end of the switch S2 is connected with a pin 7 of the singlechip U1, and the other end of the switch S1 and the other end of the switch S2 are simultaneously grounded.
The crystal oscillator circuit includes crystal oscillator Y1, electric capacity C2 and electric capacity C3, electric capacity C2's one end is divided two the tunnel, connects all the way crystal oscillator Y1's one end, and another way connects singlechip U1's 18 pin, electric capacity C2's the other end is divided two the tunnel, connects all the way singlechip U1's 20 pin, another way ground connection, electric capacity C3's one end is divided two the tunnel, connects all the way crystal oscillator Y1's the other end, and another way connects singlechip U1's 19 pin, electric capacity C3's another termination the node between electric capacity C2's the other end and singlechip U1's 20 pin.
The output end of the main control module is also electrically connected with a display module, the display module comprises a display DIS1, a resistor R1 and an adjustable resistor R2, the first end of the adjustable resistor R2 is divided into two paths, one path is grounded, the other path is connected with a pin 1 of the display DIS1, the second end of the adjustable resistor R2 is divided into three paths, the first path is connected with a pin 2 of the display DIS1, the second path is connected with a pin 15 of the display DIS1 through the resistor R1, the third path is connected with a node between one end of the switch S3 and a pin 3 of the voltage reduction chip VR1, the resistance value of the adjustable resistor R2 is adjusted and connected with a pin 3 of the display DIS1, a pin 4 of the display DIS1 is connected with a pin 17 of the singlechip U1, a pin 5 of the display DIS1 is connected with a pin 16 of the singlechip U1, a pin 6 of the display DIS1 is connected with a pin 15 of the singlechip U42, and a pin 467 of the display DIS 7 is connected with a pin 21 of the singlechip U467, the 8 pins of the display DIS1 are connected with the 22 pins of the single chip microcomputer U1, the 9 pins of the display DIS1 are connected with the 23 pins of the single chip microcomputer U1, the 10 pins of the display DIS1 are connected with the 24 pins of the single chip microcomputer U1, the 11 pins of the display DIS1 are connected with the 25 pins of the single chip microcomputer U1, the 12 pins of the display DIS1 are connected with the 26 pins of the single chip microcomputer U1, the 13 pins of the display DIS1 are connected with the 27 pins of the single chip microcomputer U1, the 14 pins of the display DIS1 are connected with the 28 pins of the single chip microcomputer U1, and the 16 pins of the display DIS1 are grounded.
A pin 1 of the motor driving chip U2 is connected with a node between a pin 2 of the resistor RP1 and a pin 39 of the singlechip U1, a pin 2 of the motor driving chip U2 is connected with a node between a pin 3 of the resistor RP1 and a pin 38 of the singlechip U1, a pin 3 of the motor driving chip U2 is connected with a node between a pin 5 of the resistor RP1 and a pin 36 of the singlechip U1, a pin 4 of the motor driving chip U2 is connected with a node between a pin 6 of the resistor RP1 and a pin 35 of the singlechip U1, a pin 9 of the motor driving chip U2 is connected with an ACOM end of the stepping motor M1, a pin 16 of the motor driving chip U2 is connected with an A end of the stepping motor M1, a pin 15 of the motor driving chip U2 is connected with a pin B end of the stepping motor M1, a pin 14 of the motor driving chip U2 is connected with a pin C end of the stepping motor M1, and a pin 2 of the motor driving chip U9613 is connected with a pin D1 of the stepping motor M9613, the BCOM of the stepping motor M1 is terminated at a node between the 3 pin of the voltage reduction chip VR2 and the capacitor C5, and the ACOM of the stepping motor M1 is terminated at the BCOM end of the stepping motor M1.
The utility model has the advantages that: the utility model discloses a each module of main control module control coordinate the cooperation, power module is main control module, the crystal oscillator circuit, reset circuit, audio playback module P1, a display module, motor drive chip U2 and step motor M1 power supply, the crystal oscillator circuit provides the required clock frequency of main control module, reset circuit makes the main control module repeat executive program, prevent that the procedure operation is unusual, lift control circuit control national flag goes up and down, main control module's output passes through motor drive chip U2 electric drive step motor M1, and simultaneously, main control module control audio playback module P1 broadcast audio frequency, thereby realize, national song when rising national flag, the speed that national flag goes up and down is even, difficult error, build the atmosphere that the saint and solemn is strict.
Drawings
The present invention will be further explained with reference to the drawings and examples.
FIG. 1 is a schematic block diagram of the present invention;
fig. 2 is a schematic circuit diagram of the present invention.
Detailed Description
Referring to fig. 1 and 2, a control device for lifting a national flag comprises a main control module, the main control module is electrically connected with a resistor RP1, an input end of the main control module is electrically connected with a power module, a crystal oscillator circuit, a reset circuit and a lifting control circuit, an output end of the main control module is electrically connected with a motor driving chip U2 and an audio playing module P1, the motor driving chip U2 is electrically connected with a stepping motor M1, the main control module controls the modules to be coordinated, the power module supplies power to the main control module, the crystal oscillator circuit, the reset circuit, an audio playing module P1, a display module, a motor driving chip U2 and a stepping motor M1, the crystal oscillator circuit provides a clock frequency required by the main control module, the reset circuit enables the main control module to execute a program again, the program is prevented from running abnormally, the lifting control circuit controls the national flag to be lifted, an output end of the main control module is electrically driven by the motor, meanwhile, the main control module controls the audio playing module P1 to play audio, so that the national flag is raised and played synchronously, the national flag is raised and lowered at a uniform speed, errors are not easy to occur, and the atmosphere of the Shensheng solemn is created.
The main control module is a single chip microcomputer U1, pin 1 of the resistor RP1 is connected with pin 40 of the single chip microcomputer U1, pin 2 of the resistor RP1 is connected with pin 39 of the single chip microcomputer U1, pin 3 of the resistor RP1 is connected with pin 38 of the single chip microcomputer U1, pin 4 of the resistor RP1 is connected with pin 37 of the single chip microcomputer U1, pin 5 of the resistor RP1 is connected with pin 36 of the single chip microcomputer U1, pin 6 of the resistor RP1 is connected with pin 35 of the single chip microcomputer U1, pin 7 of the resistor RP1 is connected with pin 34 of the single chip microcomputer U1, pin 8 of the resistor RP1 is connected with pin 33 of the single chip microcomputer U1, pin 9 of the resistor RP1 is connected with pin 32 of the single chip microcomputer U1, and the resistor RP1 is a pull-up resistor, so as to drive the motor drive chip U2.
The power module comprises a power interface IN1, a voltage reduction chip VR1, a switch S4, a voltage reduction chip VR2 and a capacitor C5, wherein a pin 1 of the voltage reduction chip VR1 is divided into two paths, one path is connected with a positive electrode output end of the power interface IN1, the other path is connected with a pin 1 of the voltage reduction chip VR2, one end of the switch S4 is grounded, the other end of the switch S4 is connected with a pin 1 of the singlechip U1, a pin 3 of the voltage reduction chip VR1 is divided into two paths, one path is connected with the reset circuit, the other path is connected with a pin 2 of the voltage reduction chip VR1 through the capacitor C4, a pin 2 of the voltage reduction chip VR2 is grounded, a pin 3 of the voltage reduction chip VR2 is divided into two paths, one path is connected with a node between the pin 2 of the voltage reduction chip VR2 and the ground through the capacitor C5, the other path is connected with the stepping motor M1, a negative electrode output end of the power interface VR 365 is grounded, IN the present embodiment, the voltage reduction chip VR, the power interface IN1 is connected to an external power supply which outputs 12V direct current and then outputs 12V direct current, the voltage reduction chip VR1 reduces the 12V direct current to 5V direct current and then supplies power to the reset circuit, the audio circuit and the display module, the voltage reduction chip VR2 reduces the 12V direct current to 5V direct current and then supplies power to the stepping motor, once the switch S4 is closed, the single chip U1 times, the closing time of the switch S4 is displayed through the display module, the time required by national flag raising or national flag lowering is counted, when the switch S4 is closed for a period of time, the single chip U1 also calculates the height of the national flag according to the closing time of the switch S4 and displays the height through the display module, and when the national flag rises to the top of the flag pole (namely, the height of the national flag is the largest), the U1 stops timing.
The 1 pin of the audio playing module P1 is connected with a node between the 3 pin of the voltage reduction chip VR1 and the reset circuit, the 2 pin of the audio playing module P1 is connected with the 10 pin of the single chip microcomputer U1, the 3 pin of the audio playing module P1 is connected with the 11 pin of the single chip microcomputer U1, and the 4 pin of the audio playing module P1 is grounded.
The reset circuit comprises a switch S3, a resistor R3, a polar capacitor C1 and a resistor R4, wherein one end of the switch S3 is divided into three paths, the first path is connected with a node between a capacitor C4 and a pin 3 of a voltage reduction chip VR1, the second path is connected with the anode of the polar capacitor C1, the third path is connected with a pin 1 of the audio playing module P1, the other end of the switch S3 is sequentially grounded through the resistor R3 and the resistor R4, the cathode of the polar capacitor C1 is divided into two paths, one path is connected with a pin 9 of the singlechip U1, the other path is connected with a node between the resistor R3 and the resistor R4, and the pin 9 of the singlechip U1 can be reset by inputting a high level, so that the switch S3 is closed to reset the singlechip U1, when reset is not needed, the switch S3 is disconnected, and generally needs to be reset before being used each time.
The lifting control circuit comprises a switch S1 and a switch S2, one end of the switch S1 is connected with a pin 6 of the single chip microcomputer U1, one end of the switch S2 is connected with a pin 7 of the single chip microcomputer U1, the other end of the switch S1 and the other end of the switch S2 are grounded simultaneously, and the switch S1 and the switch S2 control the driving motor to rotate forward and backward so as to control the lifting of the national flag.
The crystal oscillator circuit comprises a crystal oscillator Y1, a capacitor C2 and a capacitor C3, one end of the capacitor C2 is divided into two paths, one path is connected with one end of the crystal oscillator Y1, the other path is connected with the 18 pins of the singlechip U1, the other end of the capacitor C2 is divided into two paths, one path is connected with the 20 pins of the singlechip U1, the other path is grounded, one end of the capacitor C3 is divided into two paths, one path is connected with the other end of the crystal oscillator Y1, the other path is connected with the 19 pins of the singlechip U1, the other end of the capacitor C3 is connected with a node between the other end of the capacitor C2 and the 20 pins of the singlechip U1, and two ends of the crystal oscillator Y1 are provided with parallel capacitors to form a parallel resonant circuit to provide the needed clock frequency for the singlechip U.
The output end of the main control module is also electrically connected with a display module, the display module comprises a display DIS1, a resistor R1 and an adjustable resistor R2, the first end of the adjustable resistor R2 is divided into two paths, one path is grounded, the other path is connected with a pin 1 of the display DIS1, the second end of the adjustable resistor R2 is divided into three paths, the first path is connected with a pin 2 of the display DIS1, the second path is connected with a pin 15 of the display DIS1 through the resistor R1, the third path is connected with a node between one end of the switch S3 and a pin 3 of the voltage reduction chip VR1, the resistance value of the adjustable resistor R2 is adjusted and connected with a pin 3 of the display DIS1, a pin 4 of the display DIS1 is connected with a pin 17 of the singlechip U1, a pin 5 of the display DIS1 is connected with a pin 16 of the singlechip U1, a pin 6 of the display DIS1 is connected with a pin 15 of the singlechip U42, and a pin 467 of the display DIS 7 is connected with a pin 21 of the singlechip U467, 8 feet of the display DIS1 are connected with 22 pins of the single chip microcomputer U1, 9 feet of the display DIS1 are connected with 23 pins of the single chip microcomputer U1, 10 feet of the display DIS1 are connected with 24 pins of the single chip microcomputer U1, 11 feet of the display DIS1 are connected with 25 pins of the single chip microcomputer U1, 12 feet of the display DIS1 are connected with 26 pins of the single chip microcomputer U1, 13 feet of the display DIS1 are connected with 27 pins of the single chip microcomputer U1, 14 feet of the display DIS1 are connected with 28 pins of the single chip microcomputer U1, 16 feet of the display DIS1 are grounded, and the display DIS1 is of the type LCD1602, can display numbers and letters, can meet the display requirements of the utility model, and has the advantages of simple driving, low cost and the like.
Pin 1 of the motor driving chip U2 is connected with a node between pin 2 of the resistor RP1 and pin 39 of the singlechip U1, pin 2 of the motor driving chip U2 is connected with a node between pin 3 of the resistor RP1 and pin 38 of the singlechip U1, pin 3 of the motor driving chip U2 is connected with a node between pin 5 of the resistor RP1 and pin 36 of the singlechip U1, pin 4 of the motor driving chip U2 is connected with a node between pin 6 of the resistor RP1 and pin 35 of the singlechip U1, pin 9 of the motor driving chip U2 is connected with an ACOM end of the stepping motor M1, the ACOM end is a common end of an A end of the stepping motor M1 and a B end of the stepping motor M1, pin 16 of the motor driving chip U2 is connected with an A end of the stepping motor M1, and pin 15 of the motor driving chip U2 is connected with a B end of the stepping motor M1, a pin 14 of the motor driver chip U2 is connected to a terminal C of the stepping motor M1, a pin 13 of the motor driver chip U2 is connected to a terminal D of the stepping motor M1, a BCOM of the stepping motor M1 is connected to a node between a pin 3 of the step-down chip VR2 and a capacitor C5, an ACOM of the stepping motor M1 is connected to a terminal BCOM of the stepping motor M1, the single chip U1 outputs a driving signal through the motor driver chip U2 (all of the pin 9, the pin 16, the pin 15, the pin 14, and the pin 13 of the motor driver chip U2 can output the driving signal), so as to control the forward and reverse rotation of the stepping motor M1 and the rotation speed of the stepping motor M1, the step-down chip VR2 supplies power to the stepping motor M1, and in this embodiment, the model number of the motor driver chip U2 is ULN 2003.
The above embodiments do not limit the scope of the present invention, and those skilled in the art can make equivalent modifications and variations without departing from the overall concept of the present invention.

Claims (9)

1. The utility model provides a controlling means of going up and down national flag, includes main control module, main control module electricity is connected with exclusion RP1, its characterized in that main control module's input electricity is connected with power module, crystal oscillator circuit, reset circuit and lift control circuit, main control module's output electricity is connected with motor drive chip U2 and audio playback module P1, motor drive chip U2 electricity is connected with step motor M1.
2. The national flag lifting control device according to claim 1, wherein the main control module is a single chip microcomputer U1, pin 1 of the resistor RP1 is connected to pin 40 of the single chip microcomputer U1, pin 2 of the resistor RP1 is connected to pin 39 of the single chip microcomputer U1, pin 3 of the resistor RP1 is connected to pin 38 of the single chip microcomputer U1, pin 4 of the resistor RP1 is connected to pin 37 of the single chip microcomputer U1, pin 5 of the resistor RP1 is connected to pin 36 of the single chip microcomputer U1, pin 6 of the resistor RP1 is connected to pin 35 of the single chip microcomputer U1, pin 7 of the resistor RP1 is connected to pin 34 of the single chip microcomputer U1, pin 8 of the resistor RP1 is connected to pin 33 of the single chip microcomputer U1, and pin 9 of the resistor RP1 is connected to pin 32 of the single chip microcomputer U1.
3. The device as claimed IN claim 2, wherein the power module comprises a power interface IN1, a voltage-reducing chip VR1, a switch S4, a voltage-reducing chip VR2 and a capacitor C5, wherein pin 1 of the voltage-reducing chip VR1 is divided into two paths, one path is connected to the positive output terminal of the power interface IN1, the other path is connected to pin 1 of the voltage-reducing chip VR2, one end of the switch S4 is grounded, the other end of the switch S4 is connected to pin 1 of the single-chip U1, pin 3 of the voltage-reducing chip VR1 is divided into two paths, one path is connected to the reset circuit, the other path is connected to pin 2 of the voltage-reducing chip VR1 through the capacitor C4, pin 2 of the voltage-reducing chip VR2 is grounded, pin 3 of the voltage-reducing chip VR2, one path is connected to the node between pin 2 of the voltage-reducing chip VR2 and the ground through the capacitor C5, and the other path is connected to the stepping motor M1, the negative output terminal of the power interface IN1 is grounded.
4. The device as claimed in claim 3, wherein pin 1 of the audio playback module P1 is connected to a node between pin 3 of the voltage-reducing chip VR1 and the reset circuit, pin 2 of the audio playback module P1 is connected to pin 10 of the single-chip microcomputer U1, pin 3 of the audio playback module P1 is connected to pin 11 of the single-chip microcomputer U1, and pin 4 of the audio playback module P1 is connected to ground.
5. The device for controlling national flag lifting according to claim 4, wherein the reset circuit comprises a switch S3, a resistor R3, a polar capacitor C1 and a resistor R4, one end of the switch S3 is divided into three paths, the first path is connected with a node between the capacitor C4 and a pin 3 of a voltage reduction chip VR1, the second path is connected with an anode of the polar capacitor C1, the third path is connected with a pin 1 of the audio playing module P1, the other end of the switch S3 is grounded through the resistor R3 and the resistor R4 in sequence, the cathode of the polar capacitor C1 is divided into two paths, one path is connected with a pin 9 of the singlechip U1, and the other path is connected with a node between the resistor R3 and the resistor R4.
6. The device for controlling national flag raising and lowering of claim 5, wherein the raising and lowering control circuit comprises a switch S1 and a switch S2, one end of the switch S1 is connected to pin 6 of the single chip microcomputer U1, one end of the switch S2 is connected to pin 7 of the single chip microcomputer U1, and the other end of the switch S1 and the other end of the switch S2 are simultaneously grounded.
7. The national flag lifting control device according to claim 6, wherein the crystal oscillator circuit comprises a crystal oscillator Y1, a capacitor C2 and a capacitor C3, one end of the capacitor C2 is divided into two paths, one path is connected with one end of the crystal oscillator Y1, the other path is connected with the 18 pin of the singlechip U1, the other end of the capacitor C2 is divided into two paths, one path is connected with the 20 pin of the singlechip U1, the other path is grounded, one end of the capacitor C3 is divided into two paths, one path is connected with the other end of the crystal oscillator Y1, the other path is connected with the 19 pin of the singlechip U1, and the other end of the capacitor C3 is connected with a node between the other end of the capacitor C2 and the 20 pin of the singlechip U1.
8. The device as claimed in claim 7, wherein the output terminal of the main control module is further electrically connected to a display module, the display module includes a display DIS1, a resistor R1 and an adjustable resistor R2, a first terminal of the adjustable resistor R2 is divided into two paths, one path is grounded, the other path is connected to pin 1 of the display DIS1, a second terminal of the adjustable resistor R2 is divided into three paths, the first path is connected to pin 2 of the display DIS1, the second path is connected to pin 15 of the display DIS1 through the resistor R1, the third path is connected to a node between one terminal of the switch S3 and pin 3 of the voltage-reducing chip VR1, a resistance value of the adjustable resistor R2 is connected to pin 3 of the display DIS1, pin 4 of the display DIS1 is connected to pin 17 of the single-chip microcomputer U1, pin 5 of the display DIS1 is connected to pin 16 of the single-chip microcomputer U1, and pin 396 of the display DIS1 is connected to pin 3615 of the single-chip microcomputer U1, the 7 pin of the display DIS1 is connected with the 21 pin of the singlechip U1, the 8 pin of the display DIS1 is connected with the 22 pin of the singlechip U1, the 9 pin of the display DIS1 is connected with the 23 pin of the singlechip U1, the 10 pin of the display DIS1 is connected with the 24 pin of the singlechip U1, the 11 pin of the display DIS1 is connected with the 25 pin of the singlechip U1, the 12 pin of the display DIS1 is connected with the 26 pin of the singlechip U1, the 13 pin of the display DIS1 is connected with the 27 pin of the singlechip U1, the 14 pin of the display DIS1 is connected with the 28 pin of the singlechip U1, and the 16 pin of the display DIS1 is grounded.
9. The national flag raising and lowering control device as claimed in claim 8, wherein pin 1 of the motor driving chip U2 is connected to a node between pin 2 of the resistor RP1 and pin 39 of the single chip microcomputer U1, pin 2 of the motor driving chip U2 is connected to a node between pin 3 of the resistor RP1 and pin 38 of the single chip microcomputer U1, pin 3 of the motor driving chip U2 is connected to a node between pin 5 of the resistor RP1 and pin 36 of the single chip microcomputer U1, pin 4 of the motor driving chip U2 is connected to a node between pin 6 of the resistor RP1 and pin 35 of the single chip microcomputer U1, pin 9 of the motor driving chip U2 is connected to the ACOM terminal of the stepping motor M1, pin 16 of the motor driving chip U2 is connected to the A terminal of the stepping motor M1, pin 15 of the motor driving chip U2 is connected to the B terminal of the stepping motor M1, pin 14 of the motor driving chip U2 is connected to the C terminal 1 of the stepping motor M362, the pin 13 of the motor driving chip U2 is connected with the D end of the stepping motor M1, the BCOM end of the stepping motor M1 is connected with the node between the pin 3 of the voltage reduction chip VR2 and the capacitor C5, and the ACOM end of the stepping motor M1 is connected with the BCOM end of the stepping motor M1.
CN201920723729.XU 2019-05-20 2019-05-20 Control device for lifting national flag Active CN209879297U (en)

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Application Number Priority Date Filing Date Title
CN201920723729.XU CN209879297U (en) 2019-05-20 2019-05-20 Control device for lifting national flag

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Application Number Priority Date Filing Date Title
CN201920723729.XU CN209879297U (en) 2019-05-20 2019-05-20 Control device for lifting national flag

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CN209879297U true CN209879297U (en) 2019-12-31

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Country Link
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