CN209877876U

CN209877876U - LVDT/RVDT sensor measuring card

Info

Publication number: CN209877876U
Application number: CN201921086723.2U
Authority: CN
Inventors: 宋俊; 华伟
Original assignee: Chengdu Enfit Technology Co Ltd
Current assignee: Chengdu Enfit Technology Co Ltd
Priority date: 2019-07-12
Filing date: 2019-07-12
Publication date: 2019-12-31
Anticipated expiration: 2029-07-12

Abstract

The utility model discloses a LVDT/RVDT sensor measurement card, including control module, LVDT/RVDT sensor measurement card still includes excitation signal generating circuit module, ADC module, reference circuit voltage module, DAC module and sensing signal acquisition circuit module, and control module is connected with ADC module and DAC module respectively, and reference circuit voltage module is connected with ADC module and DAC module respectively, and sensing signal acquisition circuit module is connected with the ADC module, and excitation signal generating circuit module is connected with the DAC module. The utility model discloses can connect the LVDT and the RVDT sensor of 4/5/6 line and measure, can be used to the test measurement of LVDT/RVDT system, the utility model discloses can be used to EP-H5605.

Description

LVDT/RVDT sensor measuring card

Technical Field

The utility model relates to a measurement of sensor, in particular to LVDT/RVDT sensor measurement card.

Background

The LVDT/RVDT sensor utilizes the principle that the transformer transformation ratio changes along with the change of the transformer core. An alternating current excitation signal is input to the primary side, and a corresponding induction signal is output to the secondary side. The sensor has three types of 4-wire, 5-wire and 6-wire systems, and the working frequency is 1 KHz-5 KHz.

The measuring equipment judges the magnitude and direction of the position and angle change of the sensor by comparing the amplitude and phase of the excitation signal with the amplitude and phase of the output signal of the sensor.

The existing measurement scheme is to adopt special LVDT/RVDT measurement chips, such as AD598, AD698 and the like, and products adopting the schemes can only be connected with 4-line sensors or only can be connected with 5-line and 6-line sensors, and the working frequency is fixed and cannot adapt to all sensors.

SUMMERY OF THE UTILITY MODEL

One of the objects of the present invention is to provide an LVDT/RVDT sensor measuring card, which can be connected to the LVDT and RVDT sensors of 4/5/6 lines for measurement, and can be used for testing and measuring the LVDT/RVDT system.

The technical scheme is as follows: the LVDT/RVDT sensor measuring card comprises a control module, and further comprises an excitation signal generating circuit module, an ADC module, a reference circuit voltage module, a DAC module and an induction signal acquisition circuit module, wherein the control module is respectively connected with the ADC module and the DAC module, the reference circuit voltage module is respectively connected with the ADC module and the DAC module, the induction signal acquisition circuit module is connected with the ADC module, and the excitation signal generating circuit module is connected with the DAC module; the control module generates a sinusoidal parameter of the excitation signal and outputs the generated sinusoidal parameter of the excitation signal to the DAC module, the DAC module outputs a sinusoidal signal, and the sinusoidal signal forms a differential sinusoidal signal through the excitation signal generation circuit module and is input to the primary side of the LVDT/RVDT sensor to be detected; the secondary side of the LVDT/RVDT sensor to be tested forms sensing signals, the sensing signals are collected and converted into positive end signals by the sensing signal collection circuit module and then input into the ADC module for analog-to-digital conversion and then input into the control module, and the reference circuit voltage module generates reference voltages and respectively inputs the reference voltages into the ADC module and the DAC module.

Preferably, the control module is an FPGA controller.

Preferably, the DAC modules are two DACs 8831, the two DACs 8831 are a first DAC8831 and a second DAC8831, respectively, and the ADC modules are AD 7768-8.

Preferably, the reference circuit voltage module comprises a voltage reference chip, a first reference circuit emitter follower circuit module and a second reference circuit emitter follower circuit module, one end of each of the first reference circuit emitter follower circuit module and the second reference circuit emitter follower circuit module is connected with the voltage reference chip, the other end of the first reference circuit emitter follower circuit module is connected with the ADC module, and the other end of the second reference circuit emitter follower circuit module is connected with the DAC module.

Preferably, the LVDT/RVDT sensor measurement card further comprises a non-polar capacitor C₁Non-polar capacitor C₂Non-polar capacitor C₃Non-polar capacitor C₄Non-polar capacitor C₅Non-polar capacitor C₆Non-polar capacitor C₇Non-polar capacitor C₈Current limiting resistor R₁The first power supply positive electrode, the second power supply positive electrode, the third power supply positive electrode, the first ground source, the second ground source connection, the third ground source, the fourth ground source, the fifth ground source and the sixth ground source; the voltage reference chip is provided with a first pin of the voltage reference chip, a second pin of the voltage reference chip, a third pin of the voltage reference chip, a fourth pin of the voltage reference chip, a fifth pin of the voltage reference chip, a sixth pin of the voltage reference chip, a seventh pin of the voltage reference chip and an eighth pin of the voltage reference chip; the first reference circuit emitter follower circuit module is provided with a first pin of the first reference circuit emitter follower circuit module, a second pin of the first reference circuit emitter follower circuit module, a third pin of the first reference circuit emitter follower circuit module, a fourth pin of the first reference circuit emitter follower circuit module and a fifth pin of the first reference circuit emitter follower circuit module; the second reference circuit emitter follower circuit module is provided with a first pin of the second reference circuit emitter follower circuit module, a second pin of the second reference circuit emitter follower circuit module, a third pin of the second reference circuit emitter follower circuit module, a fourth pin of the second reference circuit emitter follower circuit module and a fifth pin of the second reference circuit emitter follower circuit module; non-polar capacitor C₁And a non-polar capacitor C₂After parallel connection, one end of the voltage reference chip is connected with the positive electrode of the first power supply, the other end of the voltage reference chip is connected with the first grounding source, the second pin of the voltage reference chip is connected with the positive electrode of the voltage of the first power supply, the fourth pin of the voltage reference chip is connected with the first grounding source, and the non-polar capacitor C₃Non-polar capacitor C₄One end of the resistor is connected with a current-limiting resistor R in parallel₁Connected to a second ground source, and a current limiting resistor R₁The other end of the first reference circuit emitter follower circuit module is connected with a sixth pin of the voltage reference chip, and a third pin of the first reference circuit emitter follower circuit module is connected with a third pin of the second reference circuit emitter follower circuit module and then connected with a non-polar capacitor C in parallel₃Non-polar capacitor C₄The second pin of the first reference circuit emitter follower circuit module is connected with a third grounding source, the second pin of the second reference circuit emitter follower circuit module is connected with a fourth grounding source, the fifth pin of the first reference circuit emitter follower circuit module is connected with the positive electrode of a second power supply, the fifth pin of the second reference circuit emitter follower circuit module is connected with the positive electrode of a third power supply, and a non-polar capacitor C is arranged between the fifth pin of the second reference circuit emitter follower circuit module and the positive electrode of the third power supply₅And a non-polar capacitor C₆After being connected in parallel, one end of the first reference circuit emitter follower circuit module is connected with a fifth grounding source, the other end of the first reference circuit emitter follower circuit module is equipotential with a fourth pin of the first reference circuit emitter follower circuit module, the first pin of the first reference circuit emitter follower circuit module is equipotential with the fourth pin of the first reference circuit emitter follower circuit module, and a non-polar capacitor C₇And a non-polar capacitor C₈After the parallel connection, one end of the second reference circuit emitter follower circuit module is connected with a sixth grounding source, the other end of the second reference circuit emitter follower circuit module is equal in potential to a fourth pin of the second reference circuit emitter follower circuit module, and the first pin of the second reference circuit emitter follower circuit module is equal in potential to the fourth pin of the second reference circuit emitter follower circuit module.

Preferably, the drive signal generation circuit module includes a first DAC adaptive amplifier, a first drive signal generation power amplifier, a first drive signal generation emitter follower amplifier, a second DAC adaptive amplifier, a second drive signal generation power amplifier, and a second drive signal generation emitter follower amplifier, the first DAC adaptive amplifier is connected to the first DAC8831 and the first drive signal generation power amplifier, respectively, the first drive signal generation emitter follower amplifier is connected to the first drive signal generation power amplifier, the second DAC adaptive amplifier is connected to the second DAC8831 and the second drive signal generation power amplifier, and the second drive signal generation emitter follower amplifier is connected to the second drive signal generation power amplifier.

Preferably, the drive signal generation circuit module further includes a first drive signal generation protection circuit and a second drive signal generation protection circuit, the first drive signal generation emitter follower amplifier is connected to the first drive signal generation protection circuit, and the second drive signal generation protection circuit is connected to the second drive signal generation emitter follower amplifier.

Preferably, the LVDT/RVDT sensor measurement card further comprises a first inductor L₁A first inductor L₂Resistance R₄Resistance R₅Resistance R₆Resistance R₇Current limiting resistor R₂Current limiting resistor R₃Resistance R₈Resistance R₉Non-polar capacitor C₉Non-polar capacitor C₁₀Non-polar capacitor C₁₇Non-polar capacitor C₁₈Non-polar capacitor C₁₁Non-polar capacitor C₁₆And an electrolytic capacitor C₁₂And an electrolytic capacitor C₁₅And an electrolytic capacitor C₁₃And an electrolytic capacitor C₁₄A seventh ground source, an eighth ground source, a ninth ground source, a tenth ground source, an eleventh ground source, a twelfth ground source, a thirteenth ground source, a fourteenth ground source, a fifteenth ground source, a sixteenth ground source, a seventeenth ground source, an eighteenth ground source, a nineteenth ground source, a twentieth ground source, a twenty-first ground source, a twenty-second ground source, a fourth power source, a fifth power source, a sixth power source, a seventh power source, an eighth power source, a ninth power source, a tenth power source, and an eleventh power source; the first DAC8831 is provided with a first DAC first pin, a first DAC second pin, a first DAC third pin, a first DAC fourth pin, a first DAC fifth pin, a first DAC sixth pin, a first DAC seventh pin, a first DAC eighth pin, a first DAC ninth pin, a first DAC tenth pin, a first DAC third pinA DAC eleventh pin, a first DAC twelfth pin, a first DAC thirteenth pin and a first DAC fourteenth pin; the second DAC8831 is provided with a first DAC first pin, a second DAC second pin, a second DAC third pin, a second DAC fourth pin, a second DAC fifth pin, a second DAC sixth pin, a second DAC seventh pin, a second DAC eighth pin, a second DAC ninth pin, a second DAC tenth pin, a second DAC eleventh pin, a second DAC twelfth pin, a second DAC thirteenth pin and a second DAC fourteenth pin; the first DAC adaptive amplifier is provided with a first DAC adaptive first input end, a first DAC adaptive second input end and a first DAC adaptive output end, and the second DAC adaptive amplifier is provided with a second DAC adaptive first input end, a second DAC adaptive second input end and a second DAC adaptive first output end; the first excitation signal generation power amplifier is provided with a first power amplification first input end, a first power amplification second input end and a first power amplification output end, and the second excitation signal generation power amplifier is provided with a second power amplification first input end, a second power amplification second input end and a second power amplification output end; the first driving signal generation emitter follower amplifier is provided with a first emitter follower first input end, a first emitter follower second input end and a first emitter follower output end, and the second driving signal generation emitter follower amplifier is provided with a second emitter follower first input end, a second emitter follower second input end and a second emitter follower output end; the first DAC first pin is connected with the first DAC adaptive output end, and the second DAC second pin is connected with the first inductor L₁Connected, a first inductor L₁The other end of the capacitor is equal to the second input end adapted to the first DAC, and the capacitor C is non-polar₉One end of the first DAC is matched with the second input end, the other end of the first DAC is connected with a seventh ground source, the seventh ground source is also connected with a third pin of the first DAC and a fourth pin of the first DAC, and a non-polar capacitor C is arranged between the first DAC and the fourth pin of the first DAC₁₀One end of the first DAC is connected with the eighth ground source, the other end of the first DAC is in equal potential with the fifth pin of the first DAC and the sixth pin of the first DAC, the eleventh pin of the first DAC and the twelfth pin of the first DAC are connected with the ninth ground source, the thirteenth pin of the first DAC is connected with the adaptive first input end of the first DAC, and the non-polar capacitor C is connected with the adaptive first input end of the first DAC₁₁One end is connected with the tenth connectorThe other end of the ground source is connected with the positive electrode of a fourth power supply, a fourteenth pin of the first DAC is connected with the positive electrode of the fourth power supply, the adaptive output end of the first DAC is connected with the positive electrode of the sixth power supply between the adaptive output end of the first DAC and the two ends of the adaptive first input end of the first DAC, and the adaptive output end of the first DAC is connected with the negative electrode of the sixth power supply between the adaptive output end of the first DAC and the two ends of the adaptive; electrolytic capacitor C₁₂One end of the resistor is connected with the fifteenth grounding source, the other end of the resistor is equal to the first power amplification first input end in potential, and the resistor R₄One end of the resistor R is equal to the adaptive output end of the first DAC, the other end of the resistor R is equal to the first power amplification first input end₆One end of the first power amplification output end is equipotential with the first power amplification first input end, the other end of the first power amplification output end is equipotential with the first power amplification second input end, the first power amplification second input end is connected with a sixteenth ground source, the first power amplification output end is connected with the positive electrode of an eighth power supply between the two ends of the first power amplification first input end, and the first power amplification output end is connected with the negative electrode of the eighth power supply between the two ends of the first power amplification second input end; electrolytic capacitor C₁₃One end of the current limiting resistor is connected with the nineteenth grounding source, the other end of the current limiting resistor is equal to the potential of the first emitter along with the second input end₂One end of the first emitter follower output end is equipotential with the first power amplification output end, the other end of the first emitter follower output end is equipotential with the second input end of the first emitter follower, the first emitter follower output end is equipotential with the first input end of the first emitter follower, the first emitter follower output end is connected with the positive electrode of the tenth power supply between the first emitter follower output end and the two ends of the first emitter follower input end, and the first emitter follower output end is connected with the negative electrode of the tenth power supply between the first emitter follower output end and the two ends of the first emitter; resistance R₈One end of the first excitation signal generation protection circuit is equal to the potential of the first emitter following output end, one end of the first excitation signal generation protection circuit is connected with the twenty-first grounding source, and the other end of the first excitation signal generation protection circuit is connected with the resistor R₈Equipotential; the first pin of the second DAC is connected with the first output end of the second DAC, and the second pin of the second DAC is connected with the second inductor L₂Connected, a second inductor L₂The other end of the capacitor is equal to the second input end of the second DAC in potential, and the capacitor C is non-polar₁₇One end of the first DAC is matched with the second input end, the other end of the first DAC is connected with an eleventh ground source, the eleventh ground source is also connected with a third pin of the second DAC and a fourth pin of the second DAC, and the first DAC is electrodelessSex capacitor C₁₈One end of the first DAC is connected with a twelfth ground source, the other end of the first DAC is equal in potential with a fifth pin of the second DAC and a sixth pin of the second DAC, an eleventh pin of the second DAC and a twelfth pin of the second DAC are connected with a thirteenth ground source, a thirteenth pin of the second DAC is connected with a first adaptive DAC input end, and a non-polar capacitor C is connected with the first adaptive DAC input end₁₆One end of the first DAC is connected with a fifth ground source, the other end of the first DAC is connected with a fifth power supply positive electrode, a fourteenth pin of the second DAC is connected with the fifth power supply positive electrode, the adaptive output end of the second DAC is connected with the seventh power supply positive electrode between the two ends of the adaptive first input end of the second DAC, and the adaptive output end of the second DAC is connected with the seventh power supply negative electrode between the two ends of the adaptive second input end of the second DAC; electrolytic capacitor C₁₅One end of the resistor is connected with the seventeenth grounding source, the other end of the resistor is equal to the potential of the first input end of the second power amplifier, and the resistor R₅One end of the resistor R is equal to the adaptive output end of the second DAC, the other end of the resistor R is equal to the first power amplification input end of the second DAC, and the other end of the resistor R is equal to the adaptive output end of the second DAC₇One end of the first power amplification output end is equipotential with the first input end of the first power amplification, the other end of the first power amplification output end is equipotential with the second input end of the second power amplification, the second input end of the first power amplification is connected with the eighteenth ground source, the second power amplification output end is connected with the positive electrode of the ninth power supply between the two ends of the first input end of the second power amplification, and the second power amplification output end is connected with the negative electrode of the ninth power supply between the two ends of the second input end of the second power amplification; electrolytic capacitor C₁₄One end of the current limiting resistor is connected with the twentieth ground source, the other end of the current limiting resistor is equal to the potential of the second emitter along with the second input end₃One end of the second emitter follower output end is equipotential with the second power amplification output end, the other end of the second emitter follower output end is equipotential with the second emitter follower input end, the second emitter follower output end is connected with the eleventh power supply anode between the second emitter follower output end and the two ends of the second emitter follower input end, and the second emitter follower output end is connected with the eleventh power supply cathode between the second emitter follower output end and the two ends of the second emitter follower input end; resistance R₉One end of the first excitation signal generation protection circuit is equal to the potential of the first emitter following output end, one end of the first excitation signal generation protection circuit is connected with the twenty-second ground source, and the other end of the first excitation signal generation protection circuit is connected with the resistor R₉And (3) equipotential.

Preferably, the sensing signal acquisition circuit module comprises an ADC adapter amplifier, a first sensing signal isolation amplifier, a first sensing signal protection circuit, a second sensing signal isolation amplifier and a second sensing signal protection circuit, the ADC adapter amplifier is connected to the ADC module, the first sensing signal isolation amplifier and the second sensing signal isolation amplifier are respectively connected to the ADC adapter amplifier, the first sensing signal protection circuit is connected to the first sensing signal isolation amplifier, and the second sensing signal protection circuit is connected to the second sensing signal isolation amplifier.

Preferably, the LVDT/RVDT sensor measurement card further comprises a non-polar capacitor C₁₉Non-polar capacitor C₂₀Non-polar capacitor C₂₁Resistance R₁₈Resistance R₁₄Resistance R₁₆Resistance R₁₇Resistance R₁₂Resistance R₁₃Resistance R₁₀Resistance R₁₁A twenty-third ground source, a twenty-fourth ground source, a twenty-fifth ground source, a twenty-sixth ground source, a twenty-seventh ground source, a twelfth power source and a thirteenth power source; the ADC adaptive amplifier is provided with an ADC first pin, an ADC second pin, an ADC third pin, an ADC fourth pin, an ADC fifth pin, an ADC sixth pin, an ADC seventh pin and an ADC eighth pin; the first induction signal isolation amplifier is provided with a first induction signal isolation first input end, a first induction signal isolation second input end and a first induction signal isolation output end, and the second induction signal isolation amplifier is provided with a second induction signal isolation first input end, a second induction signal isolation second input end and a second induction signal isolation output end; resistance R₁₈One end of the resistor is equal to the potential of the eighth pin of the ADC, the other end of the resistor is equal to the potential of the fifth pin of the ADC, and the resistor R₁₉One end of the resistor is equal to the potential of the first pin of the ADC, the other end of the resistor is equal to the potential of the fourth pin of the ADC, and the resistor R₁₄One end of the capacitor is equal to the potential of the fifth pin of the ADC, and the other end of the capacitor is connected with a non-polar capacitor C₁₉One end is equipotential, resistance R₁₅One end of the capacitor is equal to the potential of the fourth pin of the ADC, and the other end of the capacitor is connected with a non-polar capacitor C₂₀One end of the capacitor is equipotential and has no polarity₁₉And a non-polar capacitor C₂₀The other ends are connected with the twenty-third groundingSource, non-polar capacitor C₂₁One terminal and resistor R₁₄One end far away from the fifth pin of the ADC is equipotential, and the other end is connected with the resistor R₁₅The end far away from the fourth pin of the ADC has the same potential, the sixth pin of the ADC is connected with a twenty-fourth ground source, the third pin of the ADC is connected with the anode of a twelfth power supply, and a resistor R₁₆One end of the resistor is equipotential with the eighth pin of the ADC, the other end of the resistor is equipotential with the first induction signal isolation output end, and the resistor R₁₇One end is equipotential with the first pin of ADC, the other end is equipotential with the second sensing signal isolation output end, the first sensing signal isolation first input end is equipotential with the first sensing signal isolation output end, the second sensing signal isolation first input end is equipotential with the second sensing signal isolation output end, the first sensing signal isolation first input end is connected with the thirteenth power supply anode between the first sensing signal isolation output end and the first sensing signal isolation output end, the first sensing signal isolation second input end is connected with the thirteenth power supply cathode between the first sensing signal isolation output end and the first sensing signal isolation output end, the second sensing signal isolation first input end is connected with the fourteenth power supply anode between the second sensing signal isolation second input end and the second sensing signal isolation output end, the resistance R is connected with the fourteenth power supply cathode between the second sensing signal isolation second input end and the second sensing signal isolation output end, and the resistance R is₁₂One end of the resistor is isolated from the first sensing signal and is equipotential with the second input end, the other end of the resistor is connected with a twenty-fifth ground source, and a resistor R₁₃One end of the resistor is isolated from the second induction signal by the second input end and is at the same potential, the other end of the resistor is connected with a twenty-fifth ground source, and a resistor R₁₀One end of the resistor is isolated from the first sensing signal and is at the same potential as the second input end, and the resistor R₁₁One end of the first induction signal protection circuit is isolated from the second input end by the first induction signal, the other end of the first induction signal protection circuit is isolated from the second input end by the second induction signal, the other end of the first induction signal protection circuit is connected with the twenty-sixth grounding source, one end of the second induction signal protection circuit is isolated from the second input end by the second induction signal, and the other end of the second induction signal protection circuit is connected with the twenty-seventh grounding source.

Compared with the prior art, the beneficial effects of the utility model reside in that:

the utility model discloses measurement technology research and development adopts AD + DA + FPGA's mode research and development, uses based on FPGA application technique and embedded technique the utility model discloses the measurement card can connect the LVDT and the RVDT sensor of 4/5/6 lines and measure, can be used to the test measurement of LVDT/RVDT system, in the test of aircraft system, through the measurement to a plurality of LVDT and RVDT sensor, detects the mechanical motion of aircraft part.

The utility model can be used in EP-H5605.

Description of the terms

LVDT sensor-LVDT, Linear Variable Differential transducer, is an abbreviation for Linear Variable Differential Transformer and belongs to the Linear displacement sensor.

RVDT sensor-RVDT, Rotary Variable Differential transducer, is an abbreviation for Rotary Variable Differential Transformer, belonging to angular displacement sensors.

AD-AD is Analog-to-Digital.

DA-DA is Digital-to-Analog.

ADC-ADC is an Analog-to-Digital Converter.

DAC-DAC, i.e., Digital-to-Analog Converter, an exponential-Analog Converter.

Drawings

FIG. 1 is a block diagram of the measurement principle of the present invention;

fig. 2 is a block diagram of a reference circuit voltage module of the present invention;

fig. 3 is a circuit diagram of the reference circuit voltage module of the present invention;

fig. 4 is a block diagram of an excitation signal generating circuit module of the present invention;

fig. 5 is a circuit diagram of the excitation signal generating circuit module of the present invention;

fig. 6 is a block diagram of the sensing signal acquisition circuit of the present invention;

fig. 7 is a circuit diagram of the sensing signal collecting circuit module of the present invention;

fig. 8 is a schematic diagram of the external wiring mode of the measurement card of the present invention.

Detailed Description

The present invention will be further explained with reference to the accompanying drawings.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "longitudinal", "lateral", "horizontal", "inner", "outer", "front", "rear", "top", "bottom", and the like indicate the position or positional relationship based on the position or positional relationship shown in the drawings, or the position or positional relationship which is usually placed when the product of the present invention is used, and the terms are only for convenience of description of the present invention and simplifying the description, but do not indicate or imply that the device or element to which the term refers must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be further noted that, unless otherwise explicitly specified or limited, the terms "disposed," "opened," "mounted," "connected," and "connected" are to be construed broadly, e.g., as either a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example 1

Referring to fig. 1, the LVDT/RVDT sensor measuring card includes an excitation signal generating circuit module 3, an ADC module 7, a reference circuit voltage module 6, a control module 1, a DAC module 2, and a sensing signal collecting circuit module 5, where the control module 1 is connected to the ADC module 7 and the DAC module 2, the reference circuit voltage module 6 is connected to the ADC module 7 and the DAC module 2, the sensing signal collecting circuit module 5 is connected to the ADC module 7, and the excitation signal generating circuit module 3 is connected to the DAC module 2.

The control module 1 generates a sinusoidal parameter of an excitation signal and outputs the generated sinusoidal parameter of the excitation signal to the DAC module 2, the DAC module 2 outputs a sinusoidal signal, and the sinusoidal signal forms a differential sinusoidal signal through the excitation signal generation circuit module 3 and is input to a primary side of the LVDT/RVDT sensor 4; the secondary side of the LVDT/RVDT sensor 4 senses, the sensing signal acquisition circuit module 5 senses, acquires and converts the sensing signal into a positive end signal, then inputs the positive end signal into the ADC module 7 for analog-to-digital conversion, and then inputs the positive end signal into the control module 1, and the reference circuit voltage module 8 generates reference voltage and respectively inputs the reference voltage into the ADC module 7 and the DAC module 2.

It should be further noted that, in the present invention, the control module 1 is an FPGA controller.

Generation of the excitation signal: firstly, an NCO module is built in the FPGA controller to generate sine data with adjustable frequency. And secondly, multiplying the sine data by the excitation amplitude by using a multiplier to obtain sine data with adjustable amplitude. And thirdly, the sine data is converted into sine signals through the DAC module 2 and is output as records of adjustable frequency and amplitude.

LVDT/RVDT sensor 5 measures: collecting excitation signal and output signal of LVDT/RVDT sensor 4. Secondly, the FPGA controller respectively calculates period effective values and judges the phase relation of the signals. And thirdly, the FPGA controller calculates the displacement or angle measured by the LVDT/RVDT sensor 4 after acquiring the period effective value, and determines the direction of the displacement or angle according to the phase relation.

It should be further noted that, in the present invention, the DAC module 2 preferably includes two DACs 8831, namely a first DAC8831 and a second DAC 8831.

It should be further noted that, in the present invention, the ADC module 7 is preferably AD 7768-8.

The utility model discloses a control module 1 changes the measurement mode of ADC and carries out the four/five/six line system and measure to convert the signal into the recognizable signal of control module 1, carry out the analysis by control module 1 to data.

Referring to fig. 2 and 3, the reference circuit voltage module of the LVDT/RVDT sensor measurement card includes a voltage reference chip 11, a first reference circuit emitter follower circuit module 12 and a second reference circuit emitter follower circuit module 13, wherein the first reference circuit emitter follower circuit module 12 and the second reference circuit emitter follower circuit module 13 are connected with each other at one end and then connected with the voltage reference chip 11, the other end of the first reference circuit emitter follower circuit module 12 is connected with the ADC module, and the other end of the second reference circuit emitter follower circuit module 13 is connected with the DAC module.

The reference circuit voltage module generates a reference voltage through the voltage reference chip 11, and provides the reference voltage for the ADC module 7 and the DAC module 2 respectively according to the isolation of the first reference circuit emitter follower circuit module 12 and the second reference circuit emitter follower circuit module 13.

It should be further noted that, in the present invention, the voltage reference chip 11 is preferably an ADR421, the first reference circuit emitter follower circuit module 12 is preferably an amplifier AD8031ART, and the second reference circuit emitter follower circuit module 13 is preferably an amplifier AD8031 ART.

It should be further noted that, in the present invention, the reference circuit voltage module of the LVDT/RVDT sensor card further includes a non-polar capacitor C₁Non-polar capacitor C₂Non-polar capacitor C₃Non-polar capacitor C₄Non-polar capacitor C₅Non-polar capacitor C₆Non-polar capacitor C₇Non-polar capacitor C₈Current limiting resistor R₁The first power supply positive electrode, the second power supply positive electrode, the third power supply positive electrode, the first ground source, the second ground source connection, the third ground source, the fourth ground source, the fifth ground source and the sixth ground source; the voltage reference chip 11 is provided with a first pin of the voltage reference chip, a second pin of the voltage reference chip, a third pin of the voltage reference chip, a fourth pin of the voltage reference chip, a fifth pin of the voltage reference chip, a sixth pin of the voltage reference chip, a seventh pin of the voltage reference chip and an eighth pin of the voltage reference chip; the first reference circuit emitter follower circuit module 12 is provided with a first pin of the first reference circuit emitter follower circuit module, a second pin of the first reference circuit emitter follower circuit module, a third pin of the first reference circuit emitter follower circuit module, a fourth pin of the first reference circuit emitter follower circuit module and a fifth pin of the first reference circuit emitter follower circuit module; the second reference circuit emitter follower circuit module 13 is provided with a first pin of the second reference circuit emitter follower circuit module, a second pin of the second reference circuit emitter follower circuit module, and a second reference circuitA third pin of the emitter follower circuit module, a fourth pin of the second reference circuit emitter follower circuit module and a fifth pin of the second reference circuit emitter follower circuit module; non-polar capacitor C₁And a non-polar capacitor C₂After parallel connection, one end of the voltage reference chip is connected with the positive electrode of the first power supply, the other end of the voltage reference chip is connected with the first grounding source, the second pin of the voltage reference chip is connected with the positive electrode of the voltage of the first power supply, the fourth pin of the voltage reference chip is connected with the first grounding source, and the non-polar capacitor C₃Non-polar capacitor C₄One end of the resistor is connected with a current-limiting resistor R in parallel₁Connected to a second ground source, and a current limiting resistor R₁The other end of the first reference circuit emitter follower circuit module is connected with a sixth pin of the voltage reference chip, and a third pin of the first reference circuit emitter follower circuit module is connected with a third pin of the second reference circuit emitter follower circuit module and then connected with a non-polar capacitor C in parallel₃Non-polar capacitor C₄The second pin of the first reference circuit emitter follower circuit module is connected with a third grounding source, the second pin of the second reference circuit emitter follower circuit module is connected with a fourth grounding source, the fifth pin of the first reference circuit emitter follower circuit module is connected with the positive electrode of a second power supply, the fifth pin of the second reference circuit emitter follower circuit module is connected with the positive electrode of a third power supply, and a non-polar capacitor C is arranged between the fifth pin of the second reference circuit emitter follower circuit module and the positive electrode of the third power supply₅And a non-polar capacitor C₆After being connected in parallel, one end of the first reference circuit emitter follower circuit module is connected with a fifth grounding source, the other end of the first reference circuit emitter follower circuit module is equipotential with a fourth pin of the first reference circuit emitter follower circuit module, the first pin of the first reference circuit emitter follower circuit module is equipotential with the fourth pin of the first reference circuit emitter follower circuit module, and a non-polar capacitor C₇And a non-polar capacitor C₈After the parallel connection, one end of the second reference circuit emitter follower circuit module is connected with a sixth grounding source, the other end of the second reference circuit emitter follower circuit module is equal in potential to a fourth pin of the second reference circuit emitter follower circuit module, and the first pin of the second reference circuit emitter follower circuit module is equal in potential to the fourth pin of the second reference circuit emitter follower circuit module.

Referring to fig. 4 and 5, an excitation signal generation circuit module of an LVDT/RVDT sensor measurement card includes a first DAC adaptive amplifier, a first excitation signal generation power amplifier, a first excitation signal generation emitter follower amplifier, a first excitation signal generation protection circuit, a second DAC adaptive amplifier, a second excitation signal generation power amplifier, a second excitation signal generation emitter follower amplifier, and a second excitation signal generation protection circuit, wherein the first DAC adaptive amplifier is respectively connected with the first DAC8831 and the first excitation signal generation power amplifier, the first excitation signal generation emitter follower amplifier is respectively connected with the first excitation signal generation protection circuit and the first excitation signal generation power amplifier, the second DAC adaptive amplifier is connected with the second DAC8831 and the second excitation signal generation power amplifier, and the second excitation signal generation emitter follower amplifier is respectively connected with the second excitation signal generation protection circuit and the second excitation signal generation power amplifier And (6) connecting.

It should be further noted that, in the present invention, the first DAC adaptive amplifier is OPA2196ID, the second DAC adaptive amplifier is OPA2196ID, the first driving signal generation power amplifier is PA2196ID, the second driving signal generation power amplifier is PA2196ID, the first driving signal generation emitter follower amplifier is PA2196ID, and the second driving signal generation emitter follower amplifier is PA2196 ID.

It should be further noted that, in the present invention, the first excitation signal generation protection circuit is a bidirectional breakdown diode D₁The second excitation signal generation protection circuit is a bidirectional breakdown diode D₂。

It should be further noted that, in the present invention, the LVDT/RVDT sensor measuring card further includes a first inductor L₁A first inductor L₂Resistance R₄Resistance R₅Resistance R₆Resistance R₇Current limiting resistor R₂Current limiting resistor R₃Resistance R₈Resistance R₉Non-polar capacitor C₉Non-polar capacitor C₁₀Non-polar capacitor C₁₇Non-polar capacitor C₁₈Non-polar capacitor C₁₁Non-polar capacitor C₁₆And an electrolytic capacitor C₁₂And an electrolytic capacitor C₁₅And an electrolytic capacitor C₁₃And an electrolytic capacitor C₁₄A seventh ground source, an eighth ground sourceA ninth ground source, a tenth ground source, an eleventh ground source, a twelfth ground source, a thirteenth ground source, a fourteenth ground source, a fifteenth ground source, a sixteenth ground source, a seventeenth ground source, an eighteenth ground source, a nineteenth ground source, a twentieth ground source, a twenty-first ground source, a twenty-second ground source, a fourth power source, a fifth power source, a sixth power source, a seventh power source, an eighth power source, a ninth power source, a tenth power source, and an eleventh power source; the first DAC8831 is provided with a first DAC first pin, a first DAC second pin, a first DAC third pin, a first DAC fourth pin, a first DAC fifth pin, a first DAC sixth pin, a first DAC seventh pin, a first DAC eighth pin, a first DAC ninth pin, a first DAC tenth pin, a first DAC eleventh pin, a first DAC twelfth pin, a first DAC thirteenth pin and a first DAC fourteenth pin; the second DAC8831 is provided with a first DAC first pin, a second DAC second pin, a second DAC third pin, a second DAC fourth pin, a second DAC fifth pin, a second DAC sixth pin, a second DAC seventh pin, a second DAC eighth pin, a second DAC ninth pin, a second DAC tenth pin, a second DAC eleventh pin, a second DAC twelfth pin, a second DAC thirteenth pin and a second DAC fourteenth pin; the first DAC adaptive amplifier is provided with a first DAC adaptive first input end, a first DAC adaptive second input end and a first DAC adaptive output end, and the second DAC adaptive amplifier is provided with a second DAC adaptive first input end, a second DAC adaptive second input end and a second DAC adaptive first output end; the first excitation signal generation power amplifier is provided with a first power amplification first input end, a first power amplification second input end and a first power amplification output end, and the second excitation signal generation power amplifier is provided with a second power amplification first input end, a second power amplification second input end and a second power amplification output end; the first driving signal generation emitter follower amplifier is provided with a first emitter follower first input end, a first emitter follower second input end and a first emitter follower output end, and the second driving signal generation emitter follower amplifier is provided with a second emitter follower first input end, a second emitter follower second input end and a second emitter follower output end; first DAC first leadPin connected with the adaptive output end of the first DAC, and the second pin of the first DAC connected with the first inductor L₁Connected, a first inductor L₁The other end of the capacitor is equal to the second input end adapted to the first DAC, and the capacitor C is non-polar₉One end of the first DAC is matched with the second input end, the other end of the first DAC is connected with a seventh ground source, the seventh ground source is also connected with a third pin of the first DAC and a fourth pin of the first DAC, and a non-polar capacitor C is arranged between the first DAC and the fourth pin of the first DAC₁₀One end of the first DAC is connected with the eighth ground source, the other end of the first DAC is in equal potential with the fifth pin of the first DAC and the sixth pin of the first DAC, the eleventh pin of the first DAC and the twelfth pin of the first DAC are connected with the ninth ground source, the thirteenth pin of the first DAC is connected with the adaptive first input end of the first DAC, and the non-polar capacitor C is connected with the adaptive first input end of the first DAC₁₁One end of the first DAC is connected with a tenth ground source, the other end of the first DAC is connected with the positive electrode of a fourth power supply, a fourteenth pin of the first DAC is connected with the positive electrode of the fourth power supply, the adaptive output end of the first DAC is connected with the positive electrode of the sixth power supply between the two ends of the adaptive first input end of the first DAC, and the adaptive output end of the first DAC is connected with the negative electrode of the sixth power supply between the two ends of the adaptive second input end of the first DAC; electrolytic capacitor C₁₂One end of the resistor is connected with the fifteenth grounding source, the other end of the resistor is equal to the first power amplification first input end in potential, and the resistor R₄One end of the resistor R is equal to the adaptive output end of the first DAC, the other end of the resistor R is equal to the first power amplification first input end₆One end of the first power amplification output end is equipotential with the first power amplification first input end, the other end of the first power amplification output end is equipotential with the first power amplification second input end, the first power amplification second input end is connected with a sixteenth ground source, the first power amplification output end is connected with the positive electrode of an eighth power supply between the two ends of the first power amplification first input end, and the first power amplification output end is connected with the negative electrode of the eighth power supply between the two ends of the first power amplification second input end; electrolytic capacitor C₁₃One end of the current limiting resistor is connected with the nineteenth grounding source, the other end of the current limiting resistor is equal to the potential of the first emitter along with the second input end₂One end of the first emitter follower output end is equal to the first power amplification output end, the other end of the first emitter follower output end is equal to the second emitter follower input end, the first emitter follower output end is equal to the first emitter follower input end, the first emitter follower output end and the first emitter follower input end are connected with the positive electrode of a tenth power supply,the first emitter following output end and the two ends of the first emitter following second input end are connected with the negative electrode of a tenth power supply; resistance R₈One end of the first excitation signal generation protection circuit is equal to the potential of the first emitter following output end, one end of the first excitation signal generation protection circuit is connected with the twenty-first grounding source, and the other end of the first excitation signal generation protection circuit is connected with the resistor R₈Equipotential; the first pin of the second DAC is connected with the first output end of the second DAC, and the second pin of the second DAC is connected with the second inductor L₂Connected, a second inductor L₂The other end of the capacitor is equal to the second input end of the second DAC in potential, and the capacitor C is non-polar₁₇One end of the non-polar capacitor C is matched with the second input end of the second DAC, the other end of the non-polar capacitor C is connected with an eleventh ground source, the eleventh ground source is also connected with a third pin of the second DAC and a fourth pin of the second DAC, and the non-polar capacitor C₁₈One end of the first DAC is connected with a twelfth ground source, the other end of the first DAC is equal in potential with a fifth pin of the second DAC and a sixth pin of the second DAC, an eleventh pin of the second DAC and a twelfth pin of the second DAC are connected with a thirteenth ground source, a thirteenth pin of the second DAC is connected with a first adaptive DAC input end, and a non-polar capacitor C is connected with the first adaptive DAC input end₁₆One end of the first DAC is connected with a fifth ground source, the other end of the first DAC is connected with a fifth power supply positive electrode, a fourteenth pin of the second DAC is connected with the fifth power supply positive electrode, the adaptive output end of the second DAC is connected with the seventh power supply positive electrode between the two ends of the adaptive first input end of the second DAC, and the adaptive output end of the second DAC is connected with the seventh power supply negative electrode between the two ends of the adaptive second input end of the second DAC; electrolytic capacitor C₁₅One end of the resistor is connected with the seventeenth grounding source, the other end of the resistor is equal to the potential of the first input end of the second power amplifier, and the resistor R₅One end of the resistor R is equal to the adaptive output end of the second DAC, the other end of the resistor R is equal to the first power amplification input end of the second DAC, and the other end of the resistor R is equal to the adaptive output end of the second DAC₇One end of the first power amplification output end is equipotential with the first input end of the first power amplification, the other end of the first power amplification output end is equipotential with the second input end of the second power amplification, the second input end of the first power amplification is connected with the eighteenth ground source, the second power amplification output end is connected with the positive electrode of the ninth power supply between the two ends of the first input end of the second power amplification, and the second power amplification output end is connected with the negative electrode of the ninth power supply between the two ends of the second input end of the second power amplification; electrolytic capacitor C₁₄One end of the first transistor is connected to the twentieth ground source, and the other end of the first transistor is connected to the second emitter and follows the second inputInput end equipotential, current limiting resistor R₃One end of the second emitter follower output end is equipotential with the second power amplification output end, the other end of the second emitter follower output end is equipotential with the second emitter follower input end, the second emitter follower output end is connected with the eleventh power supply anode between the second emitter follower output end and the two ends of the second emitter follower input end, and the second emitter follower output end is connected with the eleventh power supply cathode between the second emitter follower output end and the two ends of the second emitter follower input end; resistance R₉One end of the first excitation signal generation protection circuit is equal to the potential of the first emitter follower output end, one end of the first excitation signal generation protection circuit is connected with the twenty-second ground source, and the other end of the first excitation signal generation protection circuit is equal to the potential of the resistor R9. The excitation signal from the DAC module 2 is converted into a bipolar sinusoidal excitation signal through a DAC adaptive amplifier, amplified by 4 times through a power amplification circuit, and output of the excitation signal is realized through emitter following.

Referring to fig. 6 and 7, a sensing signal collecting circuit module of an LVDT/RVDT sensor measuring card includes an ADC adapter amplifier, a first sensing signal isolation amplifier, a first sensing signal protection circuit, a second sensing signal isolation amplifier and a second sensing signal protection circuit, where the ADC adapter amplifier is connected to the ADC module 7, the first sensing signal isolation amplifier and the second sensing signal isolation amplifier are respectively connected to the ADC adapter amplifier, the first sensing signal protection circuit is connected to the first sensing signal isolation amplifier, and the second sensing signal protection circuit is connected to the second sensing signal isolation amplifier.

It should be further noted that, in the present invention, the first sensing signal protection circuit is a bidirectional breakdown diode D₃The second induction signal protection circuit is a bidirectional breakdown diode D₄。

It should be further noted that, in the present invention, the ADC adapter amplifier is preferably ADA4940, the first sensing signal isolation amplifier is preferably OPA2196ID, and the second sensing signal isolation amplifier is preferably OPA2196I D.

It should be further noted that, in the present invention, the LVDT/RVDT sensor measuring card further includes a non-polar capacitor C₁₉Non-polar capacitor C₂₀Non-polar electricityContainer C₂₁Resistance R₁₈Resistance R₁₄Resistance R₁₆Resistance R₁₇Resistance R₁₂Resistance R₁₃Resistance R₁₀Resistance R₁₁A twenty-third ground source, a twenty-fourth ground source, a twenty-fifth ground source, a twenty-sixth ground source, a twenty-seventh ground source, a twelfth power source, a thirteenth power source and a fourteenth power source; the ADC adaptive amplifier is provided with an ADC first pin, an ADC second pin, an ADC third pin, an ADC fourth pin, an ADC fifth pin, an ADC sixth pin, an ADC seventh pin and an ADC eighth pin; the first induction signal isolation amplifier is provided with a first induction signal isolation first input end, a first induction signal isolation second input end and a first induction signal isolation output end, and the second induction signal isolation amplifier is provided with a second induction signal isolation first input end, a second induction signal isolation second input end and a second induction signal isolation output end; resistance R₁₈One end of the resistor is equal to the potential of the eighth pin of the ADC, the other end of the resistor is equal to the potential of the fifth pin of the ADC, and the resistor R₁₉One end of the resistor is equal to the potential of the first pin of the ADC, the other end of the resistor is equal to the potential of the fourth pin of the ADC, and the resistor R₁₄One end of the capacitor is equal to the potential of the fifth pin of the ADC, and the other end of the capacitor is connected with a non-polar capacitor C₁₉One end is equipotential, resistance R₁₅One end of the capacitor is equal to the potential of the fourth pin of the ADC, and the other end of the capacitor is connected with a non-polar capacitor C₂₀One end of the capacitor is equipotential and has no polarity₁₉And a non-polar capacitor C₂₀The other ends of the two capacitors are connected with a twenty-third ground source and a non-polar capacitor C₂₁One terminal and resistor R₁₄One end far away from the fifth pin of the ADC is equipotential, and the other end is connected with the resistor R₁₅The end far away from the fourth pin of the ADC has the same potential, the sixth pin of the ADC is connected with a twenty-fourth ground source, the third pin of the ADC is connected with the anode of a twelfth power supply, and a resistor R₁₆One end of the resistor is equipotential with the eighth pin of the ADC, the other end of the resistor is equipotential with the first induction signal isolation output end, and the resistor R₁₇One end of the first sensing signal is equipotential with the first pin of the ADC, the other end of the first sensing signal is equipotential with the second sensing signal isolation output end, the first sensing signal isolation first input end is equipotential with the first sensing signal isolation output end, and the second sensing signal isolation first input end is equipotential with the second sensing signalThe isolation output end is equipotential, the first induction signal isolation first input end is connected with the positive electrode of the thirteenth power supply between the first induction signal isolation output end, the first induction signal isolation second input end is connected with the negative electrode of the thirteenth power supply between the first induction signal isolation output end and the first induction signal isolation second input end, the second induction signal isolation first input end is connected with the positive electrode of the fourteenth power supply between the second induction signal isolation output end and the fourteenth power supply between the second induction signal isolation second input end and the second induction signal isolation output end, the resistor R is connected with the negative electrode of the fourteenth power supply, and the resistor R is connected with the positive electrode of the thirteenth₁₂One end of the resistor is isolated from the first sensing signal and is equipotential with the second input end, the other end of the resistor is connected with a twenty-fifth ground source, and a resistor R₁₃One end of the resistor is isolated from the second induction signal by the second input end and is at the same potential, the other end of the resistor is connected with a twenty-fifth ground source, and a resistor R₁₀One end of the resistor is isolated from the first sensing signal and is at the same potential as the second input end, and the resistor R₁₁One end of the first induction signal protection circuit is isolated from the second input end by the first induction signal, the other end of the first induction signal protection circuit is isolated from the second input end by the second induction signal, the other end of the first induction signal protection circuit is connected with the twenty-sixth grounding source, one end of the second induction signal protection circuit is isolated from the second input end by the second induction signal, and the other end of the second induction signal protection circuit is connected with the twenty-seventh grounding source.

The sensing signal acquisition circuit module attenuates the input sensing signal to 1/4 through the voltage division circuit, and then the impedance isolation is realized by the first sensing signal isolation amplifier and the second sensing signal isolation amplifier, the isolated signal is input into the ADC adapter amplifier, and the converted signal is input into the ADC module 7.

As shown in fig. 8, the measuring card of the present invention can be connected to 4/5/6 line LVDT and RVDT sensors for measurement.

A-and B-are suspended during four-wire system measurement; during the five-wire system measurement, the A-and the B-are short-circuited and connected with a CT end of a user; and respectively connecting the six-wire system according to the definition of the cable during measurement.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An LVDT/RVDT sensor measurement card comprising a control module, characterized in that: the LVDT/RVDT sensor measuring card also comprises an excitation signal generating circuit module, an ADC module, a reference circuit voltage module, a DAC module and an induction signal collecting circuit module, wherein the control module is respectively connected with the ADC module and the DAC module; the control module generates a sinusoidal parameter of the excitation signal and outputs the generated sinusoidal parameter of the excitation signal to the DAC module, the DAC module outputs a sinusoidal signal, and the sinusoidal signal forms a differential sinusoidal signal through the excitation signal generation circuit module and is input to the primary side of the LVDT/RVDT sensor to be detected; the secondary side of the LVDT/RVDT sensor to be tested forms sensing signals, the sensing signals are collected and converted into positive end signals by the sensing signal collection circuit module and then input into the ADC module for analog-to-digital conversion and then input into the control module, and the reference circuit voltage module generates reference voltages and respectively inputs the reference voltages into the ADC module and the DAC module.

2. The LVDT/RVDT sensor measurement card according to claim 1, wherein: the control module is an FPGA controller.

3. The LVDT/RVDT sensor measurement card according to claim 1, wherein: the DAC modules are two DACs 8831, the two DACs 8831 are a first DAC8831 and a second DAC8831, respectively, and the ADC modules are AD 7768-8.

4. An LVDT/RVDT sensor measurement card according to any one of claims 1 to 3, characterized in that: the reference circuit voltage module comprises a voltage reference chip, a first reference circuit emitter follower circuit module and a second reference circuit emitter follower circuit module, wherein one end of each of the first reference circuit emitter follower circuit module and the second reference circuit emitter follower circuit module is connected with the voltage reference chip, the other end of the first reference circuit emitter follower circuit module is connected with the ADC module, and the other end of the second reference circuit emitter follower circuit module is connected with the DAC module.

5. The LVDT/RVDT sensor measurement card according to claim 4, characterized in that: the LVDT/RVDT sensor measuring card also comprises a non-polar capacitor C₁Non-polar capacitor C₂Non-polar capacitor C₃Non-polar capacitor C₄Non-polar capacitor C₅Non-polar capacitor C₆Non-polar capacitor C₇Non-polar capacitor C₈Current limiting resistor R₁The first power supply positive electrode, the second power supply positive electrode, the third power supply positive electrode, the first ground source, the second ground source connection, the third ground source, the fourth ground source, the fifth ground source and the sixth ground source; the voltage reference chip is provided with a first pin of the voltage reference chip, a second pin of the voltage reference chip, a third pin of the voltage reference chip, a fourth pin of the voltage reference chip, a fifth pin of the voltage reference chip, a sixth pin of the voltage reference chip, a seventh pin of the voltage reference chip and an eighth pin of the voltage reference chip; the first reference circuit emitter follower circuit module is provided with a first pin of the first reference circuit emitter follower circuit module, a second pin of the first reference circuit emitter follower circuit module, a third pin of the first reference circuit emitter follower circuit module, a fourth pin of the first reference circuit emitter follower circuit module and a fifth pin of the first reference circuit emitter follower circuit module; the second reference circuit emitter follower circuit module is provided with a first pin of the second reference circuit emitter follower circuit module, a second pin of the second reference circuit emitter follower circuit module, a third pin of the second reference circuit emitter follower circuit module, a fourth pin of the second reference circuit emitter follower circuit module and a fifth pin of the second reference circuit emitter follower circuit module; non-polar capacitor C₁And a non-polar capacitor C₂After parallel connection, one end of the voltage reference chip is connected with the positive electrode of the first power supply, the other end of the voltage reference chip is connected with the first grounding source, and the second pin of the voltage reference chip is connected with the first pinThe positive pole of the power supply voltage is connected, the fourth pin of the voltage reference chip is connected with the first grounding source, and the non-polar capacitor C₃Non-polar capacitor C₄One end of the resistor is connected with a current-limiting resistor R in parallel₁Connected to a second ground source, and a current limiting resistor R₁The other end of the first reference circuit emitter follower circuit module is connected with a sixth pin of the voltage reference chip, and a third pin of the first reference circuit emitter follower circuit module is connected with a third pin of the second reference circuit emitter follower circuit module and then connected with a non-polar capacitor C in parallel₃Non-polar capacitor C₄The second pin of the first reference circuit emitter follower circuit module is connected with a third grounding source, the second pin of the second reference circuit emitter follower circuit module is connected with a fourth grounding source, the fifth pin of the first reference circuit emitter follower circuit module is connected with the positive electrode of a second power supply, the fifth pin of the second reference circuit emitter follower circuit module is connected with the positive electrode of a third power supply, and a non-polar capacitor C is arranged between the fifth pin of the second reference circuit emitter follower circuit module and the positive electrode of the third power supply₅And a non-polar capacitor C₆After being connected in parallel, one end of the first reference circuit emitter follower circuit module is connected with a fifth grounding source, the other end of the first reference circuit emitter follower circuit module is equipotential with a fourth pin of the first reference circuit emitter follower circuit module, the first pin of the first reference circuit emitter follower circuit module is equipotential with the fourth pin of the first reference circuit emitter follower circuit module, and a non-polar capacitor C₇And a non-polar capacitor C₈After the parallel connection, one end of the second reference circuit emitter follower circuit module is connected with a sixth grounding source, the other end of the second reference circuit emitter follower circuit module is equal in potential to a fourth pin of the second reference circuit emitter follower circuit module, and the first pin of the second reference circuit emitter follower circuit module is equal in potential to the fourth pin of the second reference circuit emitter follower circuit module.

6. The LVDT/RVDT sensor measurement card according to claim 3, wherein: the driving signal generation circuit module comprises a first DAC adaptive amplifier, a first driving signal generation power amplifier, a first driving signal generation emitter follower amplifier, a second DAC adaptive amplifier, a second driving signal generation power amplifier and a second driving signal generation emitter follower amplifier, wherein the first DAC adaptive amplifier is respectively connected with the first DAC8831 and the first driving signal generation power amplifier, the first driving signal generation emitter follower amplifier is connected with the first driving signal generation power amplifier, the second DAC adaptive amplifier is connected with the second DAC8831 and the second driving signal generation power amplifier, and the second driving signal generation emitter follower amplifier is connected with the second driving signal generation power amplifier.

7. The LVDT/RVDT sensor measurement card according to claim 6, wherein: the driving signal generation circuit module further comprises a first driving signal generation protection circuit and a second driving signal generation protection circuit, wherein the first driving signal generation emitter following amplifier is connected with the first driving signal generation protection circuit, and the second driving signal generation protection circuit is connected with the second driving signal generation emitter following amplifier.

8. The LVDT/RVDT sensor measurement card of claim 7, wherein: the LVDT/RVDT sensor measurement card also comprises a first inductor L₁A first inductor L₂Resistance R₄Resistance R₅Resistance R₆Resistance R₇Current limiting resistor R₂Current limiting resistor R₃Resistance R₈Resistance R₉Non-polar capacitor C₉Non-polar capacitor C₁₀Non-polar capacitor C₁₇Non-polar capacitor C₁₈Non-polar capacitor C₁₁Non-polar capacitor C₁₆And an electrolytic capacitor C₁₂And an electrolytic capacitor C₁₅And an electrolytic capacitor C₁₃And an electrolytic capacitor C₁₄A seventh ground source, an eighth ground source, a ninth ground source, a tenth ground source, an eleventh ground source, a twelfth ground source, a thirteenth ground source, a fourteenth ground source, a fifteenth ground source, a sixteenth ground source, a seventeenth ground source, an eighteenth ground source, a nineteenth ground source, a twentieth ground source, a twenty-first ground source, a twenty-second ground source, a fourth power source, a fifth power source, a sixth power source, a seventh power source, an eighth power source, a ninth power source, a tenth power source, and an eleventh power source; the first DAC8831 is provided with a first DAC first pin, a first DAC second pinA third DAC pin, a fourth DAC pin, a fifth DAC pin, a sixth DAC pin, a seventh DAC pin, an eighth DAC pin, a ninth DAC pin, a tenth DAC pin, an eleventh DAC pin, a twelfth DAC pin, a thirteenth DAC pin and a fourteenth DAC pin; the second DAC8831 is provided with a first DAC first pin, a second DAC second pin, a second DAC third pin, a second DAC fourth pin, a second DAC fifth pin, a second DAC sixth pin, a second DAC seventh pin, a second DAC eighth pin, a second DAC ninth pin, a second DAC tenth pin, a second DAC eleventh pin, a second DAC twelfth pin, a second DAC thirteenth pin and a second DAC fourteenth pin; the first DAC adaptive amplifier is provided with a first DAC adaptive first input end, a first DAC adaptive second input end and a first DAC adaptive output end, and the second DAC adaptive amplifier is provided with a second DAC adaptive first input end, a second DAC adaptive second input end and a second DAC adaptive first output end; the first excitation signal generation power amplifier is provided with a first power amplification first input end, a first power amplification second input end and a first power amplification output end, and the second excitation signal generation power amplifier is provided with a second power amplification first input end, a second power amplification second input end and a second power amplification output end; the first driving signal generation emitter follower amplifier is provided with a first emitter follower first input end, a first emitter follower second input end and a first emitter follower output end, and the second driving signal generation emitter follower amplifier is provided with a second emitter follower first input end, a second emitter follower second input end and a second emitter follower output end; the first DAC first pin is connected with the first DAC adaptive output end, and the second DAC second pin is connected with the first inductor L₁Connected, a first inductor L₁The other end of the capacitor is equal to the second input end adapted to the first DAC, and the capacitor C is non-polar₉One end of the first DAC is matched with the second input end, the other end of the first DAC is connected with a seventh ground source, the seventh ground source is also connected with a third pin of the first DAC and a fourth pin of the first DAC, and a non-polar capacitor C is arranged between the first DAC and the fourth pin of the first DAC₁₀One end of the first DAC is connected with an eighth ground source, and the other end of the first DAC is equal in potential to the fifth pin and the sixth pin of the first DACThe eleventh pin of the DAC and the twelfth pin of the first DAC are connected with a ninth ground source, the thirteenth pin of the first DAC is connected with the first DAC adaptive first input end, and the non-polar capacitor C₁₁One end of the first DAC is connected with a tenth ground source, the other end of the first DAC is connected with the positive electrode of a fourth power supply, a fourteenth pin of the first DAC is connected with the positive electrode of the fourth power supply, the adaptive output end of the first DAC is connected with the positive electrode of the sixth power supply between the two ends of the adaptive first input end of the first DAC, and the adaptive output end of the first DAC is connected with the negative electrode of the sixth power supply between the two ends of the adaptive second input end of the first DAC; electrolytic capacitor C₁₂One end of the resistor is connected with the fifteenth grounding source, the other end of the resistor is equal to the first power amplification first input end in potential, and the resistor R₄One end of the resistor R is equal to the adaptive output end of the first DAC, the other end of the resistor R is equal to the first power amplification first input end₆One end of the first power amplification output end is equipotential with the first power amplification first input end, the other end of the first power amplification output end is equipotential with the first power amplification second input end, the first power amplification second input end is connected with a sixteenth ground source, the first power amplification output end is connected with the positive electrode of an eighth power supply between the two ends of the first power amplification first input end, and the first power amplification output end is connected with the negative electrode of the eighth power supply between the two ends of the first power amplification second input end; electrolytic capacitor C₁₃One end of the current limiting resistor is connected with the nineteenth grounding source, the other end of the current limiting resistor is equal to the potential of the first emitter along with the second input end₂One end of the first emitter follower output end is equipotential with the first power amplification output end, the other end of the first emitter follower output end is equipotential with the second input end of the first emitter follower, the first emitter follower output end is equipotential with the first input end of the first emitter follower, the first emitter follower output end is connected with the positive electrode of the tenth power supply between the first emitter follower output end and the two ends of the first emitter follower input end, and the first emitter follower output end is connected with the negative electrode of the tenth power supply between the first emitter follower output end and the two ends of the first emitter; resistance R₈One end of the first excitation signal generation protection circuit is equal to the potential of the first emitter following output end, one end of the first excitation signal generation protection circuit is connected with the twenty-first grounding source, and the other end of the first excitation signal generation protection circuit is connected with the resistor R₈Equipotential; the first pin of the second DAC is connected with the first output end of the second DAC, and the second pin of the second DAC is connected with the second inductor L₂Connected, a second inductor L₂The other end of the first DAC is in equal potential with the second input end matched with the second DAC and is electrodelessSex capacitor C₁₇One end of the non-polar capacitor C is matched with the second input end of the second DAC, the other end of the non-polar capacitor C is connected with an eleventh ground source, the eleventh ground source is also connected with a third pin of the second DAC and a fourth pin of the second DAC, and the non-polar capacitor C₁₈One end of the first DAC is connected with a twelfth ground source, the other end of the first DAC is equal in potential with a fifth pin of the second DAC and a sixth pin of the second DAC, an eleventh pin of the second DAC and a twelfth pin of the second DAC are connected with a thirteenth ground source, a thirteenth pin of the second DAC is connected with a first adaptive DAC input end, and a non-polar capacitor C is connected with the first adaptive DAC input end₁₆One end of the first DAC is connected with a fifth ground source, the other end of the first DAC is connected with a fifth power supply positive electrode, a fourteenth pin of the second DAC is connected with the fifth power supply positive electrode, the adaptive output end of the second DAC is connected with the seventh power supply positive electrode between the two ends of the adaptive first input end of the second DAC, and the adaptive output end of the second DAC is connected with the seventh power supply negative electrode between the two ends of the adaptive second input end of the second DAC; electrolytic capacitor C₁₅One end of the resistor is connected with the seventeenth grounding source, the other end of the resistor is equal to the potential of the first input end of the second power amplifier, and the resistor R₅One end of the resistor R is equal to the adaptive output end of the second DAC, the other end of the resistor R is equal to the first power amplification input end of the second DAC, and the other end of the resistor R is equal to the adaptive output end of the second DAC₇One end of the first power amplification output end is equipotential with the first input end of the first power amplification, the other end of the first power amplification output end is equipotential with the second input end of the second power amplification, the second input end of the first power amplification is connected with the eighteenth ground source, the second power amplification output end is connected with the positive electrode of the ninth power supply between the two ends of the first input end of the second power amplification, and the second power amplification output end is connected with the negative electrode of the ninth power supply between the two ends of the second input end of the second power amplification; electrolytic capacitor C₁₄One end of the current limiting resistor is connected with the twentieth ground source, the other end of the current limiting resistor is equal to the potential of the second emitter along with the second input end₃One end of the second emitter follower output end is equipotential with the second power amplification output end, the other end of the second emitter follower output end is equipotential with the second emitter follower input end, the second emitter follower output end is connected with the eleventh power supply anode between the second emitter follower output end and the two ends of the second emitter follower input end, and the second emitter follower output end is connected with the eleventh power supply cathode between the second emitter follower output end and the two ends of the second emitter follower input end; resistance R₉One terminal and the first emitter follower output terminal, etcOne end of the first excitation signal generation protection circuit is connected with the twenty-second ground source, and the other end of the first excitation signal generation protection circuit is connected with the resistor R₉And (3) equipotential.

9. An LVDT/RVDT sensor measurement card according to any one of claims 1 to 3, characterized in that: the sensing signal acquisition circuit module comprises an ADC (analog to digital converter) adapter amplifier, a first sensing signal isolation amplifier, a first sensing signal protection circuit, a second sensing signal isolation amplifier and a second sensing signal protection circuit, wherein the ADC adapter amplifier is connected with the ADC module, the first sensing signal isolation amplifier and the second sensing signal isolation amplifier are respectively connected with the ADC adapter amplifier, the first sensing signal protection circuit is connected with the first sensing signal isolation amplifier, and the second sensing signal protection circuit is connected with the second sensing signal isolation amplifier.

10. The LVDT/RVDT sensor measurement card of claim 9, wherein: the LVDT/RVDT sensor measuring card also comprises a non-polar capacitor C₁₉Non-polar capacitor C₂₀Non-polar capacitor C₂₁Resistance R₁₈Resistance R₁₄Resistance R₁₆Resistance R₁₇Resistance R₁₂Resistance R₁₃Resistance R₁₀Resistance R₁₁A twenty-third ground source, a twenty-fourth ground source, a twenty-fifth ground source, a twenty-sixth ground source, a twenty-seventh ground source, a twelfth power source and a thirteenth power source; the ADC adaptive amplifier is provided with an ADC first pin, an ADC second pin, an ADC third pin, an ADC fourth pin, an ADC fifth pin, an ADC sixth pin, an ADC seventh pin and an ADC eighth pin; the first induction signal isolation amplifier is provided with a first induction signal isolation first input end, a first induction signal isolation second input end and a first induction signal isolation output end, and the second induction signal isolation amplifier is provided with a second induction signal isolation first input end, a second induction signal isolation second input end and a second induction signal isolation output end; resistance R₁₈One end of the resistor is equal to the potential of the eighth pin of the ADC, the other end of the resistor is equal to the potential of the fifth pin of the ADC, and the resistor R₁₉One end of the resistor is equal to the potential of the first pin of the ADC, the other end of the resistor is equal to the potential of the fourth pin of the ADC, and the resistor R₁₄One end of the capacitor is equal to the potential of the fifth pin of the ADC, and the other end of the capacitor is connected with a non-polar capacitor C₁₉One end is equipotential, resistance R₁₅One end of the capacitor is equal to the potential of the fourth pin of the ADC, and the other end of the capacitor is connected with a non-polar capacitor C₂₀One end of the capacitor is equipotential and has no polarity₁₉And a non-polar capacitor C₂₀The other ends of the two capacitors are connected with a twenty-third ground source and a non-polar capacitor C₂₁One terminal and resistor R₁₄One end far away from the fifth pin of the ADC is equipotential, and the other end is connected with the resistor R₁₅The end far away from the fourth pin of the ADC has the same potential, the sixth pin of the ADC is connected with a twenty-fourth ground source, the third pin of the ADC is connected with the anode of a twelfth power supply, and a resistor R₁₆One end of the resistor is equipotential with the eighth pin of the ADC, the other end of the resistor is equipotential with the first induction signal isolation output end, and the resistor R₁₇One end is equipotential with the first pin of ADC, the other end is equipotential with the second sensing signal isolation output end, the first sensing signal isolation first input end is equipotential with the first sensing signal isolation output end, the second sensing signal isolation first input end is equipotential with the second sensing signal isolation output end, the first sensing signal isolation first input end is connected with the thirteenth power supply anode between the first sensing signal isolation output end and the first sensing signal isolation output end, the first sensing signal isolation second input end is connected with the thirteenth power supply cathode between the first sensing signal isolation output end and the first sensing signal isolation output end, the second sensing signal isolation first input end is connected with the fourteenth power supply anode between the second sensing signal isolation second input end and the second sensing signal isolation output end, the resistance R is connected with the fourteenth power supply cathode between the second sensing signal isolation second input end and the second sensing signal isolation output end, and the resistance R is₁₂One end of the resistor is isolated from the first sensing signal and is equipotential with the second input end, the other end of the resistor is connected with a twenty-fifth ground source, and a resistor R₁₃One end of the resistor is isolated from the second induction signal by the second input end and is at the same potential, the other end of the resistor is connected with a twenty-fifth ground source, and a resistor R₁₀One end of the resistor is isolated from the first sensing signal and is at the same potential as the second input end, and the resistor R₁₁One end of the first induction signal protection circuit is isolated from the second induction signal and has the same potential as the second input end, and the other end of the first induction signal protection circuit is isolated from the first induction signal and has the same potential as the second input endThe end of the second induction signal protection circuit is connected with the twenty-sixth grounding source, one end of the second induction signal protection circuit is equal in potential to the second induction signal isolation second input end, and the other end of the second induction signal protection circuit is connected with the twenty-seventh grounding source.