CN209859287U - Data acquisition system suitable for intelligent property - Google Patents
Data acquisition system suitable for intelligent property Download PDFInfo
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- CN209859287U CN209859287U CN201920675110.6U CN201920675110U CN209859287U CN 209859287 U CN209859287 U CN 209859287U CN 201920675110 U CN201920675110 U CN 201920675110U CN 209859287 U CN209859287 U CN 209859287U
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Abstract
The utility model discloses a data acquisition system suitable for intelligent property, including common mode suppression circuit and the protection circuit who is connected with first chip, common mode suppression circuit includes that one end is connected with the analog input end, the other end passes through the second resistance and connects in the first resistance of first chip pin PA10, parallelly connected third resistance and first stabiliser on the first resistance, the other end ground connection of third resistance and first stabiliser; and a first capacitor is connected in parallel to the second resistor, and the other end of the first capacitor is grounded. The beneficial effects of the utility model are mainly embodied in that: the system has a simple structure, has the functions of decentralized acquisition, monitoring and centralized management of resident information, is perfect and reliable in acquired information, high in accuracy, and capable of accurately displaying the information of three meters, saving time, manpower and material resources, improving the working efficiency and reducing the property cost.
Description
Technical Field
The utility model relates to an acquisition system particularly, especially relates to a data acquisition system suitable for intelligent property.
Background
At present, most residential districts in China are still in a low-level stage mainly managed by manpower, the development requirements of modern cities are seriously lagged, meter reading personnel need to read data from each household at regular intervals for three meters in the residential districts, after the expenses are settled, the data are requested by each household, the error is large, the statistical workload is large, and great inconvenience is brought to property management and users due to artificial errors.
SUMMERY OF THE UTILITY MODEL
The utility model aims at overcoming the not enough of prior art existence, provide a data acquisition system suitable for intelligent property.
The purpose of the utility model is realized through the following technical scheme:
a data acquisition system suitable for intelligent property comprises a common mode suppression circuit and a protection circuit which are connected with a first chip, wherein the common mode suppression circuit comprises a first resistor, one end of the first resistor is connected with an analog input end, the other end of the first resistor is connected with a first chip pin PA10 through a second resistor, a third resistor and a first voltage stabilizer are connected to the first resistor in parallel, and the third resistor and the other end of the first voltage stabilizer are grounded; a first capacitor is connected in parallel to the second resistor, and the other end of the first capacitor is grounded; the protection circuit comprises a first triode, an emitting electrode of the first triode is connected to the first chip pin PU10 through a fourth resistor, and a fifth resistor is connected in parallel to the fourth resistor and grounded; the base electrode of the first triode is grounded; the collector electrode of the first triode is respectively connected with the sixth resistor, the ground and the grid electrode of the NMOS tube, the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is connected with the power output through the motor; the pin VDD1, the pin VDD2, the pin VDD3 and the pin VDD4 of the first chip are connected with a power input end, and the pin VSS1, the pin VSS2, the pin VSS3, the pin VSS4 and the pin VSSA of the first chip are grounded.
Preferably, the first chip is connected to a conversion circuit, the conversion circuit includes a second chip, pin 2 of the second chip is connected to pin PA2 of the first chip, pin 3 of the second chip is connected to pin PA3 of the first chip, pin 4 of the second chip is connected to pin 5 of the second chip sequentially through a seventh resistor, a first potentiometer and a ninth resistor, and a slide pin on the first potentiometer is connected to pin 6 of the second chip; a pin 8 of the second chip is respectively connected with a pin 1 of a second potentiometer and a collector of a second triode, a pin 3 of the second potentiometer is respectively connected with a pin 2 of the second potentiometer and a ninth resistor, an emitter of the second triode is respectively connected with the other end of the ninth resistor and one end of a second voltage stabilizer, and a grid of the second triode is connected with the other end of the second voltage stabilizer through a tenth resistor; and a pin 10 of the second chip is connected with a power supply input end through a fourth capacitor, and a pin 11 of the second chip is connected with the power supply input end.
Preferably, the first chip is further connected to an oscillation circuit, the oscillation circuit includes a second capacitor having one end connected to the first chip pin OSSC-OUT/PD1 and the other end grounded, and a third capacitor having one end connected to the first chip pin OSSC-OUT/PD0 and the other end grounded, and a quartz crystal oscillator is further disposed between the third capacitor and the second capacitor.
Preferably, the pin NRST of the first chip is connected to an eleventh resistor and a fifth capacitor, respectively, and the other ends of the eleventh resistor and the fifth capacitor are grounded.
Preferably, the first chip is an At89S52 type linear power supply chip.
Preferably, the second chip is an ICL8083 type linear power supply chip.
The beneficial effects of the utility model are mainly embodied in that:
1. the system has a simple structure, has the functions of decentralized acquisition, monitoring and centralized management of resident information, is perfect and reliable in acquired information, high in accuracy, and capable of accurately displaying the information of three meters, saving time, manpower and material resources, improving the working efficiency and reducing the property cost;
2. the conversion circuit can convert one serial port into eight parallel ports, so that the first chip can control more RS485 or RS232 units, and the load capacity is improved;
3. the arrangement of the common mode suppression circuit can protect expensive equipment and simultaneously ensure that data is not endangered by transient voltage;
4. the protection circuit converts an input signal into a high level and a low level of an output signal by utilizing the switching characteristic of the NMOS, protects related devices from being burnt out when the input signal has high voltage, and has the advantages of good stability, high voltage prevention and low cost.
Drawings
The technical scheme of the utility model is further explained by combining the attached drawings as follows:
FIG. 1: the structure of the utility model is schematically shown.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. However, these embodiments are not limited to the present invention, and structural, method, or functional changes made by those skilled in the art according to these embodiments are all included in the scope of the present invention.
The present invention is not limited to the above embodiments, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are all included in the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.
The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
As shown in fig. 1, the utility model discloses a data acquisition system suitable for intelligent property, including common mode suppression circuit and protection circuit connected with first chip U1, common mode suppression circuit includes that one end is connected with analog input end, the other end passes through second resistance R2 to be connected in first resistance R1 of first chip U1 pin PA10, third resistance R3 and first stabiliser D1 are connected in parallel on first resistance R1, the other end of third resistance R3 and first stabiliser D1 is grounded; a first capacitor C1 is connected in parallel to the second resistor R2, and the other end of the first capacitor C1 is grounded. The common mode rejection circuit can protect expensive equipment, and meanwhile, data can be guaranteed not to be endangered by transient voltage. The pin VDD1, the pin VDD2, the pin VDD3 and the pin VDD4 of the first chip U1 are connected with a power supply input end, and the pin VSS1, the pin VSS2, the pin VSS3, the pin VSS4 and the pin VSSA of the first chip are grounded.
The protection circuit comprises a first triode Q1, an emitter of the first triode Q1 is connected to a pin PU10 of the first chip U1 through a fourth resistor R4, and a fifth resistor R5 is connected to the fourth resistor R4 in parallel and grounded; the base electrode of the first triode Q1 is grounded; the collector of the first triode Q1 is respectively connected to the sixth resistor R6 and to ground and to the gate of the NMOS transistor N1, the source of the NMOS transistor N1 is grounded, and the drain of the NMOS transistor N1 is connected to the power output through the motor M. When the pin PU10 of the first chip U1 emits a high level, the NMOS transistor N1 is turned on, and the motor M is started. When the pin PU10 of the first chip U1 emits a high level, the NMOS transistor N1 is turned off, and the motor M is turned off. The protection circuit converts an input signal into a high level and a low level of an output signal by utilizing the switching characteristic of the NMOS, protects related devices from being burnt out when the input signal has high voltage, and has the advantages of good stability, high voltage prevention and low cost.
The first chip U1 is connected with a conversion circuit, the conversion circuit comprises a second chip U2, a pin 2 of the second chip U2 is connected with a pin PA2 of the first chip U1, a pin 3 of the second chip U2 is connected with a pin PA3 of the first chip U1, a pin 4 of the second chip U2 is connected with a pin 5 of the second chip U2 sequentially through a seventh resistor R7, a first potentiometer RP1 and a ninth resistor R9, and a sliding pin on the first potentiometer RP1 is connected with a pin 6 of the second chip U2; a pin 8 of the second chip U2 is connected to a pin 1 of a second potentiometer RP2 and a collector of a second triode Q2, a pin 3 of the second potentiometer RP2 is connected to a pin 2 of the second potentiometer RP2 and a ninth resistor R9, an emitter of the second triode Q2 is connected to the other end of the ninth resistor R9 and one end of a second voltage regulator D2, and a gate of the second triode Q2 is connected to the other end of the second voltage regulator D2 through a tenth resistor R10; the pin 10 of the second chip U2 is connected with the power input end through a fourth capacitor C4, and the pin 11 of the second chip U2 is connected with the power input end. The conversion circuit can convert one serial port into eight parallel ports, and the first chip can control more RS485 or RS232 units, so that the load capacity is improved.
The first chip U1 is further connected with an oscillation circuit, the oscillation circuit comprises a second capacitor C2 and a third capacitor C3, one end of the second capacitor C3826 is connected with the first chip pin OSSC-OUT/PD1, the other end of the second capacitor C2 is grounded, one end of the third capacitor C3 is connected with the first chip pin OSSC-OUT/PD0, the other end of the third capacitor C3 is grounded, and a quartz crystal oscillator CR is further arranged between the third capacitor and the second capacitor. The oscillating circuit is used for generating a high-frequency sine wave signal.
In the above, the first chip U1 is specifically an At89S52 type linear power supply chip. The pin NRST of the first chip U1 is connected to an eleventh resistor R11 and a fifth capacitor C5, respectively, and the other ends of the eleventh resistor R11 and the fifth capacitor C5 are grounded. Further, the second chip U2 is an ICL8083 type linear power supply chip.
The beneficial effects of the utility model are mainly embodied in that:
1. the system has a simple structure, has the functions of decentralized acquisition, monitoring and centralized management of resident information, is perfect and reliable in acquired information, high in accuracy, and capable of accurately displaying the information of three meters, saving time, manpower and material resources, improving the working efficiency and reducing the property cost;
2. the conversion circuit can convert one serial port into eight parallel ports, so that the first chip can control more RS485 or RS232 units, and the load capacity is improved;
3. the arrangement of the common mode suppression circuit can protect expensive equipment and simultaneously ensure that data is not endangered by transient voltage;
4. the protection circuit converts an input signal into a high level and a low level of an output signal by utilizing the switching characteristic of the NMOS, protects related devices from being burnt out when the input signal has high voltage, and has the advantages of good stability, high voltage prevention and low cost.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above list of details is only for the practical implementation of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent implementations or modifications that do not depart from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (6)
1. Data acquisition system suitable for intelligence property, its characterized in that: the protection circuit comprises a common mode rejection circuit and a protection circuit, wherein the common mode rejection circuit is connected with a first chip (U1), the common mode rejection circuit comprises a first resistor (R1) with one end connected with an analog input end and the other end connected to a pin PA10 of the first chip (U1) through a second resistor (R2), a third resistor (R3) and a first voltage stabilizer (D1) are connected to the first resistor (R1) in parallel, and the other ends of the third resistor (R3) and the first voltage stabilizer (D1) are grounded; a first capacitor (C1) is connected in parallel to the second resistor (R2), and the other end of the first capacitor (C1) is grounded; the protection circuit comprises a first triode (Q1), an emitter of the first triode (Q1) is connected to a pin PU10 of the first chip (U1) through a fourth resistor (R4), and a fifth resistor (R5) is further connected to the fourth resistor (R4) in parallel and grounded; the base of the first triode (Q1) is grounded; the collector of the first triode (Q1) is respectively connected to the sixth resistor (R6) and the ground and the grid of an NMOS tube (N1), the source of the NMOS tube (N1) is grounded, and the drain of the NMOS tube (N1) is connected to the power supply output through the motor (M); the pin VDD1, the pin VDD2, the pin VDD3 and the pin VDD4 of the first chip (U1) are connected with a power supply input end, and the pin VSS1, the pin VSS2, the pin VSS3, the pin VSS4 and the pin VSSA of the first chip are grounded.
2. The data acquisition system suitable for intelligent property of claim 1, wherein: the first chip (U1) is connected with a conversion circuit, the conversion circuit comprises a second chip (U2), a pin 2 of the second chip (U2) is connected with a pin PA2 of the first chip (U1), a pin 3 of the second chip (U2) is connected with a pin PA3 of the first chip (U1), a pin 4 of the second chip (U2) is connected with a pin 5 of the second chip (U2) sequentially through a seventh resistor (R7), a first potentiometer (RP 1) and a ninth resistor (R9), and a sliding pin on the first potentiometer (RP 1) is connected with a pin 6 of the second chip (U2); a pin 8 of the second chip (U2) is connected with a pin 1 of a second potentiometer (RP 2) and a collector of a second triode (Q2), a pin 3 of the second potentiometer (RP 2) is connected with a pin 2 of the second potentiometer (RP 2) and a ninth resistor (R9), an emitter of the second triode (Q2) is connected with the other end of the ninth resistor (R9) and one end of a second voltage regulator (D2), and a gate of the second triode (Q2) is connected with the other end of the second voltage regulator (D2) through a tenth resistor (R10); the pin 10 of the second chip (U2) is connected with the power input end through a fourth capacitor (C4), and the pin 11 of the second chip (U2) is connected with the power input end.
3. The data acquisition system suitable for intelligent property of claim 2, wherein: the first chip (U1) is further connected with an oscillation circuit, the oscillation circuit comprises a second capacitor (C2) and a third capacitor (C3), one end of the second capacitor is connected with the first chip pin OSSC-OUT/PD1, the other end of the second capacitor is grounded, one end of the third capacitor is connected with the first chip pin OSSC-OUT/PD0, the other end of the third capacitor is grounded, and a quartz crystal oscillator (CR) is further arranged between the third capacitor and the second capacitor.
4. The data acquisition system suitable for intelligent property of claim 3, wherein: the pin NRST of the first chip (U1) is respectively connected with an eleventh resistor (R11) and a fifth capacitor (C5), and the other ends of the eleventh resistor (R11) and the fifth capacitor (C5) are grounded.
5. The data acquisition system suitable for intelligent property of claim 4, wherein: the first chip (U1) is an At89S52 type linear power supply chip.
6. The data acquisition system suitable for intelligent property of claim 5, wherein: the second chip (U2) is an ICL8083 type linear power supply chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920675110.6U CN209859287U (en) | 2019-05-13 | 2019-05-13 | Data acquisition system suitable for intelligent property |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920675110.6U CN209859287U (en) | 2019-05-13 | 2019-05-13 | Data acquisition system suitable for intelligent property |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209859287U true CN209859287U (en) | 2019-12-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920675110.6U Expired - Fee Related CN209859287U (en) | 2019-05-13 | 2019-05-13 | Data acquisition system suitable for intelligent property |
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| Country | Link |
|---|---|
| CN (1) | CN209859287U (en) |
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2019
- 2019-05-13 CN CN201920675110.6U patent/CN209859287U/en not_active Expired - Fee Related
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20191227 Termination date: 20210513 |
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| CF01 | Termination of patent right due to non-payment of annual fee |