CN209841186U - CMOS self-calibration light intensity monitoring integrated circuit - Google Patents
CMOS self-calibration light intensity monitoring integrated circuit Download PDFInfo
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- CN209841186U CN209841186U CN201920543132.7U CN201920543132U CN209841186U CN 209841186 U CN209841186 U CN 209841186U CN 201920543132 U CN201920543132 U CN 201920543132U CN 209841186 U CN209841186 U CN 209841186U
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Abstract
In the CMOS self-calibration light intensity monitoring integrated circuit, an output end of a light intensity measuring circuit is connected with an input end of a current-voltage linear conversion circuit; the input end of the current-voltage linear conversion circuit is connected with the output end of the light intensity measuring circuit and the first input end 3a of the self-calibration/monitoring control switch array; a first input end of the self-calibration/monitoring control switch array is connected with an output end of the current-voltage linear conversion circuit, a second input end SEL is a self-calibration control input end, and the first output end and the second output end are respectively connected with a first input end and a second input end of the output voltage sampling holding circuit; the first input end and the second input end of the output voltage sampling holding circuit are respectively connected with the first output end and the second output end of the self-calibration/monitoring control switch array; the first input end and the second input end of the comparison amplifying circuit (5) are respectively connected with the first output end and the second output end of the output voltage sample holding circuit, and the output end OUT2 is the output end of the utility model.
Description
Technical Field
The utility model relates to a CMOS self calibration light intensity monitoring integrated circuit.
Background
The illumination intensity measurement and monitoring become popular trends in the application aspects of LED intelligent illumination control, intelligent animal and plant cultivation technology and the like, and through illumination measurement and monitoring and further feedback and control, an illumination system can be intelligently adjusted, the growth cycle of animals and plants is controlled, the yield is improved, the time cost is saved, and the like.
A buried double PN junction photodiode is formed of two vertically stacked diodes of different depths. The output current under illumination has a linear relation with the incident light power, and can be used as a light detector for measuring the illumination intensity.
The integrated circuit for measuring and monitoring the illumination intensity based on the microelectronic technology adopts a CMOS (complementary metal oxide semiconductor) process, can improve the detection precision of weak signals while greatly reducing the circuit volume, and integrates a subsequent self-calibration and monitoring control circuit and a buried double-PN-junction photodiode photoelectric sensing unit in a single chip.
The existing illumination intensity monitoring is based on a discrete photoelectric sensing unit and a signal processing circuit, and required components are installed on the same printed circuit board, which belongs to board-level integration. Due to the weak photoelectric sensing signal, the attenuation and interference of the signal between board levels can reduce the accuracy of the measurement.
Disclosure of Invention
The utility model discloses overcome prior art's above-mentioned shortcoming, provide a CMOS self calibration light intensity monitoring integrated circuit.
The utility model discloses a CMOS self calibration light intensity monitoring integrated circuit, by light intensity measurement circuit 1, the linear converting circuit of current-voltage 2, self calibration/monitoring control switch array 3, output voltage sample hold circuit 4, comparison amplifier circuit 5, 5 circuit module constitute altogether.
In the light intensity measuring circuit 1, an output end 1b is connected with an input end 2a of the current-voltage linear conversion circuit 2;
the light intensity measuring circuit 1 consists of a shallow PN junction photodiode D1 and a deep PN junction photodiode D2; the shallow PN junction photodiode D1 and the deep PN junction photodiode D2 are connected with a common cathode, and are used as the output end 1b of the light intensity measuring circuit 1, and the deep PN junction photodiode D1 and the PN junction photodiode D2 are connected with a common anode and are grounded;
in the current-voltage linear conversion circuit 2, an input end 2a is connected with an output end 1b of the light intensity measuring circuit 1, and an output end 2b is connected with a first input end 3a of the self-calibration/monitoring control switch array 3;
the current-voltage linear conversion circuit 2 consists of NMOS tubes N1, N2, N3 and N4, PMOS tubes P1, P2, P3 and P4 and a capacitor C1; the source of the PMOS tube P1 is connected with a power supply VDD, the grid is connected with the grid of the PMOS tube P2, the drain is connected with the source of the PMOS tube P3, the grid of the PMOS tube P3 is connected with the grid of the PMOS tube P4, the drain is connected with the drain of the NMOS tube N1 and serves as the output end 2b of the current-voltage linear conversion circuit 2, the grid of the NMOS tube N1 is connected with the grid of the NMOS tube N2, the source is connected with the drain of the NMOS tube N3, the source of the NMOS tube N3 is grounded, the grid is used as the input end 2a of the current-voltage linear conversion circuit 2, the source of the PMOS tube P2 is connected with the power supply VDD, the grid-drain short circuit is connected, the drain is connected with the source of the PMOS tube P4, the grid-drain short circuit of the PMOS tube P4, the drain is connected with the drain of the NMOS tube N38, the grid-drain of the NMOS tube N2 is short circuit, the source is connected with the drain of the NMOS tube N4, the other end of the capacitor C1 is connected with the input end 2a of the current-voltage linear conversion circuit 2;
in the self-calibration/monitoring control switch array 3, a first input end 3a is connected with an output end 2b of the current-voltage linear conversion circuit 2, a second input end SEL is a self-calibration control input end, and a first output end 31b and a second output end 32b are respectively connected with a first input end 41a and a second input end 42a of the output voltage sample-and-hold circuit 4;
the self-calibration/monitoring control switch array 3 consists of PMOS tubes P5, P6, P7 and P8 and NMOS tubes N5, N6, N7 and N8; the source electrode of the PMOS tube P5 is connected with a power supply VDD, the grid electrode of the PMOS tube P5 is connected with the grid electrode of the NMOS tube N5, the grid electrode of the NMOS tube N6, the grid electrode of the PMOS tube P7 and the grid electrode of the PMOS tube P8 and is used as a second input end SEL, the drain electrode of the PMOS tube P5 is connected with the drain electrode of the NMOS tube N5, and is connected with the grid electrode of the PMOS tube P6, the grid electrode of the NMOS tube N7 and the grid electrode of the NMOS tube N8, the source electrode of the NMOS transistor N5 is grounded, the source electrode of the PMOS transistor P6 is connected with the drain electrode of the NMOS transistor N6, the source electrode of the PMOS transistor P7 and the drain electrode of the NMOS transistor N7 and serves as a first input end 3a, the drain electrode of the PMOS tube P6 is connected with the source electrode of the NMOS tube N6, the drain electrode of the PMOS tube P7 and the source electrode of the NMOS tube N7, the drain of the NMOS transistor N8 is connected to the source of the PMOS transistor P8 as the first output terminal 31b, the source electrode of the NMOS transistor N8 is connected with the drain electrode of the PMOS transistor P8 and serves as a second output end 32 b;
in the output voltage sample-and-hold circuit 4, a first input end 41a and a second input end 42a are respectively connected to a first output end 31b and a second output end 32b of the self-calibration/monitoring control switch array 3, the first output end is OUT1, and the second output end is 4 b;
the output voltage sample-and-hold circuit 4 is composed of capacitors C2 and C3; one end of the capacitor C2 is connected with the first output end OUT1, the other end of the capacitor C2 is grounded, one end of the capacitor C3 is connected with the output 4b, and the other end of the capacitor C3 is grounded;
in the comparison and amplification circuit 5, the first input end 51a and the second input end 52a are respectively connected to the first output end OUT1 and the second output end 4b of the output voltage sample-and-hold circuit 4, and the output end OUT2 is the output end of the comparison and amplification circuit 5 and is also the output end of the present invention;
the comparison amplifying circuit 5 is composed of NMOS tubes N9, N10, N11, N12, N13, N14 and N15, and PMOS tubes P9, P10, P11, P12, P13, P14 and P15; the source of the PMOS tube P11 is connected with a power supply VDD, the gate is connected with the grid of the PMOS tube P14, the source of the PMOS tube P9 is connected with the source of the PMOS tube P10 and is connected with the drain of the PMOS tube P11, the grid of the PMOS tube P9 is connected with the grid of the NMOS tube N9, the grid of the PMOS tube P10 is connected with the grid of the NMOS tube N10, the grid of the NMOS tube N9 is used as a first input end 51a of the comparison and amplification circuit 5, the source is connected with the source of the NMOS tube N10 and is connected with the drain of the NMOS tube N11, the grid of the NMOS tube N10 is used as a second input end 52a of the comparison and amplification circuit 5, the source of the NMOS tube N11 is grounded, the grid is connected with the grid of the NMOS tube N14, the source of the PMOS tube P14 is connected with a power supply VDD, the grid drain is in short circuit, the grid is connected with the PMOS tube P15, the drain of the PMOS tube P12, and the drain of the PMOS tube P12 is connected with the drain of, the NMOS transistor N12 grid drain short circuit, the grid connects NMOS transistor N13 grid, the source connects NMOS transistor N15 drain, and draws the port and connects PMOS transistor P10 drain, NMOS transistor N14 grid drain short circuit, the grid connects NMOS transistor N15 grid, the source is grounded, PMOS transistor P15 source connects power VDD, the drain connects PMOS transistor P13 source, and draws the port and connects NMOS transistor N10 drain, PMOS transistor P13 drain connects NMOS transistor N13 drain, and draws the port as the output OUT2 of whole circuit, NMOS transistor N13 source connects NMOS transistor N15 drain, and draws the port and connects PMOS transistor P10 drain, NMOS transistor N15 source ground connection.
The utility model discloses can realize the control to the measurement of illumination intensity and light intensity variation to can realize the self calibration according to different illumination intensity requirements, satisfy the monitoring demand of different illumination intensity environment. The utility model adopts CMOS technology to integrate the light intensity measuring unit and the follow-up signal processing circuit, thus realizing the intellectualization and the miniaturization of the self-calibration light intensity measuring and monitoring circuit;
the utility model has the advantages that: the utility model provides a CMOS self calibration light intensity measurement and monitoring integrated circuit, with bury the two PN junction photodiode monolithic integrations of CMOS, can realize the self calibration real-time supervision of illumination intensity parameter, it is little to have the error, and the precision is high, and detection range is wide, and advantages such as circuit is small, the low power dissipation, but wide application in illumination intensity monitoring's occasion.
Drawings
FIG. 1 is a block diagram of the structure of the present invention
FIG. 2 is a schematic diagram of the present invention
FIG. 3 is a partial enlarged view of the portion S1 in FIG. 2
FIG. 4 is a partial enlarged view of the portion S2 in FIG. 2
FIG. 5 is a partial enlarged view of the portion S3 in FIG. 2
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
The utility model discloses a CMOS self calibration light intensity measurement and monitoring integrated circuit, by light intensity measurement circuit 1, the linear converting circuit of current-voltage 2, self calibration/monitoring control switch array 3, output voltage sample hold circuit 4, comparison amplifier circuit 5, 5 circuit module constitute altogether.
The light intensity measuring circuit 1 converts light signals into electric signals by using a diode photoelectric effect, the photodiodes D1 and D2 are used for converting the light signals into the electric signals, the illumination intensity and the output current form a strong dependence relationship, the photodiodes D1 and D2 adopt a parallel structure, the output current of the output end 1b of the light intensity measuring circuit is the sum of the currents D1 and D2, and the test sensitivity is improved;
the current-voltage linear conversion circuit 2 is high in sensitivity and strong in anti-interference performance, and converts a current signal into a voltage signal by reading weak current at the input end 2 a; the circuit is integrated and converted into voltage output through the capacitor C1, wherein a cascode amplifying circuit formed by the PMOS tubes P1 and P3 and the NMOS tubes N1 and N3 is used as an operational amplifier in the current-voltage linear conversion circuit 2, the PMOS tubes P2 and P4 and the NMOS tubes N2 and N4 provide bias for the cascode amplifying circuit, the current-voltage linear conversion circuit 2 provides very low reverse bias voltage for the photodiode through an operational amplifier feedback loop to reduce dark current, and meanwhile, the voltage on the parasitic capacitor of the photodiode is kept unchanged in the integration stage, so that the integrated voltage output at the output end 2b is ensured to have better linearity;
the self-calibration/monitoring control switch array 3 is used for switching between a self-calibration mode and a monitoring mode under different light intensity requirement environments; the NMOS transistor N6 and the PMOS transistor P6 form a first transmission gate, the NMOS transistor N7 and the PMOS transistor P7 form a second transmission gate, the NMOS transistor N8 and the PMOS transistor P8 form a third transmission gate, when a control terminal SEL inputs a low level, the first transmission gate is disconnected, the second transmission gate and the third transmission gate are connected, at the time, the first output end 31b and the second output end 32b of the self-calibration/monitoring control switch array 3 output the same voltage value, the output voltage and the photocurrent intensity are in a linear relation, the circuit is in a self-calibration mode, when the control terminal SEL inputs a high level, the first transmission gate is connected, the second transmission gate and the third transmission gate are disconnected, at the time, the output voltage of the second output end 32b of the self-calibration/monitoring control switch array 3 is kept as a reference value at the end of the self-calibration mode and does not change along with the light intensity, and the output voltage of the first output end 31b still changes along with the illumination intensity, whether the illumination intensity changes or not can be dynamically monitored by comparing the voltages of the first output end 31b and the second output end 32b, and in addition, the driving capability of signals can be increased by a transmission gate in the circuit;
the output voltage sample and hold circuit 4 is composed of a sampling capacitor, the output voltage is held by the capacitor, when the circuit is in a self-calibration mode, the output voltages of a first output end OUT1 and a second output end 4b in the output voltage sample and hold circuit 4 are the same and are respectively stored on capacitors C2 and C3, the output voltage changes along with the illumination intensity, when the circuit is in a monitoring mode, the output voltage of the second output end 4b in the output voltage sample and hold circuit 4 is kept as a reference value at the end of the self-calibration mode and does not change along with the illumination intensity;
the comparison amplification output circuit 5 is used for amplifying and outputting voltage signals between two output ends of the output voltage sample-hold circuit 4 after making a difference, when the circuit is in an illumination intensity monitoring mode, if the illumination intensity exceeds a set reference intensity, the output voltage of a first output end OUT1 in the output voltage sample-hold circuit 4 exceeds the reference voltage of a second output end 4b in the output voltage sample-hold circuit 4, at this time, an output end OUT2 of the comparison amplification output circuit 5 outputs a high level signal, otherwise, an output end OUT2 of the comparison amplification output circuit 5 outputs a low level signal, if the monitored illumination intensity is not changed, the output voltage of the comparison amplification output circuit 5 is 1/2 power voltage, the comparison amplification output circuit 5 adopts a rail-to-rail structure, when the input voltage of the input ends 51a and 52a changes from 0 to the power voltage, both can be comparatively amplified;
the embodiments described in this specification are merely illustrative of implementations of the inventive concepts, and the scope of the invention should not be considered limited to the specific forms set forth in the embodiments, but rather by the claims and their equivalents.
Claims (1)
- CMOS self-calibration light intensity monitoring integrated circuit, characterized by: the device comprises a light intensity measuring circuit (1), a current-voltage linear conversion circuit (2), a self-calibration/monitoring control switch array (3), an output voltage sampling and holding circuit (4) and a comparison and amplification circuit (5);in the light intensity measuring circuit (1), an output end 1b is connected with an input end 2a of a current-voltage linear conversion circuit (2);the light intensity measuring circuit (1) consists of a shallow PN junction photodiode D1 and a deep PN junction photodiode D2; the shallow PN junction photodiode D1 is connected with the deep PN junction photodiode D2 in a common cathode mode and serves as the output end 1b of the light intensity measuring circuit (1), and the deep PN junction photodiode D1 is connected with the PN junction photodiode D2 in a common anode mode and is grounded;in the current-voltage linear conversion circuit (2), an input end 2a is connected with an output end 1b of the light intensity measuring circuit (1), and an output end 2b is connected with a first input end 3a of the self-calibration/monitoring control switch array (3);the current-voltage linear conversion circuit (2) consists of NMOS tubes N1, N2, N3, N4, PMOS tubes P1, P2, P3, P4 and a capacitor C1; a source electrode of a PMOS tube P1 is connected with a power supply VDD, a grid electrode is connected with a grid electrode of a PMOS tube P2, a drain electrode is connected with a source electrode of a PMOS tube P3, a grid electrode of a PMOS tube P3 is connected with a grid electrode of a PMOS tube P4, the drain electrode is connected with a drain electrode of an NMOS tube N1 and serves as an output end 2b of the current-voltage linear conversion circuit (2), a grid electrode of an NMOS tube N1 is connected with a grid electrode of an NMOS tube N2, a source electrode is connected with a drain electrode of an NMOS tube N3, a source electrode of the NMOS tube N3 is grounded, the grid electrode serves as an input end 2a of the current-voltage linear conversion circuit (2), a source electrode is connected with a grid-drain short circuit, a drain electrode is connected with a source electrode of the PMOS tube P4, a grid-drain short circuit of the PMOS tube P4, a drain electrode is connected with a drain electrode of the NMOS tube N2, a grid-drain electrode short circuit of the NMOS tube N2, a source electrode is connected with a drain electrode of the NMOS tube N596;in the self-calibration/monitoring control switch array (3), a first input end 3a is connected with an output end 2b of the current-voltage linear conversion circuit (2), a second input end SEL is a self-calibration control input end, and a first output end 31b and a second output end 32b are respectively connected with a first input end 41a and a second input end 42a of the output voltage sample holding circuit (4);the self-calibration/monitoring control switch array (3) consists of PMOS tubes P5, P6, P7 and P8 and NMOS tubes N5, N6, N7 and N8; a source electrode of a PMOS tube P5 is connected with a power supply VDD, a grid electrode of the NMOS tube N5, a grid electrode of the NMOS tube N6, a grid electrode of the PMOS tube P7 and a grid electrode of the PMOS tube P8 are connected and serve as a second input end SEL, a drain electrode of the PMOS tube P5 is connected with a drain electrode of the NMOS tube N5, a grid electrode of the PMOS tube P6, a grid electrode of the NMOS tube N7 and a grid electrode of the NMOS tube N8, a source electrode of the NMOS tube N5 is grounded, a source electrode of the PMOS tube P6 is connected with a drain electrode of the NMOS tube N6, a source electrode of the PMOS tube P7 and a drain electrode of the NMOS tube N7 and serve as a first input end 3a, a drain electrode of the PMOS tube P6 is connected with a source electrode of the NMOS tube N6, a drain electrode of the PMOS tube P7 and a source electrode of the NMOS tube N7, a drain electrode of the NMOS tube N8 is connected with a source electrode of the PMOS tube P8 and serves as a first;in the output voltage sample-and-hold circuit (4), a first input end 41a and a second input end 42a are respectively connected with a first output end 31b and a second output end 32b of the self-calibration/monitoring control switch array (3), the first output end is OUT1, and the second output end is 4 b;the output voltage sample-and-hold circuit (4) is composed of capacitors C2 and C3; one end of the capacitor C2 is connected with the first output end OUT1, the other end is grounded, one end of the capacitor C3 is connected with the output 4b, and the other end is grounded;in the comparison and amplification circuit (5), a first input end 51a and a second input end 52a are respectively connected with a first output end OUT1 and a second output end 4b of an output voltage sample-and-hold circuit (4), and an output end OUT2 is an output end of the comparison and amplification circuit (5) and is also a total output end;the comparison amplification circuit (5) is composed of NMOS tubes N9, N10, N11, N12, N13, N14 and N15, and PMOS tubes P9, P10, P11, P12, P13, P14 and P15; a source of a PMOS tube P11 is connected with a power supply VDD, a grid is connected with a grid of a PMOS tube P14, a source of the PMOS tube P9 is connected with a source of a PMOS tube P10 and is connected with a drain of the PMOS tube P11, a grid of the PMOS tube P9 is connected with a grid of an NMOS tube N9, a grid of the PMOS tube P10 is connected with a grid of an NMOS tube N10, a grid of the NMOS tube N9 is used as a first input end 51a of the comparison amplifying circuit (5), a source of the NMOS tube N10 is connected with a source of the NMOS tube N10 and is connected with a drain of the NMOS tube N11, a grid of the NMOS tube N10 is used as a second input end 52a of the comparison amplifying circuit (5), a source of the NMOS tube N11 is grounded, a grid is connected with a grid of an NMOS tube N14, a source of the PMOS tube P14 is connected with the power supply VDD, a grid drain short circuit, a grid is connected with a grid of the PMOS tube P15, a drain of the PMOS tube P12, a drain of the PMOS tube is connected with a drain of the PMOS tube P12, a drain of the NMOS tube, a drain of the NMOS, the grid drain of the NMOS tube N14 is in short circuit, the grid is connected with the grid of the NMOS tube N15, the source is grounded, the source of the PMOS tube P15 is connected with the power VDD, the drain is connected with the source of the PMOS tube P13, the leading-OUT port is connected with the drain of the NMOS tube N10, the drain of the PMOS tube P13 is connected with the drain of the NMOS tube N13, the leading-OUT port is used as the output end OUT2 of the whole circuit, the source of the NMOS tube N13 is connected with the drain of the NMOS tube N15, the leading-OUT port is connected with the drain of the PMOS tube.
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| CN201920543132.7U CN209841186U (en) | 2019-04-19 | 2019-04-19 | CMOS self-calibration light intensity monitoring integrated circuit |
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| CN201920543132.7U CN209841186U (en) | 2019-04-19 | 2019-04-19 | CMOS self-calibration light intensity monitoring integrated circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109959448A (en) * | 2019-04-19 | 2019-07-02 | 浙江工业大学 | CMOS self calibration intensity monitor integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109959448A (en) * | 2019-04-19 | 2019-07-02 | 浙江工业大学 | CMOS self calibration intensity monitor integrated circuit |
| CN109959448B (en) * | 2019-04-19 | 2023-11-17 | 浙江工业大学 | CMOS self-calibration light intensity monitoring integrated circuit |
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