CN209824120U - Circuit board and electric connector with same - Google Patents
Circuit board and electric connector with same Download PDFInfo
- Publication number
- CN209824120U CN209824120U CN201920112172.6U CN201920112172U CN209824120U CN 209824120 U CN209824120 U CN 209824120U CN 201920112172 U CN201920112172 U CN 201920112172U CN 209824120 U CN209824120 U CN 209824120U
- Authority
- CN
- China
- Prior art keywords
- metal
- circuit board
- layer
- differential
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
The utility model discloses a circuit board and have electric connector of this circuit board. The circuit board is sequentially provided with a first circuit layer, a first insulating layer, a second circuit layer, an insulating substrate, a third circuit layer, a second insulating layer and a fourth circuit layer from top to bottom in a stacking manner. The first metal routing and the second metal routing are respectively formed on the first circuit layer and the second circuit layer and form a first differential routing pair. The third metal routing and the fourth metal routing are respectively formed on the third circuit layer and the fourth circuit layer and form a second differential routing pair; the two metal wires forming each differential wire pair are vertically corresponding and have different widths, so that crosstalk between signals of adjacent differential pairs can be reduced.
Description
Technical Field
The present invention relates to a connector, and more particularly to a circuit board capable of transmitting differential signals and an electrical connector having the same.
Background
Differential Signal (Differential Signal) is a Signal transmission technology, and its application in high-speed circuit design is becoming more and more extensive, and the most critical signals in the circuit are often designed by using a Differential structure, and the pair of traces carrying Differential signals is called Differential traces.
In actual circuit board (PCB) routing, the conventional differential trace structure cannot effectively reduce crosstalk noise between adjacent differential pairs, which affects signal integrity of high-speed systems.
Therefore, there is a need for a new circuit board that employs a completely new wiring scheme to solve the problems of the prior art.
SUMMERY OF THE UTILITY MODEL
A primary object of the present invention is to provide a circuit board capable of transmitting differential signals and reducing crosstalk between adjacent differential pairs.
Another object of the present invention is to provide an electrical connector, which employs a novel circuit board to reduce crosstalk between adjacent differential pair signals.
Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.
In order to achieve the purpose, the utility model adopts the following technical scheme: the circuit board is sequentially stacked from top to bottom and provided with: a first circuit layer, a first insulating layer, a second circuit layer, an insulating substrate, a third circuit layer, a second insulating layer, and a fourth circuit layer. At least one first metal wire is formed on the first circuit layer, at least one second metal wire is formed on the second circuit layer, and the first metal wire and the second metal wire form a first differential wire pair; at least one third metal wire is formed on the third circuit layer, at least one fourth metal wire is formed on the fourth circuit layer, and the third metal wire and the fourth metal wire form a second differential wire pair. The two metal wires forming each differential wire pair are corresponding up and down and have different widths.
In one embodiment, the width of the first metal trace is greater than the width of the second metal trace, and the width of the fourth metal trace is greater than the width of the third metal trace.
In one embodiment, the two metal traces forming each differential trace pair have at least a portion of paths extending in a staggered manner and the orthogonal projections thereof are located in the same projection area.
In one embodiment, the two metal traces forming each differential trace pair have at least a portion of a serpentine path.
In one embodiment, one of the metal traces forming each differential trace pair has at least a portion of serpentine path, and the other metal trace has at least a portion of linear path, and the at least a portion of linear path and the at least a portion of serpentine path correspond to each other up and down and extend in a staggered manner.
In one embodiment, the first metal trace has at least a portion of a serpentine path, the second metal trace has at least a portion of a linear path, and the width of the first metal trace is greater than the width of the second metal trace.
In one embodiment, the insulating substrate has a first surface and a second surface, the first surface is parallel to the second surface; the second circuit layer is a metal layer, is laid on the first surface of the insulating substrate, and is also provided with another second metal routing; the first insulating layer covers the second circuit layer; the first circuit layer is a metal layer, is formed on the first insulating layer, and is also provided with another first metal wire, and the another first metal wire and the another second metal wire form a third differential wire pair; the third circuit layer is a metal layer, is formed on the second surface of the insulating substrate, and is also provided with another third metal routing; the second insulating layer covers the third circuit layer; and the fourth circuit layer is a metal layer, is formed on the second insulating layer, and is also provided with another fourth metal wire, and the another first metal wire and the another second metal wire form a fourth differential wire pair.
In one embodiment, the circuit board further has a plurality of conductive through holes formed thereon, each of the conductive through holes penetrating the upper and lower surfaces of the circuit board, and each of the conductive through holes is connected to one end of one of the metal traces.
In order to achieve the above purpose, the utility model discloses still adopt following technical scheme: an electrical connector comprises a circuit board as described above, and a plurality of conductive terminals mounted to the circuit board; each conductive terminal is electrically connected with one end of one metal wire.
Compared with the prior art, the utility model discloses circuit board and electric connector that has this circuit board walk the line setting on the circuit layer of difference through two metals that will constitute every difference line pair, and the width is inconsistent to these two metals are walked at least partly route and are crisscross extension each other and its orthographic projection is located same projection region, walk the line and be close to each other with these two metals of guarantee this difference line pair, thereby strengthen coupling each other. The utility model discloses circuit board and electric connector who has this circuit board can reduce the signal crosstalk between the adjacent difference line pair.
Drawings
Fig. 1 is a schematic perspective view of a circuit board according to a first embodiment of the present invention.
Fig. 2 is a cross-sectional view of the circuit board of the present invention along the line a-a shown in fig. 1.
Fig. 3 is a top view of the circuit board of the present invention shown in fig. 1.
Fig. 4 is a bottom view of the circuit board of the present invention shown in fig. 1.
Fig. 5 is a layout diagram of the first embodiment of the differential routing pair according to the present invention.
Fig. 6 is a top view of the differential trace pair of the present invention shown in fig. 5.
Fig. 7 is a bottom view of the differential wiring pair shown in fig. 5.
Fig. 8 is a layout diagram of a second embodiment of the differential routing pair according to the present invention.
Fig. 9 is a top view of the differential pair of traces shown in fig. 8.
Fig. 10 is a bottom view of the differential pair of traces shown in fig. 8.
Fig. 11 is a diagram of a usage status of the circuit board of the present invention.
Fig. 12 is a diagram of a usage status of the circuit board of the present invention at another angle.
Fig. 13 is a schematic structural diagram of the electrical connector of the present invention.
Fig. 14 is a schematic view of the disassembled structure of the electrical connector of the present invention.
The reference numbers in the above figures are as follows:
electric connector 1 circuit board 10
First circuit layer 101 first insulating layer 102
Second circuit layer 103 insulating substrate 104
First surface 1040 and second surface 1041
Third line layer 105 second insulating layer 106
Fourth line layer 107 via 108
Pad 109 first differential pair of traces 21, 21a
Second differential track pair 22, 22a third differential track pair 23, 23a
Fourth differential pair of traces 24, 24a
First metal trace 201, 201', 201a
Second metal trace 202, 202', 202a
Third Metal trace 203, 203 'fourth Metal trace 204, 204'
Conductive terminal 40 with strip-shaped projection regions 30, 30a
Front terminal 41 and rear terminal 42
A cable 50.
Detailed Description
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. In the present invention, directional terms such as "up", "down", "front", "back", "left", "right", "top", "bottom", etc. refer to directions of the attached drawings only. Accordingly, the directional terms used are used for describing and understanding the present invention, and are not used for limiting the present invention.
Referring to fig. 1 and fig. 2, the circuit board 10 of the present invention is sequentially stacked from top to bottom to form a first circuit layer 101, a first insulating layer 102, a second circuit layer 103, an insulating substrate 104, a third circuit layer 105, a second insulating layer 106, and a fourth circuit layer 107. At least one first metal trace 201 is formed on the first circuit layer 101, at least one second metal trace 202 is formed on the second circuit layer 103, and the first metal trace 201 and the second metal trace 202 form a differential trace pair. In addition, at least one third metal trace 203 is formed on the third circuit layer 105, and at least one fourth metal trace 204 is formed on the fourth circuit layer 107, wherein the third metal trace 203 and the fourth metal trace 204 also form a differential trace pair.
More specifically, referring to fig. 2 and fig. 5, in the first embodiment, the first metal trace 201 and the second metal trace 202 are vertically corresponding and staggered to form a first differential trace pair 21. The third metal trace 203 and the fourth metal trace 204 are also vertically corresponding and staggered to form a second differential trace pair 22.
Referring to fig. 2 and fig. 5, in the first embodiment, a differential routing pair, i.e., a third differential routing pair 23, is further formed on the first circuit layer 101 and the second circuit layer 103. A differential wiring pair, i.e., a fourth differential wiring pair 24, is further formed on the third wiring layer 105 and the fourth wiring layer 107. In more detail, another first metal trace 201 'is further formed on the first circuit layer 101, and another second metal trace 202' is further formed on the second circuit layer 103, where the another first metal trace 201 'and the another second metal trace 202' form the third differential trace pair 23. In addition, another third metal trace 203 'is formed on the third circuit layer 105, and another fourth metal trace 204' is formed on the fourth circuit layer 107, where the another third metal trace 203 'and the another fourth metal trace 204' form the fourth differential trace pair 24.
As shown in fig. 3, the two first metal traces 201, 201' can be represented on the top surface of the circuit board 10. Of course, solder resist can also be coated on the top surface of the circuit board 10 to provide insulation protection for the first metal traces 201, 201'.
As shown in fig. 4, the two fourth metal traces 204, 204' can be represented on the bottom surface of the circuit board 10. Of course, solder resist can be coated on the bottom surface of the circuit board 10 to provide insulation protection for the fourth metal traces 204, 204'.
In the first embodiment, as shown in fig. 2, the two metal traces constituting each differential trace pair are located in different line layers to reduce signal crosstalk between adjacent differential trace pairs. Taking the first differential routing pair 21 as an example, the first metal routing 201 and the second metal routing 202 constituting the first differential routing pair 21 are respectively located in the first circuit layer 101 and the second circuit layer 103, and the widths of the first metal routing 201 and the second metal routing 202 are different, for example, the width of the first metal routing 201 is greater than the width of the second metal routing 202. In this embodiment, the width of the fourth metal trace 204 is greater than the width of the third metal trace 203.
In the first embodiment, as shown in fig. 5, each of the two metal traces forming each differential trace pair has at least a portion of paths extending in a staggered manner, and orthogonal projections of the at least a portion of paths are located in the same projection area in a direction perpendicular to the top surface of the circuit board (i.e., in a top view direction of the circuit board), so as to ensure that the two metal traces of the differential trace pair are close to each other, and enhance coupling therebetween. Taking the first differential trace pair 21 as an example, the two metal traces 201 and 202 constituting the first differential trace pair 21 each have at least a portion of a serpentine path (which may also be called S-shaped or serpentine path), and the serpentine paths of the two metal traces 201 and 202 extend in a staggered manner and their orthographic projections are located in the same projection area, for example, a strip-shaped projection area 30 (see fig. 6). In this embodiment, at least a portion of the serpentine path is substantially located in the middle region of the corresponding metal trace, for example, the serpentine path of the first metal trace 201 is located in the middle region of the first metal trace 201.
Each layer of the circuit board 10 of the present invention will be described in detail below.
As shown in fig. 2, the insulating substrate 104 has a first surface 1040 and a second surface 1041. The first surface 1040 is parallel to the second surface 1041. The insulating substrate 104 is made of an insulating and heat-insulating material and is not easily bent. In the first embodiment, the insulating substrate 104 may be made of Glass Epoxy (Glass Epoxy) or the like.
As shown in fig. 2, the second circuit layer 103 is formed on the first surface 1040 of the insulating substrate 104. For example, the second circuit layer 103 can be a thin metal layer, which is laid on the first surface, and etched or otherwise formed to form at least one second metal trace 202. In the first embodiment, two second metal traces 202 and 202' are formed on the first circuit layer 101.
As shown in fig. 2, the first insulating layer 102 covers the entire second circuit layer 103 to provide isolation.
As shown in fig. 2, the first circuit layer 101 is formed on the first insulating layer 102 in the same manner as the second circuit layer 103. Likewise, at least one first metal trace 201 can also be formed by etching or other methods. In the first embodiment, two first metal traces 201 and 201 'are formed on the first circuit layer 101, and the two first metal traces 201 and 201' are shown in fig. 1, fig. 2 and fig. 3.
Similarly, as shown in fig. 2, the third circuit layer 105 is formed on the second surface 1041 of the insulating substrate 104. In the first embodiment, two third metal traces 203, 203' are formed on the third circuit layer 105.
As shown in fig. 2, the second insulating layer 106 covers the entire third circuit layer 105 to provide an isolation function.
As shown in fig. 2, the fourth circuit layer 107 is formed on the second insulating layer 106. In the first embodiment, two fourth metal traces 204, 204' are formed on the fourth circuit layer 107. Both of these fourth metal tracks 204, 204' are represented in fig. 2 and 4.
Fig. 6 and 7 respectively show a top view and a bottom plan view of the differential trace pair of the present invention to clearly show the planar layout structure of the first differential trace pair 21, the second differential trace pair 22, the third differential trace pair 23, and the fourth differential trace pair 24. The two metal traces forming each differential trace pair have at least a portion of a serpentine path (also referred to as S-shaped or serpentine path), which extend in a staggered manner and whose orthographic projections are located in the same projection area, such as the strip-shaped projection area 30 (see fig. 6).
However, the path shape of the differential wiring pair is not limited to the serpentine shape of the first embodiment.
Fig. 8, 9, and 10 show a second embodiment of the differential wiring pair according to the present invention. This second embodiment also provides a first differential running pair 21a, a second differential running pair 22a, a third differential running pair 23a, and a fourth differential running pair 24a similar to the first embodiment. The two metal wires forming each differential wire pair are positioned in different circuit layers and have different widths, at least part of paths of the two metal wires forming each differential wire pair are not overlapped but extend in a staggered mode, orthographic projections of the two metal wires are positioned in the same projection area, the two metal wires of the differential wire pair are close to each other, and coupling between the two metal wires is enhanced. Furthermore, one of the metal traces forming each differential trace pair has at least a portion of a serpentine path, and the other metal trace has at least a portion of a straight-line path, where the at least a portion of the serpentine path and the at least a portion of the straight-line path extend in a staggered manner and their orthographic projections are located in the same projection area, such as a strip-shaped projection area 30a (see fig. 9).
Referring to fig. 8, taking the first differential trace pair 21a as an example, one of the metal traces (i.e., the first metal trace 201 a) forming the first differential trace pair 21a has at least a portion of a serpentine path, and the other metal trace (i.e., the second metal trace 202 a) has at least a portion of a linear path, as shown in the figure, the at least a portion of the linear path and the at least a portion of the serpentine path are not overlapped, extend in a staggered manner, and have orthographic projections thereof located in the same projection area.
In this embodiment, the at least one portion of the straight path and the at least one portion of the serpentine path are both located approximately in the middle of the corresponding metal trace.
In addition, as shown in fig. 1, a plurality of vias 108 are formed on the circuit board 10, each via 108 penetrates through the upper and lower surfaces of the circuit board 10, and each via 108 corresponds to a metal trace and is connected to one end of the metal trace. In more detail, a pad 109 (see fig. 5) is formed at each of two ends of each metal trace, and each pad 109 is electrically connected to a corresponding via 108.
As shown in fig. 11 and 12, each of the conductive through holes 108 of the circuit board 10 of the present invention can be used for an external conductive terminal 40 to be soldered thereon or inserted therein to form an electrical connection.
As shown in fig. 13 and 14, the electrical connector 1 of the present invention employs the circuit board 10 shown in fig. 1.
Referring to fig. 11, 12, 13 and 14, the electrical connector 1 includes a plurality of conductive terminals 40 mounted on the circuit board 10. Each conductive terminal 40 is electrically connected to one end of a corresponding one of the metal traces on the circuit board 10. In addition, the conductive terminal 40 includes a plurality of front terminals 41 and a plurality of rear terminals 42, wherein the front terminals 41 can electrically interface with a corresponding mating connector (not shown); the rear terminal 42 is fork-shaped and can be electrically connected to the cable 50 of the electrical connector 1.
To sum up, the utility model discloses circuit board 10 and electric connector 1 that has this circuit board are walked the line setting on the circuit layer of difference through two metals that will constitute every difference walking line pair, and the width is inconsistent, and these two metals are walked at least partly route and are crisscross extension each other and its orthographic projection is located same projection region, it is close to each other to walk the line with these two metals of guarantee this difference walking line pair, thereby strengthen mutual coupling, the overall arrangement of this difference walking line pair simultaneously can also reduce the signal crosstalk between the adjacent difference walking line pair.
Claims (9)
1. A circuit board, characterized by: the circuit board is sequentially provided with a first circuit layer, a first insulating layer, a second circuit layer, an insulating substrate, a third circuit layer, a second insulating layer and a fourth circuit layer in a stacking way from top to bottom; at least one first metal wire is formed on the first circuit layer, at least one second metal wire is formed on the second circuit layer, and the first metal wire and the second metal wire form a first differential wire pair; forming at least one third metal wire on the third circuit layer, and forming at least one fourth metal wire on the fourth circuit layer, wherein the third metal wire and the fourth metal wire form a second differential wire pair; the two metal wires forming each differential wire pair are corresponding up and down and have different widths.
2. The circuit board of claim 1, wherein: the width of the first metal wire is larger than that of the second metal wire, and the width of the fourth metal wire is larger than that of the third metal wire.
3. The circuit board of claim 1, wherein: the two metal wires forming each differential wire pair have at least a part of paths extending in a staggered mode, and the orthographic projections of the two metal wires are located in the same projection area.
4. The circuit board of claim 3, wherein: the two metal wires forming each differential wire pair are provided with at least one part of snake-shaped path.
5. The circuit board of claim 3, wherein: one metal wire of each differential wire pair is provided with at least one part of serpentine path, the other metal wire of each differential wire pair is provided with at least one part of straight path, and the at least one part of straight path and the at least one part of serpentine path are vertically corresponding and extend in a staggered manner.
6. The circuit board of claim 5, wherein: the first metal trace has at least a part of serpentine path, and the second metal trace has at least a part of linear path.
7. The circuit board of claim 1, wherein: the insulating substrate is provided with a first surface and a second surface, and the first surface is parallel to the second surface;
the second circuit layer is a metal layer, is laid on the first surface of the insulating substrate, and is also provided with another second metal routing;
the first insulating layer covers the second circuit layer;
the first circuit layer is a metal layer, is formed on the first insulating layer, and is also provided with another first metal wire, and the another first metal wire and the another second metal wire form a third differential wire pair;
the third circuit layer is a metal layer, is formed on the second surface of the insulating substrate, and is also provided with another third metal routing;
the second insulating layer covers the third circuit layer; and
the fourth circuit layer is a metal layer, is formed on the second insulating layer, and is also formed with another fourth metal wire, and the another first metal wire and the another second metal wire form a fourth differential wire pair.
8. The circuit board of claim 7, wherein: the circuit board is also provided with a plurality of conductive through holes, each conductive through hole penetrates through the upper surface and the lower surface of the circuit board, and each conductive through hole is connected with one end of one metal routing wire.
9. An electrical connector having the circuit board of claim 1, wherein: the electric connector comprises the circuit board and a plurality of conductive terminals arranged on the circuit board; each conductive terminal is electrically connected with one end of one metal wire.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2018216798157 | 2018-10-17 | ||
| CN201821679815 | 2018-10-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209824120U true CN209824120U (en) | 2019-12-20 |
Family
ID=68871740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920112172.6U Active CN209824120U (en) | 2018-10-17 | 2019-01-23 | Circuit board and electric connector with same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209824120U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109688698A (en) * | 2018-10-17 | 2019-04-26 | 欧品电子(昆山)有限公司 | Circuit board and electric connector with the circuit board |
-
2019
- 2019-01-23 CN CN201920112172.6U patent/CN209824120U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109688698A (en) * | 2018-10-17 | 2019-04-26 | 欧品电子(昆山)有限公司 | Circuit board and electric connector with the circuit board |
| CN109688698B (en) * | 2018-10-17 | 2024-06-28 | 欧品电子(昆山)有限公司 | Circuit board and electric connector with same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101120491B (en) | Midplane epecially applicable to an orthogonal architecture electronic system | |
| CN101950893B (en) | Differential electrical connector assembly | |
| TWI549385B (en) | Circuit board for an electrical connector | |
| TWI566484B (en) | Circuits, systems and methods for implementing high speed data communications connectors that provide for reduced modal alien crosstalk in communications systems | |
| US7520757B2 (en) | Circuit board having configurable ground link and with coplanar circuit and ground traces | |
| US7658651B2 (en) | Electrical connectors and circuit boards having non-ohmic plates | |
| CN100544126C (en) | The paddle-card termination that is used for shielded cable | |
| US20060046569A1 (en) | Balanced transmission cable connector | |
| CN108736186B (en) | Electrical device having a ground bus terminated to a cable drain | |
| TW202243338A (en) | Overmolded lead frame providing contact support and impedance matching properties | |
| US20100041278A1 (en) | Electrical connector with improved compensation | |
| TWI741786B (en) | A terminal structure and an electrical connector | |
| WO2011056977A2 (en) | Multi-layer circuit member and assembly therefor | |
| JP2002117938A (en) | Connector | |
| TWI693875B (en) | Circuit board, connector assembly and cable harness | |
| JPH0154828B2 (en) | ||
| CN104488135A (en) | Multi-layer transmission lines | |
| WO2014026597A1 (en) | Communication connector and electronic device using communication connector | |
| US20100173507A1 (en) | Electrical connector having multiple ground planes | |
| CN209824120U (en) | Circuit board and electric connector with same | |
| CN109688698B (en) | Circuit board and electric connector with same | |
| CN114765330A (en) | Electrical connector and connector assembly | |
| CN110829069A (en) | Connector and combination thereof | |
| CN106257755B (en) | Connector | |
| TWM582282U (en) | Circuit board and electrical connector with the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |