CN209822634U - Wafer test circuit unit, wafer test circuit and wafer - Google Patents

Wafer test circuit unit, wafer test circuit and wafer Download PDF

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Publication number
CN209822634U
CN209822634U CN201921079091.7U CN201921079091U CN209822634U CN 209822634 U CN209822634 U CN 209822634U CN 201921079091 U CN201921079091 U CN 201921079091U CN 209822634 U CN209822634 U CN 209822634U
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pad
control
test
wafer
die
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李新
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Abstract

The disclosure relates to a wafer test circuit unit, a wafer test circuit and a wafer, wherein the wafer test circuit unit is used for wafer test, the wafer comprises a crystal grain area and a scribing way, the crystal grain area comprises at least one crystal grain, and the wafer test circuit unit comprises a test bonding pad, a control bonding pad and a parasitic resistance simulation circuit; the test pad is arranged in the scribing channel and used for inputting a test signal; the control pad is arranged on the scribing channel and used for inputting a control signal; and the parasitic resistance simulation circuit is respectively connected with the test pad, the control pad and the crystal grain, and is used for simulating the parasitic resistance outside the crystal grain and responding to the control signal to transmit the test signal to the crystal grain.

Description

Wafer test circuit unit, wafer test circuit and wafer
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a wafer test circuit unit, a wafer test circuit, and a wafer.
Background
With the development and progress of the technology, the application of the chip in various electronic products is more and more extensive, the chip is usually arranged on a printed circuit board, a crystal grain packaged inside the chip is electrically connected with an external pin through a packaging lead, and the external pin is connected with an electric signal contact point on the printed circuit board through a printed circuit board wiring.
The package lead and the Printed Circuit Board (PCB) trace both have resistors with certain resistance, that is, there is an external parasitic resistor in the die packaged in the chip. The external parasitic resistance may affect the accuracy of the signal by changing the signal input to the die, for example, by changing the current and frequency of the input signal, and further affect the normal operation of the chip.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a wafer test circuit unit, a wafer test circuit, and a wafer, so as to solve the problem of abnormal chip operation caused by a parasitic resistance outside a die in the related art to a certain extent.
According to a first aspect of the present disclosure, a wafer test circuit unit is provided for wafer testing, the wafer including a die area and a scribe lane, the die area including at least one die, the wafer test circuit unit including:
the test pad is arranged on the scribing channel and used for inputting a test signal;
the control bonding pad is arranged on the scribing channel and used for inputting a control signal;
and the parasitic resistance simulation circuit is arranged in the scribing channel, is respectively connected with the test bonding pad, the control bonding pad and the crystal grain, and is used for simulating the external parasitic resistance of the crystal grain and responding to the control signal to transmit the test signal to the crystal grain.
According to an embodiment of the present disclosure, the parasitic resistance simulation circuit includes:
and the first end of the first switch element is connected with the test pad, the second end of the first switch element is connected with the crystal grain, and the control end of the first switch element is connected with the control pad.
According to an embodiment of the present disclosure, the control pad includes:
a first control pad for inputting a first control signal;
a second control pad for inputting a second control signal;
the parasitic resistance simulation circuit further includes:
a second switch element, wherein the first end is connected with the test pad, and the second end is connected with the crystal grain;
a third switch element, wherein the first end is connected with the test pad, and the second end is connected with the crystal grain;
the test mode selection circuit is provided with two input ends and multiple output ends, wherein the first input end is connected with the first control bonding pad, the second input end is connected with the second control bonding pad, the first output end is connected with the control end of the first switch element, the second output end is connected with the control end of the second switch element, and the third output end is connected with the control end of the third switch element.
According to an embodiment of the present disclosure, the test mode selection circuit includes:
the input end of the first inverter is connected to the first control bonding pad;
the input end of the second inverter is connected to the second control bonding pad;
a first input end of the first AND gate is connected to the output end of the first inverter, a second input end of the first AND gate is connected to the second control pad, and an output end of the first AND gate is connected to the control end of the first switch element;
a first input end of the first AND gate is connected to the output end of the first inverter, a second input end of the first AND gate is connected to the first control pad, and an output end of the first AND gate is connected to the control end of the first switching element;
and a first input end of the third AND gate is connected to the first control bonding pad, a second end of the third AND gate is connected to the second control bonding pad, and an output end of the third AND gate is connected to the control end of the third switching element.
According to an embodiment of the present disclosure, the parasitic resistance simulation circuit further includes:
and a fourth switch element, wherein the first end is connected to the test pad, the second end is connected to the die, and the control end is connected to the fourth output end of the test mode selection circuit.
According to an embodiment of the present disclosure, the test mode selection circuit further includes:
and the first input end of the fourth AND gate is connected with the output end of the first phase inverter, the second input end of the fourth AND gate is connected with the output end of the second phase inverter, and the output end of the fourth AND gate is connected with the control end of the fourth switching element.
According to an embodiment of the present disclosure, the on-resistance of the first switching element, the on-resistance of the second switching element, the on-resistance of the third switching element, and the resistance of the fourth switching element are all different.
According to an embodiment of the present disclosure, the parasitic resistance simulation circuit further includes:
a first resistor connected between the second end of the first switching element and the die;
a second resistor connected between a second end of the second switching element and the die;
a third resistor connected between the second end of the third switching element and the die;
a fourth resistor connected between the second end of the fourth switching element and the die;
the first resistor, the second resistor, the third resistor and the fourth resistor are different.
According to an embodiment of the present disclosure, the parasitic resistance simulation circuit further includes:
and the first resistor is connected between the test pad and the crystal grain.
According to a second aspect of the present disclosure, a wafer test circuit is provided, which includes the wafer test circuit unit described above.
According to one embodiment of the disclosure, at least one die pad is arranged on a die, a test pad corresponds to the die pad one to one, and the wafer test circuit unit is arranged between the corresponding test pad and the die pad.
According to an embodiment of the present disclosure, the control pad is shared by the parasitic resistance simulation circuits in the wafer test circuit units.
According to a third aspect of the present disclosure, a wafer is provided, which includes the wafer test circuit described above.
According to the wafer test circuit unit, the test signal is input through the test pad, the control pad inputs the control signal, the parasitic resistance analog circuit responds to the control signal to transmit the test signal to the crystal grain, and on one hand, the crystal grain can be detected; on the other hand, the influence of the external parasitic resistance on the grain input signal in the chip is simulated through the parasitic resistance simulation circuit, the influence of the parasitic resistance simulation circuit on the input signal is detected, the detection result can provide guidance for adjusting the external input signal, the external input signal is made to adapt to the external parasitic resistance, and the problem of abnormal chip operation caused by the influence of the external parasitic resistance on the signal input to the grain of the chip is solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 is a schematic view of a wafer according to an exemplary embodiment of the present disclosure;
fig. 2 is a schematic diagram of a first wafer test circuit unit provided in an exemplary embodiment of the present disclosure;
fig. 3 is a schematic diagram of a second wafer test circuit unit provided in an exemplary embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a third wafer test circuit unit provided in an exemplary embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a first test mode selection circuit provided in an exemplary embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a fourth wafer test circuit unit according to an exemplary embodiment of the present disclosure;
fig. 7 is a schematic diagram of a fifth wafer test circuit unit provided in an exemplary embodiment of the present disclosure;
FIG. 8 is a schematic diagram of a second test mode selection circuit provided in an exemplary embodiment of the present disclosure;
FIG. 9 is a flowchart illustrating a method for testing a wafer test circuit unit according to an exemplary embodiment of the present disclosure;
fig. 10 is a schematic diagram of a wafer test circuit according to an exemplary embodiment of the disclosure.
In the figure:
10. a wafer; 11. a grain region; 12. scribing a street; 100. testing the bonding pad; 200. a control pad; 210. a first control pad; 220. a second control pad; 300. a parasitic resistance analog circuit; 310. a first switching element; 320. a second switching element; 330. a third switching element; 340. a fourth switching element; 350. a test mode selection circuit; 351. a first inverter; 352. a second inverter; 353. a first AND gate; 354. a second AND gate; 355. a third AND gate; 356. a fourth AND gate; 360. a fifth resistor; 400. a crystal grain; 410. a die pad.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in the form of software, or in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.
In the related art, Wafer level testing (Wafer Probe) is a necessary process from manufacturing to packaging of a chip, and this step is to perform a probing Test on a Die (Die) on a Wafer (Wafer) by using Automatic Test Equipment (ATE) to primarily screen out a Die whose electrical Parameters (electrical Parameters) meet design requirements.
After the die is cut from the wafer, the package is packaged, such as a QFN type package, in which the bonding pads of the die are connected to the leads of the package housing through metal wires, and the package after packaging is called a chip. The chip is generally applied to a PCB, and the PCB is also provided with metal wires to connect the chip and the chip, the chip and the battery, the chip and the sensor, and the like, thereby forming the electronic device with complete functions.
In the packaging process, the packaging lead and the PCB wiring are actually resistors with certain resistance values, which are called external parasitic resistors for the crystal grains, and the resistors can affect the performance of the chip under the conditions of large current, high frequency and the like. For example, a large current may cause a voltage drop, which may cause the voltage at the battery terminal to meet the requirement, but the pad terminal voltage of the die in the chip may not meet the requirement; further, for example, external parasitic resistance and external parasitic capacitance may form a filter, and a high frequency signal may be attenuated when transmitted. The above-listed effects are not considered in wafer level testing, and if the effect of external parasitic resistance can be considered in wafer level testing, a die with stronger Robustness (Robustness) can be screened out to reduce the packaging cost, and PCB level application of the chip can be guided to reduce the application risk.
The exemplary embodiment of the present disclosure first provides a wafer test circuit unit for wafer testing, as shown in fig. 1, the wafer 10 includes a die area 11 and a scribe lane 12, the die area 11 includes at least one die 400, as shown in fig. 2, the wafer test circuit unit includes a test pad 100, a control pad 200 and a parasitic resistance simulation circuit 300; the test pad 100 is arranged on the scribing street 12 and used for inputting a test signal; the control pad 200 is arranged on the scribing channel 12 and used for inputting a control signal; the parasitic resistance simulation circuit 300 is respectively connected to the test pad 100, the control pad 200 and the die 400, and is configured to simulate a parasitic resistance outside the die 400 and transmit the test signal to the die 400 in response to the control signal.
According to the wafer test circuit unit provided by the embodiment of the disclosure, the test pad 100 inputs a test signal, the control pad 200 inputs a control signal, and the parasitic resistance analog circuit 300 responds to the control signal to transmit the test signal to the crystal grain 400, so that on one hand, the crystal grain can be detected, and the crystal grain with stronger robustness can be screened out; on the other hand, the influence of the external parasitic resistance on the input signal of the die 400 in the chip is simulated through the parasitic resistance simulation circuit 300, the influence of the parasitic resistance simulation circuit 300 on the input signal is detected, the detection result can provide guidance for adjusting the external input signal, so that the external input signal adapts to the external parasitic resistance, and the problem of abnormal chip operation caused by the influence of the external parasitic resistance on the signal input to the die 400 of the chip is solved.
The following will describe each component in the wafer test circuit unit provided by the embodiments of the present disclosure in detail:
as shown in fig. 3, the parasitic resistance simulation circuit 300 includes a first switch element 310, a first terminal of the first switch element 310 is connected to the test pad 100, a second terminal of the first switch element 310 is connected to the die 400, and a control terminal is connected to the control pad 200. The die 400 is provided with a die pad 410, and the second end of the first switching element 310 is connected to the die pad 410. The first switching element 310 is turned on in response to the control signal to transmit the test signal to the die 400. The first switching element 310 has impedance when turned on, and thus external parasitic resistance of the chip can be simulated by the first switching element 310. When the test signal passes through the first switch element 310, the test signal may change due to the influence of the on-resistance, and at this time, the influence of the external parasitic resistance on the response result is determined by detecting the response result of the die 400 receiving the changed test signal, so as to adjust the input signal, so that the die 400 responds to the input signal to obtain an expected response result.
For example, when the die pad 410 is a power signal receiving pad, due to the on-resistance of the first switching element 310, the voltage of the power signal transmitted to the die pad 410 is insufficient, and at this time, the power voltage received by the die 400 may be detected, an error between the power voltage and an expected power voltage may be determined, and the voltage of the externally input power signal may be adjusted to ensure that the power voltage transmitted to the die 400 meets the expected value.
As shown in fig. 4, the control pad 200 may include a first control pad 210 and a second control pad 220, the first control pad 210 being used to input a first control signal; the second control pad 220 is used for inputting a second control signal, and the first control pad 210 and the second control pad 220 are both disposed on the scribe lane 12.
On this basis, the parasitic resistance simulation circuit 300 further includes a second switching element 320, a third switching element 330, and a test mode circuit. A first terminal of the second switching element 320 is connected to the test pad 100, and a second terminal of the second switching element 320 is connected to the die 400; a first end of the third switching element 330 is connected to the test pad 100, and a second end of the third switching element 330 is connected to the die 400; the test mode selection circuit 350 has two input terminals and two output terminals, the first input terminal is connected to the first control pad 210, the second input terminal is connected to the second control pad 220, the first output terminal of the test mode selection circuit 350 is connected to the control terminal of the first switch element 310, the second output terminal of the test mode selection circuit 350 is connected to the control terminal of the second switch element 320, and the third output terminal of the test mode selection circuit 350 is connected to the control terminal of the third switch element 330.
As shown in fig. 5, the test mode selection circuit 350 includes a first inverter 351, a second inverter 352, a first and gate 353, a second and gate 354, and a third and gate 355. The input end of the first inverter 351 is connected to the first control pad 210; the input end of the second inverter 352 is connected to the second control pad 220; a first input terminal of the first and gate 353 is connected to the output terminal of the first inverter 351, a second input terminal of the first and gate 353 is connected to the second control pad 220, and an output terminal of the first and gate 353 is connected to the control terminal of the first switching element 310; a first input terminal of the second and gate 354 is connected to the output terminal of the second inverter 352, a second input terminal of the second and gate 354 is connected to the first control pad 210, and an output terminal of the second and gate 354 is connected to the control terminal of the second switching element 320; a first input terminal of the third and gate 355 is connected to the first steering pad 210, a second terminal of the third and gate 355 is connected to the second steering pad 220, and an output terminal of the third and gate 355 is connected to a control terminal of the third switching element 330. The output end of the first and gate 353 is a first output stage of the test mode selection circuit 350, the output end of the second and gate 354 is a second output stage of the test mode selection circuit 350, and the output end of the third and gate 355 is a third output stage of the test mode selection circuit 350.
It can be noted that the first control signal input by the first control pad 210 is a, the second control signal input by the second control pad 220 is B, and the signal output by the output terminal of the test mode selection circuit 350 is the first output signalSecond output signalAnd a third output signal AB. The control signal input and the output control signal of the test mode selection circuit 350 are shown in table 1.
TABLE 1
As can be seen from the above table, the test mode selection circuit 350 outputs a control signal to control the first switching element 310, the second switching element 320 and the third switching element 330 to be turned on under different control signals, so as to simulate different external parasitic resistances and provide different test environments.
Further, as shown in fig. 7, the parasitic resistance simulation circuit 300 may further include a fourth switching element 340, a first terminal of the fourth switching element 340 is connected to the test pad 100, a second terminal of the fourth switching element 340 is connected to the die 400, and a control terminal of the fourth switching element 340 is connected to a fourth output terminal of the test mode selection circuit 350.
On this basis, as shown in fig. 8, the test mode selection circuit 350 further includes a fourth and gate 356, a first input terminal of the fourth and gate 356 is connected to the output terminal of the first inverter 351, a second input terminal of the fourth and gate 356 is connected to the output terminal of the second inverter 352, and an output terminal of the fourth and gate 356 is connected to the control terminal of the fourth switching element 340. When the first control signal inputted from the first control pad 210 is a and the second control signal inputted from the second control pad 220 is B, the signals outputted from the output terminal of the fourth and gate 356 and the fourth output terminal of the test mode selection circuit 350 are aAt this time, the control signal input and the output control signal from the test mode selection circuit 350 are as shown in table 2.
TABLE 2
As can be seen from the above table, the test mode selection circuit 350 outputs a control signal to control the first switching element 310, the second switching element 320, the third switching element 330 and the fourth switching element 340 to be turned on under different control signals, so as to simulate different external parasitic resistances and provide different test environments.
In order to simulate various external parasitic resistances, the on-resistance of the first switching element 310, the on-resistance of the second switching element 320, the on-resistance of the third switching element 330, and the resistance of the fourth switching element 340 are all different. Due to the fact that the conduction impedances of the switch elements are different, when the switch elements are respectively conducted, the influence on input signals is different, the wafer test circuit is better in adaptability and suitable for various test scenes.
Certainly, in practical applications, the on-resistances of the plurality of switching elements may also be the same, so as to facilitate the fabrication of the switching elements, in this case, the parasitic resistance simulation circuit 300 may further include: the circuit comprises a first resistor, a second resistor, a third resistor and a fourth resistor. A first resistor is connected between the second terminal of the first switching element 310 and the die 400; a second resistor is connected between a second terminal of the second switching element 320 and the die 400; a third resistor is connected between the second end of the third switching element 330 and the die 400; a fourth resistor is connected between the second end of the fourth switching element 340 and the die 400; the first resistor, the second resistor, the third resistor and the fourth resistor are different. Alternatively, resistors may be connected to some of the switching elements, and resistors may not be connected to the remaining switching elements, for example, the second terminal of the first switching element 310 is connected to the die pad 410, the second terminal of the second switching element 320 is connected to the second resistor, the second terminal of the third switching element 330 is connected to the third resistor, and the second terminal of the fourth switching element 340 is connected to the fourth resistor.
As shown in fig. 6, the parasitic resistance simulation circuit 300 may further include a fifth resistor 360, and the fifth resistor 360 is connected between the test pad 100 and the die 400. That is, the fifth resistor 360 is connected in parallel with each switching element, and the fifth resistor 360 can operate under the condition that a plurality of switching elements are all turned off, so that the adaptability of the wafer test circuit is improved.
In this example embodiment, the first to fourth switching units may correspond to first to fourth transistors, respectively, each having a control terminal, a first terminal, and a second terminal. Each transistor may be an N-type transistor, a P-type transistor, or a transmission gate. Specifically, the control terminal of each transistor may be a gate, the first terminal may be a source, and the second terminal may be a drain; alternatively, the control terminal of each transistor may be a gate, the first terminal may be a drain, and the second terminal may be a source. Further, each transistor may be an enhancement transistor or a depletion transistor, which is not particularly limited in this exemplary embodiment. The on-resistances of the first to fourth transistors provided in the embodiments of the present disclosure may be in the milliohm range, the resistances of the first to fifth resistors may be in the milliohm range, and each resistor may be a metal resistor or a polysilicon resistor.
A first transistor having a first terminal connected to the test pad 100, a second terminal connected to a die pad 410 of the die 400, and a control terminal connected to the first output terminal of the test mode selection circuit 350.
A second transistor having a first terminal connected to the test pad 100, a second terminal connected to a die pad 410 on the die 400, and a control terminal connected to the second output terminal of the test mode selection circuit 350.
A third transistor having a first terminal connected to the test pad 100, a second terminal connected to a die pad 410 of the die 400, and a control terminal connected to the third output terminal of the test mode selection circuit 350.
A fourth transistor having a first terminal connected to the test pad 100, a second terminal connected to a die pad 410 on the die 400, and a control terminal connected to the fourth output terminal of the test mode selection circuit 350.
The wafer test circuit unit provided by the embodiment of the disclosure inputs a test signal through the test pad 100, inputs a control signal through the control pad 200, the parasitic resistance simulation circuit 300 responds to the control signal to transmit the test signal to the die 400, simulates the influence of an external parasitic resistance on the input signal of the die 400 in a chip through the parasitic resistance simulation circuit 300, detects the influence of the parasitic resistance simulation circuit 300 on the input signal, and the detection result can provide guidance for adjusting the external input signal, so that the external input signal adapts to the external parasitic resistance, and further solves the problem of abnormal chip operation caused by the influence of the external parasitic resistance on the signal input to the die 400 of the chip.
The exemplary embodiment of the present disclosure further provides a testing method of a wafer test circuit unit, which is used for the wafer test circuit unit, as shown in fig. 9, the testing method includes the following steps:
step S910, inputting a test signal by using the test pad 100;
step S920, inputting a control signal by using the control pad 200;
in step S930, the test signal is transmitted to the die 400 through the parasitic resistance simulation circuit 300 according to the control signal.
According to the test method of the wafer test circuit unit provided by the embodiment of the disclosure, a test signal is input through the test pad 100, a control signal is input through the control pad 200, the parasitic resistance simulation circuit 300 responds to the control signal to transmit the test signal to the crystal grain 400, the influence of the external parasitic resistance on the input signal of the crystal grain 400 in the chip is simulated through the parasitic resistance simulation circuit 300, the influence of the parasitic resistance simulation circuit 300 on the input signal is detected, the detection result can provide guidance for adjusting the external input signal, so that the external input signal adapts to the external parasitic resistance, and the problem of abnormal chip operation caused by the influence of the external parasitic resistance on the signal input to the crystal grain 400 of the chip is further solved.
In step S910, a test signal may be input using the test pad 100. Wherein the test pad 100 is disposed on the scribe line 12, and the test signal may be a voltage signal or a current signal.
In step S920, a control signal may be input using the control pad 200. Wherein, when the control pad 200 includes the first control pad 210 and the second control pad 220, the control signal includes a first control signal and a second control signal.
In step S930, the test signal may be transmitted to the die 400 through the parasitic resistance simulation circuit 300 according to the control signal.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Under the control of the control signal, the test signal is transmitted to the die 400 through the parasitic resistance simulation circuit 300, the parasitic resistance simulation circuit 300 simulates the external parasitic resistance of the chip, the test signal changes, the die 400 responds to the changed test signal, detects the die 400, compares the detection structure with the expected result, and further feeds back and guides to adjust the test signal to obtain the expected test result. That is, the test signal corresponding to the expected test result is obtained, so that the correct input signal is input in practical application, and the problem of abnormal chip operation caused by an external parasitic circuit is solved.
The specific details of each testing method are already described in detail in the corresponding wafer test circuit unit, and therefore are not described herein again.
The exemplary embodiment of the present disclosure further includes a wafer test circuit, which includes the wafer test circuit unit. As shown in fig. 10, the wafer die area 11 includes a plurality of dies 400, each die 400 is provided with at least one die pad 410, the test pads 100 correspond to the die pads 410 one by one, and the wafer test circuit unit is disposed between the test pads 100 and the die pads 410. The test pads 100 are cut to be distributed in an array.
A plurality of die pads 410 may be disposed at an edge region of the die 400, the parasitic resistance simulation circuit 300 connected to the die pads 410 is disposed at a region near the scribe streets 12 near a side of the die pads 410, and the test pad 100 is disposed at a side of the parasitic resistance simulation circuit 300 away from the die 400.
The parasitic resistance simulation circuit 300 in a plurality of the wafer test circuit units shares the control pad 200. The control pad 200 may simultaneously supply the control signals to the plurality of parasitic resistance simulation circuits 300 or separately supply the control signals to the plurality of parasitic resistance simulation circuits 300.
In one possible embodiment of the present disclosure, the plurality of parasitic resistance simulation circuits 300 are commonly connected to the control pad 200. When the parasitic resistance simulation circuit 300 includes the test mode selection circuit 350, the control pad 200 includes a first control pad 210 and a second control pad 220, first input terminals of the plurality of test mode selection circuits 350 are connected to the same first control pad 210, and second input terminals of the plurality of test mode selection circuits 350 are connected to the same second control pad 220.
The wafer test circuit provided by the embodiment of the disclosure inputs a test signal through the test pad 100, inputs a control signal through the control pad 200, the parasitic resistance simulation circuit 300 responds to the control signal to transmit the test signal to the die 400, simulates the influence of an external parasitic resistance on the input signal of the die 400 in a chip through the parasitic resistance simulation circuit 300, detects the influence of the parasitic resistance simulation circuit 300 on the input signal, and the detection result can provide guidance for adjusting the external input signal to make the external input signal adapt to the external parasitic resistance, thereby solving the problem of abnormal chip operation caused by the influence of the external parasitic resistance on the signal input to the die 400 of the chip.
The exemplary embodiments of the present disclosure also include a wafer including the wafer test circuit described above.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims (13)

1. A wafer test circuit unit for wafer test, the wafer includes a die area and a scribe lane, the die area includes at least one die, the wafer test circuit unit includes:
the test pad is arranged on the scribing channel and used for inputting a test signal;
the control bonding pad is arranged on the scribing channel and used for inputting a control signal;
and the parasitic resistance simulation circuit is arranged in the scribing channel, is respectively connected with the test bonding pad, the control bonding pad and the crystal grain, and is used for simulating the external parasitic resistance of the crystal grain and responding to the control signal to transmit the test signal to the crystal grain.
2. The wafer test circuit unit of claim 1, wherein the parasitic resistance simulation circuit comprises:
and the first end of the first switch element is connected with the test pad, the second end of the first switch element is connected with the crystal grain, and the control end of the first switch element is connected with the control pad.
3. The wafer test circuit unit of claim 2, wherein the control pad comprises:
a first control pad for inputting a first control signal;
a second control pad for inputting a second control signal;
the parasitic resistance simulation circuit further includes:
a second switch element, wherein the first end is connected with the test pad, and the second end is connected with the crystal grain;
a third switch element, wherein the first end is connected with the test pad, and the second end is connected with the crystal grain;
the test mode selection circuit is provided with two input ends and multiple output ends, wherein the first input end is connected with the first control bonding pad, the second input end is connected with the second control bonding pad, the first output end is connected with the control end of the first switch element, the second output end is connected with the control end of the second switch element, and the third output end is connected with the control end of the third switch element.
4. The wafer test circuit unit of claim 3, wherein the test mode selection circuit comprises:
the input end of the first inverter is connected to the first control bonding pad;
the input end of the second inverter is connected to the second control bonding pad;
a first input end of the first AND gate is connected to the output end of the first inverter, a second input end of the first AND gate is connected to the second control pad, and an output end of the first AND gate is connected to the control end of the first switch element;
a first input end of the first AND gate is connected to the output end of the first inverter, a second input end of the first AND gate is connected to the first control pad, and an output end of the first AND gate is connected to the control end of the first switching element;
and a first input end of the third AND gate is connected to the first control bonding pad, a second end of the third AND gate is connected to the second control bonding pad, and an output end of the third AND gate is connected to the control end of the third switching element.
5. The wafer test circuit unit of claim 4, wherein the parasitic resistance simulation circuit further comprises:
and a fourth switch element, wherein the first end is connected to the test pad, the second end is connected to the die, and the control end is connected to the fourth output end of the test mode selection circuit.
6. The wafer test circuit unit of claim 5, wherein the test mode selection circuit further comprises:
and the first input end of the fourth AND gate is connected with the output end of the first phase inverter, the second input end of the fourth AND gate is connected with the output end of the second phase inverter, and the output end of the fourth AND gate is connected with the control end of the fourth switching element.
7. The wafer test circuit unit as recited in claim 6, wherein the on-resistance of the first switch element, the on-resistance of the second switch element, the on-resistance of the third switch element and the resistance of the fourth switch element are different.
8. The wafer test circuit unit of claim 6, wherein the parasitic resistance simulation circuit further comprises:
a first resistor connected between the second end of the first switching element and the die;
a second resistor connected between a second end of the second switching element and the die;
a third resistor connected between the second end of the third switching element and the die;
a fourth resistor connected between the second end of the fourth switching element and the die;
the first resistor, the second resistor, the third resistor and the fourth resistor are different.
9. The wafer test circuit unit of any one of claims 2-8, wherein the parasitic resistance simulation circuit further comprises:
and the fifth resistor is connected between the test pad and the crystal grain.
10. A wafer test circuit, characterized in that the wafer test circuit comprises the wafer test circuit unit according to any one of claims 1-9.
11. The wafer test circuit as claimed in claim 10, wherein at least one die pad is disposed on a die, a test pad is in one-to-one correspondence with the die pad, and the wafer test circuit unit is disposed between the corresponding test pad and the die pad.
12. The wafer test circuit as claimed in claim 11, wherein the parasitic resistance simulation circuit in a plurality of the wafer test circuit units shares a control pad.
13. A wafer comprising the wafer test circuit of any of claims 10-12.
CN201921079091.7U 2019-07-10 2019-07-10 Wafer test circuit unit, wafer test circuit and wafer Active CN209822634U (en)

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Publication Number Publication Date
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