CN209822618U - Packaging structure without outer pin - Google Patents
Packaging structure without outer pin Download PDFInfo
- Publication number
- CN209822618U CN209822618U CN201920653876.4U CN201920653876U CN209822618U CN 209822618 U CN209822618 U CN 209822618U CN 201920653876 U CN201920653876 U CN 201920653876U CN 209822618 U CN209822618 U CN 209822618U
- Authority
- CN
- China
- Prior art keywords
- chip
- dust cover
- base
- groove
- dust
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- 239000000428 dust Substances 0.000 claims abstract description 52
- 238000007789 sealing Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model belongs to the technical field of chip packaging, especially, be a packaging structure of no outer pin, including base, chip holder and lead frame all fixed mounting are in the upper surface of base, the lead frame is located one side of the chip holder, the upper surface of base block joint has the dust cover, and the dust cover is located the outside of dust cover, the inside top surface of dust cover has the heat conduction strip, be provided with the insulating layer between chip holder and the base, set up the chip groove on the chip holder, the lead groove has been seted up to the inside bottom surface in chip groove; this packaging structure of no outer pin can effectually prevent dust to the chip to avoid dust and chip contact, influence the work efficiency and the life of chip, simultaneously can effectually dredge the dust guard with the heat on the chip on, thereby increase the heat radiating area of chip, improve its radiating efficiency.
Description
Technical Field
The utility model belongs to the technical field of the chip package, concretely relates to packaging structure of no outer pin.
Background
Nowadays, in order to meet the demands of various high-density packages, various types of package structures are gradually developed, wherein various System In Package (SIP) design concepts are commonly used to construct the high-density package structures. Generally, a system in package (soc) is divided into a multi-chip module (MCM), a Package On Package (POP), a Package In Package (PIP), and the like.
The prior art has the following problems:
1. the packaging structure of a common semiconductor is exposed and leaked outside, so that external dust is easily polluted, and the working efficiency and the service life of the semiconductor are influenced;
2. the heat dissipation efficiency is low, which often causes the damage of the semiconductor and influences the normal work of the chip.
SUMMERY OF THE UTILITY MODEL
To solve the problems set forth in the background art described above. The utility model provides a packaging structure of no outer pin has high-efficient dustproof and heat dissipation characteristics.
In order to achieve the above object, the utility model provides a following technical scheme: the utility model provides a packaging structure of no outer pin, includes base, chip carrier and lead frame, the equal fixed mounting of chip carrier and lead frame is in the upper surface of base, the lead frame is located one side of chip carrier, the upper surface snap-fit of base is connected with the dust cover, just the dust cover is located the outside of dust cover, the inside top surface of dust cover has the heat conduction strip, the chip carrier with be provided with the insulating layer between the base, set up the chip groove on the chip carrier, the pin groove has been seted up to the inside bottom surface in chip groove.
Preferably, the upper surface of the base is provided with a clamping groove corresponding to the dust cover.
Preferably, the outer wall of the dust cover is provided with a sealing strip, and the sealing strip is made of rubber materials.
Preferably, the lead frame comprises a cap and a cap, a support column is fixedly mounted on the upper surface of the base, and the cap is screwed on the top end of the support column.
Preferably, notches are formed in two end edges of the chip groove.
Preferably, one surface of the joint of the cap and the support column is concave.
Compared with the prior art, the beneficial effects of the utility model are that:
1. according to the packaging structure without the outer pins, the dust cover and the clamping groove are arranged, and the dust cover is clamped on the base through the clamping groove, so that the normal packaging of the chip is not influenced, meanwhile, the chip can be effectively prevented from dust, and therefore, the dust is prevented from contacting the chip, and the working efficiency and the service life of the chip are prevented from being influenced;
2. this packaging structure of no outer pin is through setting up heat conduction strip, can effectually dredge the heat on the chip to the shield to increase the heat radiating area of chip, improve its radiating efficiency.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural view of the present invention;
fig. 2 is a schematic top view of the base of the present invention;
FIG. 3 is a schematic structural view of a chip holder according to the present invention;
FIG. 4 is an enlarged schematic view of the structure of FIG. 1;
in the figure: 1. a base; 101. a card slot; 2. a dust cover; 201. a heat conducting strip; 202. a sealing strip; 3. A chip holder; 301. a chip slot; 302. a notch; 303. a lead groove; 4. an insulating layer; 5. a lead frame; 501. a support pillar; 502. and (7) capping.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Example 1
Referring to fig. 1-4, the present invention provides the following technical solutions: the utility model provides a packaging structure of no outer pin, which comprises a base 1, chip carrier 3 and lead frame 5, the equal fixed mounting of chip carrier 3 and lead frame 5 is at the upper surface of base 1, lead frame 5 is located one side of chip carrier 3, the upper surface joint of base 1 is connected with dust cover 2, and dust cover 2 is located the outside of dust cover 2, the inside top surface of dust cover 2 has heat conduction strip 201, be provided with insulating layer 4 between chip carrier 3 and the base 1, set up chip groove 301 on the chip carrier 3, pin groove 303 has been seted up to the inside bottom surface of chip groove 301.
In this embodiment, heat conduction strip 201 adopts red copper to make, and dust cover 2 adopts metal material to make, dredges the heat on the chip to metal dust cover 2 through heat conduction strip 201 on, the heat radiating area of increase chip to improve its radiating efficiency.
In this embodiment, the insulating layer 4 is made of an insulating material, so that the chip holder 3 can be effectively isolated from the base 1, and the base 1 is prevented from being electrified due to the contact between the chip pins and the base 1.
In this embodiment: by arranging the dust cover 2 and the clamping groove 101, the dust cover 2 is clamped on the base 1 through the clamping groove 101, so that the normal packaging of the chip is not influenced, and meanwhile, the chip can be effectively prevented from dust, thereby avoiding the contact of dust and the chip and influencing the working efficiency and the service life of the chip; through setting up heat conduction strip 201, can effectually dredge the heat on the chip to dust cover 2 to increase the heat radiating area of chip, improve its radiating efficiency.
Specifically, the upper surface of the base 1 is provided with a clamping groove 101 corresponding to the dust cover 2; dust cover 2 passes through draw-in groove 101 block on base 1 to protect chip carrier 3, when the encapsulation, can take off dust cover 2 and encapsulate, the maintenance in the later stage of being convenient for.
Specifically, the outer surface wall of the dust cover 2 is provided with a sealing strip 202, and the sealing strip 202 is made of rubber material; through setting up sealing strip 202, use sealing strip 202 to seal the gap between dust cover 2 and the base 1, avoid outside dust to pile up in draw-in groove 101, influence the normal use of draw-in groove 101.
Specifically, the lead frame 5 comprises a cap 502 and a cap 502, a support column 501 is fixedly mounted on the upper surface of the base 1, and the cap 502 is screwed on the top end of the support column 501; the lead frame 5 is used for wiring, and during wiring, the lead is pressed on the supporting column 501 through the cap 502, so that the wiring work of the lead is completed.
Specifically, notches 302 are formed in two end edges of the chip slot 301; the chip is convenient to take by arranging the notch 302 on the edge of the chip groove 301.
Specifically, one surface of the joint of the cap 502 and the support column 501 is concave; the cap 502 adopts a concave design, so that the wires can be effectively covered, the exposed area of the wires is reduced, and the wiring is more attractive.
The utility model discloses a theory of operation and use flow: the during operation, protect the chip through dust cover 2, outside dust falls on dust cover 2, it is isolated with the dust through dust cover 2, avoid the dust and chip on the chip seat 3 and the wire contact on the lead frame 5, thereby effectually prevent dust, avoid being infected with the chip because of the dust, thereby the life of chip has been improved, dredge dust cover 2 through leading heat strip 201 with the heat on the chip, through dust cover 2 and outside air contact, thereby make the heat give off, can effectual increase the heat radiating area of chip, improve its radiating efficiency.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. The utility model provides a packaging structure of no outer pin, includes base (1), chip holder (3) and lead frame (5), the equal fixed mounting of chip holder (3) and lead frame (5) is in the upper surface of base (1), lead frame (5) are located one side of chip holder (3), its characterized in that: the upper surface snap-fit of base (1) is connected with dust cover (2), just dust cover (2) are located the outside of dust cover (2), the inside top surface of dust cover (2) has heat conduction strip (201), chip seat (3) with be provided with insulating layer (4) between base (1), offer chip groove (301) on chip seat (3), pin groove (303) have been seted up to the inside bottom surface in chip groove (301).
2. The leadless package structure of claim 1, wherein: the upper surface of the base (1) is provided with a clamping groove (101) corresponding to the dust cover (2).
3. The leadless package structure of claim 1, wherein: the outer surface wall of the dust cover (2) is provided with a sealing strip (202), and the sealing strip (202) is made of rubber materials.
4. The leadless package structure of claim 1, wherein: the lead frame (5) comprises a cover cap (502) and a cover cap (502), a support column (501) is fixedly mounted on the upper surface of the base (1), and the cover cap (502) is screwed on the top end of the support column (501).
5. The leadless package structure of claim 1, wherein: notches (302) are arranged on two end edges of the chip groove (301).
6. The leadless package structure of claim 4, wherein: one surface of the joint of the cap (502) and the support column (501) is concave.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920653876.4U CN209822618U (en) | 2019-05-09 | 2019-05-09 | Packaging structure without outer pin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920653876.4U CN209822618U (en) | 2019-05-09 | 2019-05-09 | Packaging structure without outer pin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209822618U true CN209822618U (en) | 2019-12-20 |
Family
ID=68882877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920653876.4U Expired - Fee Related CN209822618U (en) | 2019-05-09 | 2019-05-09 | Packaging structure without outer pin |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209822618U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113747713A (en) * | 2021-09-03 | 2021-12-03 | 深圳市永利杰科技有限公司 | Prevent falling excellent performance's memory chip |
-
2019
- 2019-05-09 CN CN201920653876.4U patent/CN209822618U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113747713A (en) * | 2021-09-03 | 2021-12-03 | 深圳市永利杰科技有限公司 | Prevent falling excellent performance's memory chip |
| CN113747713B (en) * | 2021-09-03 | 2022-11-04 | 启芯半导体(深圳)有限公司 | Prevent falling excellent performance's memory chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20191220 |