CN209821627U - Multichannel strain signal synchronous acquisition system - Google Patents
Multichannel strain signal synchronous acquisition system Download PDFInfo
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- CN209821627U CN209821627U CN201920683800.6U CN201920683800U CN209821627U CN 209821627 U CN209821627 U CN 209821627U CN 201920683800 U CN201920683800 U CN 201920683800U CN 209821627 U CN209821627 U CN 209821627U
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Abstract
The utility model relates to a multichannel strain signal synchronous acquisition system and a method, which belongs to the field of electronic technology measurement; the system comprises a voltage reference proportion conversion circuit, a program control setting module, a driving circuit, a Wheatstone strain bridge, an amplifying circuit, an anti-aliasing filter circuit, an A/D synchronous acquisition circuit, an isolation module and a microprocessor system; the voltage of the voltage reference proportional transformation circuit is provided for the driving circuit through the program control setting module, the driving circuit drives the Wheatstone strain bridge to amplify and filter the strain signal through the amplifying circuit and the anti-aliasing filter circuit, then the analog signal is converted into a digital signal through the A/D synchronous acquisition circuit and the digital isolation, and finally the digital signal is transmitted to the microprocessor system through the SPI interface to be processed; the utility model provides a multichannel strain signal drive circuit and AD analog-to-digital synchronous conversion framework need not the electrical isolation between each passageway, need not a plurality of analog-to-digital conversion chips, need not the conversion data storage and the transmission circuit of extension, has reduced the size, has practiced thrift the cost.
Description
Technical Field
The invention discloses a multichannel strain signal synchronous acquisition system, and belongs to the field of electronic technology measurement.
Background
In production life and scientific research, physical parameters such as weight, pressure, vibration and the like are often required to be measured in real time, and real-time information of multiple points is required to be synchronously acquired so as to perform time domain and frequency domain analysis of measurement or signals, for example, monitoring of a large bridge, vibration signals of multiple points are required to be simultaneously acquired to analyze distribution of traffic flow, resonance frequency of the bridge, and monitoring of buildings are also required to monitor vibration and analyze physical characteristics of the bridge.
The traditional multichannel strain signal synchronous acquisition device is shown in fig. 1, and as can be seen from fig. 1, because of the discreteness of the resistance values of all wheatstone strain bridges, in order to ensure high-precision measurement, each channel needs an independent A/D and complete wheatstone strain bridge signal conditioning circuit and a special conversion data transmission link circuit, so that the circuit is complex, the cost is high, and the physical size is large.
The invention provides a multichannel strain signal synchronous acquisition system, which aims to solve the problem of the traditional multichannel strain signal synchronous acquisition system.
Disclosure of Invention
The invention discloses a multichannel strain signal synchronous acquisition system and a multichannel strain signal synchronous acquisition method, aiming at the problems of complex circuit, high cost and large physical size of the traditional multichannel strain signal synchronous acquisition device.
The purpose of the invention is realized as follows:
a multichannel strain signal synchronous acquisition system comprises a voltage reference proportion conversion circuit, a program control setting module, a driving circuit, a Wheatstone strain bridge, an amplifying circuit, an anti-aliasing filter circuit, an A/D synchronous acquisition circuit, an isolation module and a microprocessor system;
voltage of voltage reference proportional transformation circuit provides drive circuit through programme-controlled setting module, and drive circuit drive Wheatstone strain bridge passes through amplifier circuit and anti-aliasing filter circuit with the signal of meeting an emergency and amplifies the filtering, and the synchronous acquisition circuit of rethread AD and digital isolation convert analog signal into digital signal, transmit for microprocessor system through the SPI interface at last and handle.
In the multi-channel strain signal synchronous acquisition system, the voltage reference proportional transformation circuit comprises a voltage reference, a noise reduction filter circuit and a logic circuit;
the voltage reference adopts ADR02, ADR4550, REF5050 or other compatible reference chips;
the noise reduction filter circuit performs noise reduction filtering on the voltage reference and outputs 5V reference voltage;
the logic circuit comprises a U3 chip, a U4 chip, a U5 chip and a 3 x 8 resistor network; the U3 chip, the U4 chip and the U5 chip are all operational amplifier chips, OPA2277, AD706 or other precision dual operational amplifier chips with similar performance are selected, the non-inverting input end of the U3 chip-B is connected with the output end of the noise reduction filter circuit, the inverting input end of the U3 chip-B is defined as VP4 and is connected with the output end of the U3 chip-B, and the output end of the U3 chip-B is connected with the left side of the first column of the resistance network; the non-inverting input end of the U3 chip-A is grounded, the inverting input end of the U3 chip-A is connected with the junction of the fourth column and the fifth column of the resistor network, the output end of the U3 chip-A is defined as VN4, and the output end of the U3 chip-A is connected with the right side of the eighth column of the resistor network; the non-inverting input end of the U4 chip-A is connected with the boundary of the third column and the fourth column of the resistor network, and the inverting input end of the U4 chip-A is connected with the output end of the U4 chip-A, which is defined as VP 1; the non-inverting input end of the U4 chip-B is connected with the boundary of the second column and the third column of the resistor network, and the inverting input end of the U4 chip-B is connected with the output end of the U4 chip-B, which is defined as VP 2; the non-inverting input end of the U5 chip-A is connected with the boundary of the sixth column and the seventh column of the resistor network, and the inverting input end of the U5 chip-A is connected with the output end of the U5 chip-A, which is defined as VN 2; the non-inverting input terminal of the U5 chip-B is connected to the boundary of the fifth column and the sixth column of the resistor network, and the inverting input terminal of the U5 chip-B is connected to the output terminal of the U5 chip-B, which is defined as VN 1.
In the above multichannel synchronous acquisition system for strain signals, the driving circuit and the wheatstone strain bridge form a wheatstone strain bridge driving circuit, as follows:
the double-four-one-by-one analog switch U1i chip comprises a U1i chip, wherein an X0 port is connected with AGND, an X1 port is connected with VP1, an X2 port is connected with VP2, an X3 port is connected with VP4, a Y0 port is connected with AGND, a Y1 port is connected with VN1, a Y2 port is connected with VN2, a Y3 port is connected with VN4, an X port is connected with a non-inverting input end of a U2i chip-A, a Y port is connected with a non-inverting input end of a U2i chip-B, an A port is defined as SETAi, a B port is defined as SETBi, and the A port and the B port are; the double-four-out-of-one analog switch U1i chip is 74HC4052, ADG659 or ADG409, the U2i chip is an operational amplifier chip, and OPA2277, AD706 or other precision double operational amplifier chips with similar performance are selected;
the inverting input end of the U2i chip-A is defined as SNi +, the output end is connected with the base electrode of the first triode through a resistor, the collector electrode of the first triode is connected with a +9V power supply through a resistor, and the emitter electrode of the first triode is defined as EXi + and is connected with SNi +; the inverting input end of the U2i chip-B is defined as SNi-, the output end is connected with the base electrode of the second triode through a resistor, the collector electrode of the second triode is connected with a-9V power supply through a resistor, the emitter electrode of the second triode is defined as EXi-, and is connected with SNi-;
the U2i chip is an operational amplifier chip, and the U2i chip-A and the U2i chip-B are respectively connected into a voltage follower;
the wheatstone strain bridge is composed of four resistors, wherein one diagonal is respectively defined as AIi + and AIi-, and the other diagonal is respectively defined as SNi + and SNi-.
In the multichannel strain signal synchronous acquisition system, the amplifying circuit comprises a Ui3 chip, the Ui3 chip is a zero-drift operational amplifier chip, and OPA2187, ADA4522-2 or other zero-drift double operational amplifier chips with similar performance are adopted;
the non-inverting input end of the Ui3 chip-A is defined as AIi +, the inverting input end of the Ui3 chip-A is defined as VOPi, and the output end of the Ui3 chip-A is connected with a resistor network Ri1 formed by connecting four resistors in series;
the non-inverting input end of the Ui3 chip-B is defined as AIi, the inverting input end of the Ui3 chip-B is defined as VONi, and the output end of the Ui3 chip-B is connected with a resistor network Ri2 formed by connecting four resistors in series;
the inverting input end of the Ui3 chip-A and the inverting input end of the Ui3 chip-B are connected through a resistor network Ri3 formed by four resistors in parallel.
In the multichannel strain signal synchronous acquisition system, the pins or ports with the same definition are connected together.
A voltage reference proportion conversion circuit for a multichannel strain signal synchronous acquisition system comprises a voltage reference, a noise reduction filter circuit and a logic circuit;
the voltage reference adopts ADR02, ADR4550, REF5050 or other compatible reference chips;
the noise reduction filter circuit performs noise reduction filtering on the voltage reference and outputs 5V reference voltage;
the logic circuit comprises a U3 chip, a U4 chip, a U5 chip and a 3 x 8 resistor network; the U3 chip, the U4 chip and the U5 chip are all operational amplifier chips, OPA2277, AD706 or other precision dual operational amplifier chips with similar performance are selected, the non-inverting input end of the U3 chip-B is connected with the output end of the noise reduction filter circuit, the inverting input end of the U3 chip-B is defined as VP4 and is connected with the output end of the U3 chip-B, and the output end of the U3 chip-B is connected with the left side of the first column of the resistance network; the non-inverting input end of the U3 chip-A is grounded, the inverting input end of the U3 chip-A is connected with the junction of the fourth column and the fifth column of the resistor network, the output end of the U3 chip-A is defined as VN4, and the output end of the U3 chip-A is connected with the right side of the eighth column of the resistor network; the non-inverting input end of the U4 chip-A is connected with the boundary of the third column and the fourth column of the resistor network, and the inverting input end of the U4 chip-A is connected with the output end of the U4 chip-A, which is defined as VP 1; the non-inverting input end of the U4 chip-B is connected with the boundary of the second column and the third column of the resistor network, and the inverting input end of the U4 chip-B is connected with the output end of the U4 chip-B, which is defined as VP 2; the non-inverting input end of the U5 chip-A is connected with the boundary of the sixth column and the seventh column of the resistor network, and the inverting input end of the U5 chip-A is connected with the output end of the U5 chip-A, which is defined as VN 2; the non-inverting input terminal of the U5 chip-B is connected to the boundary of the fifth column and the sixth column of the resistor network, and the inverting input terminal of the U5 chip-B is connected to the output terminal of the U5 chip-B, which is defined as VN 1.
A Wheatstone strain bridge driving circuit for multi-channel strain signal synchronous acquisition system,
the chip comprises a U1i chip, wherein an X0 port of the U1i chip is connected with AGND, an X1 port is connected with VP1, an X2 port is connected with VP2, an X3 port is connected with VP4, a Y0 port is connected with AGND, a Y1 port is connected with VN1, a Y2 port is connected with VN2, a Y3 port is connected with VN4, an X port is connected with a non-inverting input end of a U2i chip-A, a Y port is connected with a non-inverting input end of a U2i chip-B, an A port is defined as SETAi, a B port is defined as SETBi, and the A port and the B port are both connected; the double-four-out-of-one analog switch U1i chip is 74HC4052, ADG659 or ADG409, the U2i chip is an operational amplifier chip, and OPA2277, AD706 or other precision double operational amplifier chips with similar performance are selected;
the inverting input end of the U2i chip-A is defined as SNi +, the output end is connected with the base electrode of the first triode through a resistor, the collector electrode of the first triode is connected with a +9V power supply through a resistor, and the emitter electrode of the first triode is defined as EXi + and is connected with SNi +; the inverting input end of the U2i chip-B is defined as SNi-, the output end is connected with the base electrode of the second triode through a resistor, the collector electrode of the second triode is connected with a-9V power supply through a resistor, the emitter electrode of the second triode is defined as EXi-, and is connected with SNi-;
the U2i chip is an operational amplifier chip, and the U2i chip-A and the U2i chip-B are respectively connected into a voltage follower;
the wheatstone strain bridge is composed of four resistors, wherein one diagonal is respectively defined as AIi + and AIi-, and the other diagonal is respectively defined as SNi + and SNi-.
An amplifying circuit for a multichannel strain signal synchronous acquisition system comprises a Ui3 chip, wherein the Ui3 chip is a zero-drift operational amplifier chip and adopts OPA2187, ADA4522-2 or other zero-drift double operational amplifier chips with similar performance;
the non-inverting input end of the Ui3 chip-A is defined as AIi +, the inverting input end of the Ui3 chip-A is defined as VOPi, and the output end of the Ui3 chip-A is connected with a resistor network Ri1 formed by connecting four resistors in series;
the non-inverting input end of the Ui3 chip-B is defined as AIi, the inverting input end of the Ui3 chip-B is defined as VONi, and the output end of the Ui3 chip-B is connected with a resistor network Ri2 formed by connecting four resistors in series;
the inverting input end of the Ui3 chip-A and the inverting input end of the Ui3 chip-B are connected through a resistor network Ri3 formed by four resistors in parallel.
A multichannel strain signal synchronous acquisition method comprises the following steps after electrification:
step a, initializing, namely setting the Wheatstone strain bridge driving voltage to be zero, reading configuration and calibration parameters by a microprocessor system, and setting the sampling rate and gain of an A/D synchronous acquisition circuit;
b, detecting the state of the Wheatstone strain bridge, step-by-step increasing the driving voltage of the Wheatstone bridge, detecting whether the output signal of the Wheatstone strain bridge changes in proportion to the driving voltage, and judging whether the bridge works normally according to the change, if so:
prompting if the output signal of the Wheatstone strain bridge does not change in proportion to the driving voltage;
c, if the output signal of the Wheatstone strain bridge changes in proportion to the driving voltage, entering the step c;
c, identifying the network port communication, checking whether the microprocessor system can perform the network port communication, if so:
if yes, the microprocessor system collects data in a network port communication state;
if not, entering the step d;
d, serial communication identification, checking whether the microprocessor system can perform serial communication, if so:
if yes, the microprocessor system collects data in a serial port communication state;
if not, entering the step e;
step e, USB communication identification, checking whether the microprocessor system can carry out USB communication, if so:
if yes, the microprocessor system collects data in a USB communication state;
if not, entering the step f;
f, identifying the USB flash disk, checking whether the USB interface is connected with the USB flash disk, if so:
acquiring data according to a mode of a configuration file in the USB flash disk, and storing the data according to a specified format;
if not, the microprocessor system is in an idle state;
in the above steps, according to the configuration of the USB flash disk, synchronous signal acquisition is carried out to be in an unattended value acquisition mode; and the communication interface is utilized to acquire the synchronous signals into a real-time acquisition mode.
A multichannel strain signal synchronous acquisition method comprises a parameter calibration method and a data acquisition processing method;
the parameter calibration method comprises the steps that according to different measuring ranges, an analog calibrator is used for providing input signals, a digital multimeter and a nanovolt meter meeting precision requirements are used externally for monitoring the positive end and the negative end of the input signals, and zero point and gain calibration is carried out on each measuring range of each channel at a specific temperature; the method comprises the following specific steps:
step a: adjusting the output of the analog calibrator to be zero, measuring the voltages of the positive and negative ends of the input signal, reading the output value N0 of the A/D synchronous acquisition circuit, and monitoring the driving voltage by using a voltmeter;
step b: adjusting the output of the analog calibrator to be full scale, measuring the voltages at the positive end and the negative end of an input signal, reading an output value N1 of the A/D synchronous acquisition circuit, and monitoring the driving voltage by using a voltmeter;
calculating the zero point and the gain of the channel by using the driving voltage measured by the voltmeter twice;
the data acquisition and processing method finds out two points above and below the current temperature, and calculates the gain and zero point range parameters of the specific channel in the specific driving voltage range at the current temperature according to a linear interpolation method.
Has the advantages that:
firstly, the multichannel strain signal synchronous acquisition system does not need electrical isolation among channels, reduces the cost and reduces the complexity of a circuit structure; the signal after ADC reference proportion conversion actively drives the Wheatstone strain bridge, so that the reference noise is reduced, and the self-detection and low power consumption of the Wheatstone strain bridge are realized; the cost is greatly reduced by using a common low-temperature drift resistor, and the measurement accuracy is improved; and a 5VDC power supply mode compatible with a USB interface is adopted, so that the compatibility of indoor and field environments is realized, and the compatibility of real-time transmission and USB flash disk storage is realized.
Secondly, the invention adopts independent reference voltage as the conversion reference of the A/D synchronous acquisition circuit, the reference voltage is used as the driving signal of the Wheatstone strain bridge after the multi-gear proportion conversion, the driving voltage of the Wheatstone strain bridge can be automatically adjusted according to the measuring range of the strain signal, the Wheatstone strain bridge can be self-detected when the electric power is on, and the power supply voltage of a plurality of channels of Wheatstone strain bridges can be independently set to be zero so as to reduce the power consumption.
Thirdly, the invention adopts an active Wheatstone bridge driving circuit structure. The driving power supply of the electric bridge is derived from bipolar symmetrical signals, so that common-mode interference can be eliminated; the driving signal of the bridge is buffered and output by each power amplifier and then drives the Wheatstone strain bridges, so that the driving voltage amplitudes of the Wheatstone strain bridges are ensured to be the same, and the crosstalk of a Wheatstone strain bridge power supply among channels is prevented; the Wheatstone bridge driving circuit adopts a differential output mode, each output end of the Wheatstone bridge driving circuit uses a triode to improve the driving capability, the potential of the working point of the corresponding strain bridge is equal to the potential arranged at the same phase end of the voltage follower, and the error of lead resistance is eliminated; the differential driving voltage is fixed at the low end, the high end can be uniformly set to be 0, Vref, 2Vref and 4Vref, and the Vref is the ADC reference, so that the power-saving working mode and self-diagnosis of the channel can be realized.
Fourth, the synchronous acquisition circuit of AD has single data line SPI interface, and microprocessor can directly adopt its SPI and ADC communication, need not additionally to increase conversion data transmission link circuit, can reduce the requirement to microprocessor system clock like this, improves the data transmission speed that multichannel meets an emergency signal synchronous acquisition relatively.
Fifthly, the synchronous sampling speed of the A/D synchronous acquisition circuit is not lower than 32KSPS, the requirement of the synchronous acquisition speed of a vibration strain signal and a dynamic weighing signal is met, the conversion result is in an SPI data transmission mode of a single data line and is in seamless connection with an interface of a microprocessor, an expanded conversion data storage and transmission circuit is not needed, and the circuit of a digital system is simplified.
And sixthly, the series-parallel combination of the batch of common low-temperature drift chip resistors in the same batch is used as the gain setting of the signal amplification unit, a zero-drift operational amplifier is added to realize the signal amplification function, the cost is greatly reduced, the excellent temperature stability of signal acquisition is kept, the series-parallel combination of the batch of common low-temperature drift chip resistors in the same batch is also adopted for reference proportion transformation, and the stability of voltage reference is also ensured by combining the zero-drift operational amplifier.
Drawings
Fig. 1 is a general block diagram of a conventional multichannel strain signal synchronous acquisition device.
Fig. 2 is a general block diagram of the multichannel strain signal synchronous acquisition system of the invention.
Fig. 3 is a schematic diagram of a voltage reference scaling circuit of the present invention.
FIG. 4 is a schematic diagram of a Wheatstone strain bridge driving circuit of the present invention.
Fig. 5 is a schematic diagram of an amplification circuit of the present invention.
Detailed Description
The following describes in further detail specific embodiments of the present invention with reference to the accompanying drawings.
Detailed description of the preferred embodiment
The embodiment is a multi-channel strain signal synchronous acquisition system embodiment.
As shown in fig. 2, the multichannel strain signal synchronous acquisition system of the present embodiment includes a voltage reference proportional transformation circuit, a program control setting module, a driving circuit, a wheatstone strain bridge, an amplifying circuit, an anti-aliasing filtering circuit, an a/D synchronous acquisition circuit, an isolation module, and a microprocessor system;
the voltage of the voltage reference proportional transformation circuit is provided for the driving circuit through the program control setting module, the driving circuit drives the Wheatstone strain bridge to amplify and filter the strain signal through the amplifying circuit and the anti-aliasing filter circuit, then the analog signal is converted into a digital signal through the A/D synchronous acquisition circuit and the digital isolation, and finally the digital signal is transmitted to the microprocessor system through the SPI interface to be processed;
in the present embodiment, it is preferred that,
the A/D synchronous acquisition circuit selects ADS131A0X series, wherein X is respectively 4, 6 or 8, and respectively represents four-channel, six-channel and eight-channel synchronous sampling;
the isolation module employs ADUM1400 and ADUM1401 digital logic to isolate the chips.
Detailed description of the invention
The embodiment is a multi-channel strain signal synchronous acquisition system embodiment.
In the multichannel synchronous acquisition system for strain signals of the embodiment, on the basis of the first specific embodiment, the voltage reference proportional conversion circuit is further limited to include a voltage reference, a noise reduction filter circuit and a logic circuit, as shown in fig. 3;
the voltage reference adopts ADR02, ADR4550, REF5050 or other compatible reference chips;
the noise reduction filter circuit performs noise reduction filtering on the voltage reference and outputs 5V reference voltage;
the logic circuit comprises a U3 chip, a U4 chip, a U5 chip and a 3 x 8 resistor network; the U3 chip, the U4 chip and the U5 chip are all operational amplifier chips, OPA2277, AD706 or other precision dual operational amplifier chips with similar performance are selected, the non-inverting input end of the U3 chip-B is connected with the output end of the noise reduction filter circuit, the inverting input end of the U3 chip-B is defined as VP4 and is connected with the output end of the U3 chip-B, and the output end of the U3 chip-B is connected with the left side of the first column of the resistance network; the non-inverting input end of the U3 chip-A is grounded, the inverting input end of the U3 chip-A is connected with the junction of the fourth column and the fifth column of the resistor network, the output end of the U3 chip-A is defined as VN4, and the output end of the U3 chip-A is connected with the right side of the eighth column of the resistor network; the non-inverting input end of the U4 chip-A is connected with the boundary of the third column and the fourth column of the resistor network, and the inverting input end of the U4 chip-A is connected with the output end of the U4 chip-A, which is defined as VP 1; the non-inverting input end of the U4 chip-B is connected with the boundary of the second column and the third column of the resistor network, and the inverting input end of the U4 chip-B is connected with the output end of the U4 chip-B, which is defined as VP 2; the non-inverting input end of the U5 chip-A is connected with the boundary of the sixth column and the seventh column of the resistor network, and the inverting input end of the U5 chip-A is connected with the output end of the U5 chip-A, which is defined as VN 2; the non-inverting input terminal of the U5 chip-B is connected to the boundary of the fifth column and the sixth column of the resistor network, and the inverting input terminal of the U5 chip-B is connected to the output terminal of the U5 chip-B, which is defined as VN 1.
Detailed description of the preferred embodiment
The embodiment is a multi-channel strain signal synchronous acquisition system embodiment.
In the multichannel strain signal synchronous acquisition system of this embodiment, on the basis of the first specific embodiment, the driving circuit and the wheatstone strain bridge are further limited to form a wheatstone strain bridge driving circuit, as shown in fig. 4, as follows:
the double-four-one-by-one analog switch U1i chip comprises a U1i chip, wherein an X0 port is connected with AGND, an X1 port is connected with VP1, an X2 port is connected with VP2, an X3 port is connected with VP4, a Y0 port is connected with AGND, a Y1 port is connected with VN1, a Y2 port is connected with VN2, a Y3 port is connected with VN4, an X port is connected with a non-inverting input end of a U2i chip-A, a Y port is connected with a non-inverting input end of a U2i chip-B, an A port is defined as SETAi, a B port is defined as SETBi, and the A port and the B port are; the double-four-out-of-one analog switch U1i chip is 74HC4052, ADG659 or ADG409, the U2i chip is an operational amplifier chip, and OPA2277, AD706 or other precision double operational amplifier chips with similar performance are selected;
the inverting input end of the U2i chip-A is defined as SNi +, the output end is connected with the base electrode of the first triode through a resistor, the collector electrode of the first triode is connected with a +9V power supply through a resistor, and the emitter electrode of the first triode is defined as EXi + and is connected with SNi +; the inverting input end of the U2i chip-B is defined as SNi-, the output end is connected with the base electrode of the second triode through a resistor, the collector electrode of the second triode is connected with a-9V power supply through a resistor, the emitter electrode of the second triode is defined as EXi-, and is connected with SNi-;
the U2i chip is an operational amplifier chip, and the U2i chip-A and the U2i chip-B are respectively connected into a voltage follower;
the wheatstone strain bridge is composed of four resistors, wherein one diagonal is respectively defined as AIi + and AIi-, and the other diagonal is respectively defined as SNi + and SNi-.
Detailed description of the invention
The embodiment is a multi-channel strain signal synchronous acquisition system embodiment.
The multichannel strain signal synchronous acquisition system of the embodiment further defines that, on the basis of the first specific embodiment, the amplification circuit is shown in fig. 5, and includes a Ui3 chip, where the Ui3 chip is a zero-drift operational amplifier chip, and adopts OPA2187, ADA4522-2 or other zero-drift dual operational amplifier chips with similar performance;
the non-inverting input end of the Ui3 chip-A is defined as AIi +, the inverting input end of the Ui3 chip-A is defined as VOPi, and the output end of the Ui3 chip-A is connected with a resistor network Ri1 formed by connecting four resistors in series;
the non-inverting input end of the Ui3 chip-B is defined as AIi, the inverting input end of the Ui3 chip-B is defined as VONi, and the output end of the Ui3 chip-B is connected with a resistor network Ri2 formed by connecting four resistors in series;
the inverting input end of the Ui3 chip-A and the inverting input end of the Ui3 chip-B are connected through a resistor network Ri3 formed by four resistors in parallel.
Detailed description of the preferred embodiment
The embodiment is a multi-channel strain signal synchronous acquisition system embodiment.
The multi-channel strain signal synchronous acquisition system of the embodiment further defines pins or ports with the same definition to be connected together on the basis of the first embodiment, the second embodiment, the third embodiment and/or the fourth embodiment.
Detailed description of the preferred embodiment
The embodiment is a voltage reference proportion conversion circuit embodiment for a multi-channel strain signal synchronous acquisition system.
The voltage reference proportional transformation circuit for the multichannel strain signal synchronous acquisition system of the embodiment, as shown in fig. 3, includes a voltage reference, a noise reduction filter circuit and a logic circuit;
the voltage reference adopts ADR02, ADR4550, REF5050 or other compatible reference chips;
the noise reduction filter circuit performs noise reduction filtering on the voltage reference and outputs 5V reference voltage;
the logic circuit comprises a U3 chip, a U4 chip, a U5 chip and a 3 x 8 resistor network; the U3 chip, the U4 chip and the U5 chip are all operational amplifier chips, OPA2277, AD706 or other precision dual operational amplifier chips with similar performance are selected, the non-inverting input end of the U3 chip-B is connected with the output end of the noise reduction filter circuit, the inverting input end of the U3 chip-B is defined as VP4 and is connected with the output end of the U3 chip-B, and the output end of the U3 chip-B is connected with the left side of the first column of the resistance network; the non-inverting input end of the U3 chip-A is grounded, the inverting input end of the U3 chip-A is connected with the junction of the fourth column and the fifth column of the resistor network, the output end of the U3 chip-A is defined as VN4, and the output end of the U3 chip-A is connected with the right side of the eighth column of the resistor network; the non-inverting input end of the U4 chip-A is connected with the boundary of the third column and the fourth column of the resistor network, and the inverting input end of the U4 chip-A is connected with the output end of the U4 chip-A, which is defined as VP 1; the non-inverting input end of the U4 chip-B is connected with the boundary of the second column and the third column of the resistor network, and the inverting input end of the U4 chip-B is connected with the output end of the U4 chip-B, which is defined as VP 2; the non-inverting input end of the U5 chip-A is connected with the boundary of the sixth column and the seventh column of the resistor network, and the inverting input end of the U5 chip-A is connected with the output end of the U5 chip-A, which is defined as VN 2; the non-inverting input terminal of the U5 chip-B is connected to the boundary of the fifth column and the sixth column of the resistor network, and the inverting input terminal of the U5 chip-B is connected to the output terminal of the U5 chip-B, which is defined as VN 1.
Detailed description of the preferred embodiment
The embodiment is a Wheatstone strain bridge driving circuit embodiment for a multi-channel strain signal synchronous acquisition system.
The wheatstone strain bridge driving circuit for the multichannel strain signal synchronous acquisition system of the embodiment, as shown in fig. 4, includes a double-four-to-one analog switch U1i chip, an X0 port of the U1i chip is connected to AGND, an X1 port is connected to VP1, an X2 port is connected to VP2, an X3 port is connected to VP4, a Y0 port is connected to AGND, a Y1 port is connected to VN1, a Y2 port is connected to VN2, a Y3 port is connected to VN4, an X port is connected to the non-inverting input terminal of a chip U2i, a Y port is connected to the non-inverting input terminal of a chip U2 i-B, an a port is defined as SETAi, a port is defined as SETBi, and B port is defined as SETBi, both a port and B port are connected; the double-four-out-of-one analog switch U1i chip is 74HC4052, ADG659 or ADG409, the U2i chip is an operational amplifier chip, and OPA2277, AD706 or other precision double operational amplifier chips with similar performance are selected;
the inverting input end of the U2i chip-A is defined as SNi +, the output end is connected with the base electrode of the first triode through a resistor, the collector electrode of the first triode is connected with a +9V power supply through a resistor, and the emitter electrode of the first triode is defined as EXi + and is connected with SNi +; the inverting input end of the U2i chip-B is defined as SNi-, the output end is connected with the base electrode of the second triode through a resistor, the collector electrode of the second triode is connected with a-9V power supply through a resistor, the emitter electrode of the second triode is defined as EXi-, and is connected with SNi-;
the U2i chip is an operational amplifier chip, and the U2i chip-A and the U2i chip-B are respectively connected into a voltage follower;
the wheatstone strain bridge is composed of four resistors, wherein one diagonal is respectively defined as AIi + and AIi-, and the other diagonal is respectively defined as SNi + and SNi-.
Detailed description of the preferred embodiment
The embodiment is an amplifying circuit embodiment for a multichannel strain signal synchronous acquisition system.
The amplifying circuit for the multichannel strain signal synchronous acquisition system of the embodiment is shown in fig. 5, and comprises a Ui3 chip, wherein the Ui3 chip is a zero drift operational amplifier chip, and adopts OPA2187, ADA4522-2 or other zero drift double operational amplifier chips with similar performance;
the non-inverting input end of the Ui3 chip-A is defined as AIi +, the inverting input end of the Ui3 chip-A is defined as VOPi, and the output end of the Ui3 chip-A is connected with a resistor network Ri1 formed by connecting four resistors in series;
the non-inverting input end of the Ui3 chip-B is defined as AIi, the inverting input end of the Ui3 chip-B is defined as VONi, and the output end of the Ui3 chip-B is connected with a resistor network Ri2 formed by connecting four resistors in series;
the inverting input end of the Ui3 chip-A and the inverting input end of the Ui3 chip-B are connected through a resistor network Ri3 formed by four resistors in parallel.
Detailed description of the preferred embodiment
The embodiment is an embodiment of a method for synchronously acquiring multi-channel strain signals.
The multichannel strain signal synchronous acquisition method of the embodiment comprises the following steps after electrification:
step a, initializing, namely setting the Wheatstone strain bridge driving voltage to be zero, reading configuration and calibration parameters by a microprocessor system, and setting the sampling rate and gain of an A/D synchronous acquisition circuit;
b, detecting the state of the Wheatstone strain bridge, step-by-step increasing the driving voltage of the Wheatstone bridge, detecting whether the output signal of the Wheatstone strain bridge changes in proportion to the driving voltage, and judging whether the bridge works normally according to the change, if so:
prompting if the output signal of the Wheatstone strain bridge does not change in proportion to the driving voltage;
c, if the output signal of the Wheatstone strain bridge changes in proportion to the driving voltage, entering the step c;
c, identifying the network port communication, checking whether the microprocessor system can perform the network port communication, if so:
if yes, the microprocessor system collects data in a network port communication state;
if not, entering the step d;
d, serial communication identification, checking whether the microprocessor system can perform serial communication, if so:
if yes, the microprocessor system collects data in a serial port communication state;
if not, entering the step e;
step e, USB communication identification, checking whether the microprocessor system can carry out USB communication, if so:
if yes, the microprocessor system collects data in a USB communication state;
if not, entering the step f;
f, identifying the USB flash disk, checking whether the USB interface is connected with the USB flash disk, if so:
acquiring data according to a mode of a configuration file in the USB flash disk, and storing the data according to a specified format;
if not, the microprocessor system is in an idle state;
in the above steps, according to the configuration of the USB flash disk, synchronous signal acquisition is carried out to be in an unattended value acquisition mode; and the communication interface is utilized to acquire the synchronous signals into a real-time acquisition mode.
Detailed description of the preferred embodiment
The embodiment is an embodiment of a method for synchronously acquiring multi-channel strain signals.
The multichannel strain signal synchronous acquisition method comprises a parameter calibration method and a data acquisition and processing method;
the parameter calibration method comprises the steps that according to different measuring ranges, an analog calibrator is used for providing input signals, a digital multimeter and a nanovolt meter meeting precision requirements are used externally for monitoring the positive end and the negative end of the input signals, and zero point and gain calibration is carried out on each measuring range of each channel at a specific temperature; the method comprises the following specific steps:
step a: adjusting the output of the analog calibrator to be zero, measuring the voltages of the positive and negative ends of the input signal, reading the output value N0 of the A/D synchronous acquisition circuit, and monitoring the driving voltage by using a voltmeter;
step b: adjusting the output of the analog calibrator to be full scale, measuring the voltages at the positive end and the negative end of an input signal, reading an output value N1 of the A/D synchronous acquisition circuit, and monitoring the driving voltage by using a voltmeter;
calculating the zero point and the gain of the channel by using the driving voltage measured by the voltmeter twice;
the data acquisition and processing method finds out two points above and below the current temperature, and calculates the gain and zero point range parameters of the specific channel in the specific driving voltage range at the current temperature according to a linear interpolation method.
It should be noted that, in the above embodiments, the non-contradictory technical solutions can be arranged and combined, and since a person skilled in the art can exhaust all possible arrangement and combination results only by applying high-school mathematical knowledge, they are not listed in detail in this application. However, it should be understood that the results of the permutation and combination are all described in the present application.
Claims (5)
1. A multichannel strain signal synchronous acquisition system is characterized by comprising a voltage reference proportional transformation circuit, a program control setting module, a driving circuit, a Wheatstone strain bridge, an amplifying circuit, an anti-aliasing filtering circuit, an A/D synchronous acquisition circuit, an isolation module and a microprocessor system;
voltage of voltage reference proportional transformation circuit provides drive circuit through programme-controlled setting module, and drive circuit drive Wheatstone strain bridge passes through amplifier circuit and anti-aliasing filter circuit with the signal of meeting an emergency and amplifies the filtering, and the synchronous acquisition circuit of rethread AD and digital isolation convert analog signal into digital signal, transmit for microprocessor system through the SPI interface at last and handle.
2. The multi-channel strain signal synchronous acquisition system according to claim 1, wherein the voltage reference scaling circuit comprises a voltage reference, a noise reduction filter circuit and a logic circuit;
the voltage reference adopts ADR02, ADR4550 or REF 5050;
the noise reduction filter circuit performs noise reduction filtering on the voltage reference and outputs 5V reference voltage;
the logic circuit comprises a U3 chip, a U4 chip, a U5 chip and a 3 x 8 resistor network; the U3 chip, the U4 chip and the U5 chip are all operational amplifier chips, OPA2277 or AD706 is selected, the non-inverting input end of the U3 chip-B is connected with the output end of the noise reduction filter circuit, the inverting input end of the U3 chip-B is defined as VP4 and is connected with the output end of the U3 chip-B, and the output end of the U3 chip-B is connected with the left side of the first column of the resistor network; the non-inverting input end of the U3 chip-A is grounded, the inverting input end of the U3 chip-A is connected with the junction of the fourth column and the fifth column of the resistor network, the output end of the U3 chip-A is defined as VN4, and the output end of the U3 chip-A is connected with the right side of the eighth column of the resistor network; the non-inverting input end of the U4 chip-A is connected with the boundary of the third column and the fourth column of the resistor network, and the inverting input end of the U4 chip-A is connected with the output end of the U4 chip-A, which is defined as VP 1; the non-inverting input end of the U4 chip-B is connected with the boundary of the second column and the third column of the resistor network, and the inverting input end of the U4 chip-B is connected with the output end of the U4 chip-B, which is defined as VP 2; the non-inverting input end of the U5 chip-A is connected with the boundary of the sixth column and the seventh column of the resistor network, and the inverting input end of the U5 chip-A is connected with the output end of the U5 chip-A, which is defined as VN 2; the non-inverting input terminal of the U5 chip-B is connected to the boundary of the fifth column and the sixth column of the resistor network, and the inverting input terminal of the U5 chip-B is connected to the output terminal of the U5 chip-B, which is defined as VN 1.
3. The multi-channel strain signal synchronous acquisition system according to claim 1, wherein the driving circuit and the wheatstone strain bridge form a wheatstone strain bridge driving circuit, as follows:
the double-four-one-by-one analog switch U1i chip comprises a U1i chip, wherein an X0 port is connected with AGND, an X1 port is connected with VP1, an X2 port is connected with VP2, an X3 port is connected with VP4, a Y0 port is connected with AGND, a Y1 port is connected with VN1, a Y2 port is connected with VN2, a Y3 port is connected with VN4, an X port is connected with a non-inverting input end of a U2i chip-A, a Y port is connected with a non-inverting input end of a U2i chip-B, an A port is defined as SETAi, a B port is defined as SETBi, and the A port and the B port are; the double-four-out-of-one analog switch U1i chip is 74HC4052, ADG659 or ADG409, the U2i chip is an operational amplifier chip, and OPA2277 or AD706 is selected;
the inverting input end of the U2i chip-A is defined as SNi +, the output end is connected with the base electrode of the first triode through a resistor, the collector electrode of the first triode is connected with a +9V power supply through a resistor, and the emitter electrode of the first triode is defined as EXi + and is connected with SNi +; the inverting input end of the U2i chip-B is defined as SNi-, the output end is connected with the base electrode of the second triode through a resistor, the collector electrode of the second triode is connected with a-9V power supply through a resistor, the emitter electrode of the second triode is defined as EXi-, and is connected with SNi-;
the U2i chip is an operational amplifier chip, and the U2i chip-A and the U2i chip-B are respectively connected into a voltage follower;
the wheatstone strain bridge is composed of four resistors, wherein one diagonal is respectively defined as AIi + and AIi-, and the other diagonal is respectively defined as SNi + and SNi-.
4. The multi-channel strain signal synchronous acquisition system as claimed in claim 1, wherein the amplifying circuit comprises a Ui3 chip, the Ui3 chip is a zero drift operational amplifier chip, and the OPA2187 or ADA4522-2 is adopted;
the non-inverting input end of the Ui3 chip-A is defined as AIi +, the inverting input end of the Ui3 chip-A is defined as VOPi, and the output end of the Ui3 chip-A is connected with a resistor network Ri1 formed by connecting four resistors in series;
the non-inverting input end of the Ui3 chip-B is defined as AIi, the inverting input end of the Ui3 chip-B is defined as VONi, and the output end of the Ui3 chip-B is connected with a resistor network Ri2 formed by connecting four resistors in series;
the inverting input end of the Ui3 chip-A and the inverting input end of the Ui3 chip-B are connected through a resistor network Ri3 formed by four resistors in parallel.
5. A multichannel strain signal synchronous acquisition system as claimed in claim 1, 2, 3 or 4, characterized in that identically defined pins or ports are connected together.
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| CN110032126A (en) * | 2019-05-14 | 2019-07-19 | 哈尔滨理工大学 | A kind of multichannel strain signal synchronous and method |
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| CN110032126B (en) * | 2019-05-14 | 2024-03-05 | 哈尔滨理工大学 | Multichannel strain signal synchronous acquisition system and method |
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