CN209805673U

CN209805673U - prevent that power consumption equipment restarts circuit

Info

Publication number: CN209805673U
Application number: CN201920596496.1U
Authority: CN
Inventors: 祝琳; 史晓娇
Original assignee: SUZHOU LAMBO CONTROL TECHNIQUES Co Ltd
Current assignee: SUZHOU LAMBO CONTROL TECHNIQUES Co Ltd
Priority date: 2019-04-28
Filing date: 2019-04-28
Publication date: 2019-12-17
Anticipated expiration: 2029-04-28

Abstract

The utility model discloses an prevent that power consumption equipment restarts circuit, including power input end, earthing terminal, DC/DC converter and load, the boost circuit that is provided with between power input end and the DC/DC converter, DC/DC converter is connected to boost circuit's output, boost circuit works when detecting the voltage of power input end is less than its enable output threshold voltage and steps up; the boost circuit does not work when detecting that the voltage of the power supply output end is larger than the output forbidden threshold voltage. This scheme design is exquisite, simple structure, as long as parallelly connected boost circuit on the basis that does not change original circuit, just can be automatic carry out automatically regulated according to power output voltage size, need not change original circuit, also need not verify original circuit again, be convenient for in the various occasions that exist the risk of falling the electricity and use.

Description

Prevent that power consumption equipment restarts circuit

Technical Field

The utility model belongs to the technical field of electrical equipment and specifically relates to prevent falling electric power consumption equipment restart circuit.

Background

As shown in fig. 1, the power supply circuit for various indicating instruments generally includes a power supply, a DC/DC converter, and the DC/DC converter converts a power supply voltage into 5V and outputs the 5V to a subsequent DC/DC step-down or step-up device and an instrument.

However, when the device where the instrument is located is started, an instantaneous large current is often needed, which causes the voltage of a power supply to drop in a short time or instantaneously, thereby causing the condition that the instrument is restarted when the power failure occurs, generally, in order to avoid the influence of the equipment starting on the electronic instrument, one or more high-capacity super capacitors are also connected in parallel to the power output end for storing energy, and the super capacitors discharge to supply power for a subsequent circuit when the power voltage suddenly drops.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a prevent falling electric power consumption equipment restart circuit in order to solve the above-mentioned problem that exists among the prior art exactly.

The purpose of the utility model is realized through the following technical scheme:

The power-off-preventing electric equipment restarting circuit comprises a power supply input end, a grounding end, a DC/DC converter and a load, wherein a boosting circuit is arranged between the power supply input end and the DC/DC converter, the output end of the boosting circuit is connected with the DC/DC converter, and the boosting circuit works for boosting when detecting that the voltage of the power supply input end is smaller than the enabling output threshold voltage of the boosting circuit; the boost circuit is not operated when detecting that the voltage of the power supply input end is larger than the output forbidden threshold voltage.

preferably, in the power-off prevention electric equipment restarting circuit, the input voltage of the power supply input end is between 3 and 36V.

Preferably, in the restart circuit of the power-loss prevention electric equipment, the power input end is connected with the anode of a first diode, and the cathode of the first diode is connected with the input end of the boost circuit.

Preferably, in the power-off prevention restarting circuit for electrical equipment, a surge suppressor and a filter capacitor are further arranged between the power input end and the grounding end in parallel.

Preferably, in the circuit for restarting the power-down prevention electric equipment, the surge suppressor is a voltage stabilizing diode, and the filter capacitor is a polar capacitor.

Preferably, in the restart circuit for power-loss-prevention electric equipment, the boost circuit includes an inductor, a second diode, an MOS transistor, and a boost chip, one end of the inductor is connected to the power input end, the other end of the inductor is connected to the anode of the second diode and the drain of the MOS transistor, the cathode of the second diode is connected to the DC/DC converter, the source of the MOS transistor is grounded through a second resistor, the gate of the MOS transistor is connected to the GDRV pin of the boost chip, the VDRV pin of the boost chip is grounded through a first capacitor and connected to the STATUS pin of the boost chip through a fifth resistor, and the STATUS pin of the boost chip is further connected to the 3.3V voltage output end through a first resistor; the ISNS pin of the chip that steps up connects the connecting wire of MOS pipe and second resistance, the GND pin ground connection of the chip that steps up, the DISB pin of the chip that steps up connects 3.3V voltage output end and through the ground connection of sixth resistance through the third resistance, the VC pin of the chip that steps up is through the second electric capacity and the fourth resistance ground connection that concatenate.

Preferably, in the restart circuit of the power-down prevention electric equipment, the MOS transistor comprises a silicon substrate, a Gi1-nGen epitaxial layer and a P-type strain germanium channel layer which are sequentially formed from top to bottom, a hafnium oxide layer is arranged at the middle position of the P-type strain germanium channel layer, a tantalum nitride layer is arranged on the hafnium oxide layer, a source region and a drain region which are located around the hafnium oxide layer and the tantalum nitride layer are further arranged on the P-type strain germanium channel layer, an electrode and a dielectric layer which covers the tantalum nitride layer and is arranged on the periphery of the electrode are respectively arranged on the source region and the drain region, and the dielectric layer and the electrode cover the passivation layer.

The utility model discloses technical scheme's advantage mainly embodies:

This scheme design is exquisite, simple structure, as long as parallelly connected boost circuit on the basis that does not change original circuit, just can be automatic carry out automatically regulated according to power output voltage size, need not change original circuit, also need not verify original circuit again, be convenient for in the various occasions that exist the risk of falling the electricity and use.

The circuit of the scheme has a wide input voltage range (2V to 40V), so that the application range is widened, and the popularization and the application in various fields are facilitated.

The circuit of the scheme has the functions of preventing reverse connection of a power supply and preventing peak current and voltage, and effectively ensures the stability and safety of circuit operation.

The boost circuit of this scheme has state diagnostic function, output unstable disable function, overcurrent protection, overheat protection function, has richened the performance, the effectual stability and the security of guaranteeing the circuit to output precision 2%, low quiescent current (< 12 microamperes) under the sleep mode, the low-power consumption, the precision is high, and is with low costs, and circuit structure easily realizes.

Drawings

Fig. 1 is a prior art described in the background of the invention;

Fig. 2 is a schematic diagram of the restart circuit of the power-off prevention electric equipment of the present invention;

Fig. 3 is a schematic diagram of a zener diode of the present invention;

Fig. 4 is a schematic diagram of the boost circuit of the present invention;

Fig. 5 is a schematic diagram of a MOS transistor according to the present invention.

Detailed Description

Objects, advantages and features of the present invention will be illustrated and explained by the following non-limiting description of preferred embodiments. These embodiments are merely exemplary embodiments for applying the technical solutions of the present invention, and all technical solutions formed by adopting equivalent substitutions or equivalent transformations fall within the scope of the present invention.

In the description of the embodiments, it should be noted that the terms "center", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the embodiment, the operator is used as a reference, and the direction close to the operator is a proximal end, and the direction away from the operator is a distal end.

The following explains the restart circuit of the power-down prevention electric device disclosed by the present invention with reference to the accompanying drawings, as shown in fig. 2, it includes a power input terminal, a grounding terminal, a DC/DC converter 1 and a load 2, wherein the voltage output by the power input terminal is between 3-36V, so that the circuit can have a wide input voltage range; the power input end is connected with a DC/DC converter 1, the DC/DC converter 1 may be various known step-up and step-down circuits, and adjusts the voltage input by the power input end to 5V and outputs the adjusted voltage to a load 2, the load 2 may be various 5V electric devices, such as a backlight power supply, a display instrument, and the like, and may also be other step-down devices or step-up devices, such as a 3.3 DC/DC step-down device and/or a 1.8V DC/DC step-down device and/or a 1.2V DC/DC step-down device.

In addition, in order to prevent the damage caused by the reverse connection of the power supply, the anode of the first diode D1 is connected with the power supply input end, and the cathode of the first diode D1 is connected with the input end of the booster circuit 3, so that the unidirectional conduction characteristic of the diode can be effectively utilized, and the load can be prevented from being damaged; meanwhile, a surge suppressor TVS and a filter capacitor E2 are further arranged between the power supply access end and the grounding end in parallel, the surge suppressor TVS is a voltage stabilizing diode, the cathode of the surge suppressor TVS is connected with the cathode of the first diode, and the anode of the surge suppressor TVS is grounded, so that the damage to the whole circuit when spike current or voltage is suddenly generated from the outside can be effectively prevented; the filter capacitor E2 is a polar capacitor, the anode of the polar capacitor is connected to the cathode of the first diode D1, and the cathode of the polar capacitor is grounded, so that the ripple can be effectively and smoothly output.

Preferably, as shown in fig. 3, the zener diode 200 includes a first electrode 2001, a titanium bottom layer 2002, a titanium-tungsten alloy layer 2003, a titanium layer 2004, a PN junction 2005, and a second electrode 2006, which are sequentially arranged from bottom to top, the second electrode 2006 is in a step shape with a low middle and a high periphery, a silicon nitride layer 42 and a silicon oxide layer 2008 are further arranged between the second electrode 2006 and the PN junction 2005, and the silicon nitride layer 42 and the silicon oxide layer 2008 have a step-shaped structure matched with the second electrode 2006.

further, as shown in fig. 2, a boost circuit 3 is arranged between the power input end and the DC/DC converter 1, an output end of the boost circuit 3 is connected to the DC/DC converter 1, and the boost circuit 3 operates to boost when detecting that the voltage at the power input end is smaller than an enable output threshold voltage thereof; the booster circuit 3 does not operate when it detects that the voltage at the power supply output terminal is greater than its output-prohibited threshold voltage.

In detail, as shown in fig. 2 and fig. 4, the boost circuit 3 includes an inductor L1, a second diode D2, a MOS transistor N1, and a boost chip U1, one end of the inductor L1 is connected to the first diode D1, the other end is connected to the anode of the second diode D2 and the drain of the MOS transistor, the cathode of the second diode D2 is connected to the DC/DC converter 1, the source of the MOS transistor N1 is grounded through a second resistor R2, the gate of the MOS transistor N1 is connected to the GDRV pin of the boost chip U1, the VDRV pin of the boost chip U1 is grounded through a first capacitor C1 and connected to the STATUS pin of the boost chip through a fifth resistor, and the STATUS pin of the boost chip is further connected to the 3.3V voltage output terminal through a first resistor R1; the ISNS pin of the chip that steps up connects MOS pipe and second resistance R2's connecting wire, the GND foot ground connection of the chip that steps up, the DISB pin of the chip that steps up connects 3.3V voltage output end and through sixth resistance R6 ground connection through third resistance R3, the VC pin of the chip that steps up is through the second electric capacity C2 and the third resistance R4 ground connection that concatenate.

The boost chip U1 may be an integrated circuit of model number NCV887801D1R2G, in which the STATUS pin is used for open-drain diagnosis, and serves as a chip state operation flag indicator, and when the VOUT pin of the boost chip U1 is lower than an enable output threshold voltage VIN1, the device is activated; the ISNS pin is used for current detection input and is connected to a power supply of an external MOS tube through a current sensing resistor so as to sense switching current for regulation and current limiting; the GDRV pin is a gate driver output pin and is used for being connected to a grid electrode of an external MOS tube, and a series of resistors can be added to the grid electrode from the GDRV pin to customize EMC performance; the VDRV pin is a driving electric pressure pin; the VOUT pin is used for monitoring the output voltage and providing the input voltage of the boost chip U1; the VC pin is a Vc output of the voltage error transconductance amplifier, and an external compensation network from VC to GND is used for stabilizing the converter; the DISB pin is the disable release input, and when the voltage at this pin goes low, this component is disabled.

moreover, the MOS transistor is preferably an N-type MOSFET, as shown in fig. 5, the MOS transistor N1 includes a silicon substrate 10, a Gi 1-nggen epitaxial layer 20, and a P-type strained germanium channel layer 30, which are sequentially formed from top to bottom, a hafnium oxide layer 40 is disposed in the middle of the P-type strained germanium channel layer 30, a tantalum nitride layer 50 is disposed on the hafnium oxide layer 40, a source region 60 and a drain region 70 are further disposed on the P-type strained germanium channel layer 102 and located around the hafnium oxide layer 40 and the tantalum nitride layer 50, electrodes 80 and 90 and a dielectric layer 100 covering the electrodes 80 and 90 and covering the tantalum nitride layer 50 are respectively disposed on the source region 60 and the drain region 70, and the dielectric layer 100 and the electrodes 80 and 90 cover under a passivation layer 110.

According to the scheme, the high-quality Gi1-nGen epitaxial layer and the P-type strain germanium channel layer are adopted, compared with a traditional germanium material NMOS device, the carrier mobility of the NMOS device is greatly improved, the size of the NMOS device is reduced, and the current driving and frequency characteristics of the NMOS device are improved.

When the whole circuit works, when the input voltage of a power supply input end is less than VIN1 (voltage for enabling the boost chip to work), the VDRV output voltage of the boost chip is 6V, the MOS tube N1 is conducted to work, and the VOUT pin of the boost chip U1 outputs VOUT voltage (boost output voltage) to provide stable voltage for the DC/DC converter; when the input voltage of the power supply input end continuously drops to 3V, the boosting chip U1 continuously works to output VOUT voltage.

When the output voltage of the power input end is lower than 3V or the input voltage of the DISB pin is lower than 3.3V (the output voltage of the 3.3V is reduced) or when the output voltage of the power input end is recovered to be larger than the output forbidden threshold voltage VIN2 (VIN 2 means the operation voltage of the boosting chip is forbidden, and VIN2 is larger than VIN 1), the output voltage of the VDRV pin of the boosting chip U1 is 0V, the MOS tube N1 is turned off and does not work, the boosting chip U1 is turned off to output VOUT voltage, and the voltage of the two is in a voltage forming interval due to the fact that VIN2 is larger than VIN1, so that the voltage fluctuation can be prevented from causing.

The utility model has a plurality of implementation modes, and all technical schemes formed by adopting equivalent transformation or equivalent transformation all fall within the protection scope of the utility model.

Claims

1. The restart circuit of the power-off-preventing electric equipment comprises a power supply input end, a grounding end, a DC/DC converter (1) and a load (2), and is characterized in that a booster circuit (3) is arranged between the power supply input end and the DC/DC converter (1), and the booster circuit (3) works and boosts when detecting that the voltage of the power supply input end is smaller than the enabling output threshold voltage of the power supply input end; the boost circuit is not operated when detecting that the voltage of the power supply input end is larger than the output forbidden threshold voltage.

2. The power-down prevention electric equipment restarting circuit of claim 1 wherein the input voltage at the power input is between 3-36V.

3. The power-loss prevention restart circuit of claim 1, wherein the power input is connected to the anode of a first diode (D1), and the cathode of the first diode (D1) is connected to the input of the voltage boosting circuit.

4. the power-off-preventing electric equipment restarting circuit of claim 1 is characterized in that a surge suppressor (TVS) and a filter capacitor (E2) are further arranged between the power supply input end and the grounding end in parallel.

5. the power-loss prevention electric equipment restarting circuit according to claim 4 is characterized in that said surge suppressor (TVS) is a zener diode and said filter capacitor (E2) is a polar capacitor.

6. The power down prevention consumer restart circuit of any of claims 1-4, wherein: the boosting circuit (3) comprises an inductor (L1), a second diode (D2), an MOS (N1) and a boosting chip (U1), wherein one end of the inductor (L1) is connected with a power input end, the other end of the inductor (L1) is connected with the anode of the second diode (D2) and the drain of the MOS, the cathode of the second diode (D2) is connected with the DC/DC converter (1), the source of the MOS (N1) is grounded through a second resistor (R2), the gate of the MOS (N1) is connected with the GDRV pin of the boosting chip (U1), the VDRV pin of the boosting chip (U1) is grounded through a first capacitor (C1) and connected with the STATUS pin of the boosting chip through a fifth resistor, and the STATUS pin of the boosting chip is further connected with a 3.3V voltage output end through a first resistor (R1); the ISNS pin of the chip that steps up connects the connecting wire of MOS pipe and second resistance (R2), the GND pin ground connection of the chip that steps up, the DISB pin of the chip that steps up connects 3.3V voltage output end and through sixth resistance (R6) ground connection through third resistance (R3), the VC pin of the chip that steps up is through the second electric capacity (C2) and the fourth resistance (R4) ground connection that concatenate.

7. The restart circuit of claim 6, wherein the MOS transistor (N1) comprises a silicon substrate (10), a Gi1-nGen epitaxial layer (20) and a P-type strained germanium channel layer (30) sequentially formed from top to bottom, a hafnium dioxide layer (40) is disposed in the middle of the P-type strained germanium channel layer (30), a tantalum nitride layer (50) is disposed on the hafnium dioxide layer (40), a source region (60) and a drain region (70) are disposed on the P-type strained germanium channel layer (30) and around the hafnium dioxide layer (40) and the tantalum nitride layer (50), electrodes (80, 90) and a dielectric layer (100) covering the electrodes (80, 90) and the tantalum nitride layer (50) are disposed on the source region (60) and the drain region (70), respectively, and the dielectric layer (100) and the electrodes (80, 90) are disposed on the source region and the drain region (70) and cover the tantalum nitride layer (50), respectively, 90) Covering under the passivation layer (110).