CN209804655U

CN209804655U - Semiconductor wafer and electronic device with same

Info

Publication number: CN209804655U
Application number: CN201920706780.XU
Authority: CN
Inventors: 吴佳蒙; 肖婷; 敖利波; 梁赛嫦; 廖勇波
Original assignee: Gree Electric Appliances Inc of Zhuhai
Current assignee: Gree Electric Appliances Inc of Zhuhai
Priority date: 2019-05-16
Filing date: 2019-05-16
Publication date: 2019-12-17
Anticipated expiration: 2029-05-16

Abstract

The utility model discloses a semiconductor wafer and an electronic device with the same; the semiconductor wafer comprises a chip layer, a wafer layer and a metal layer which are connected in sequence; the chip layer comprises a plurality of chips which are arranged on the wafer layer at intervals, and a scribing channel is formed by two adjacent chips; a plurality of grooves are arranged on the scribing channel at intervals. According to the utility model provides a semiconductor wafer is equipped with a plurality of recesses on the scribing way that wafer layer and chip formed, separates into a plurality of regions of waiting to cut through the recess with the scribing way, because the existence of recess has prevented the cutting stress excess dispersion, improves cutting efficiency, has prevented moreover that unexpected lobe of a leaf appears in the wafer among the cutting process, and then has improved wafer output yield.

Description

Semiconductor wafer and electronic device with same

Technical Field

The utility model relates to a semiconductor integrated circuit makes technical field, concretely relates to semiconductor wafer and have its electron device.

Background

After a device is fabricated on a semiconductor wafer through the process steps of illumination, etching, deposition, cleaning, injection, etc., a physical mechanical cutting mode is generally adopted to cut a circuit device fabricated on the semiconductor wafer into a plurality of independent chips through diamond scribing or mechanical scribing.

However, with the continuous development of chip manufacturing technology, the thickness of the wafer is continuously reduced, and the volume is smaller and smaller, so that the mechanical strength of the wafer is also poorer and poorer; therefore, problems such as cutting stress dispersion and blade sliding deviation are easily caused in the wafer cutting process, unexpected splinters are easily caused in the wafer cutting process, and the wafer yield is reduced.

SUMMERY OF THE UTILITY MODEL

A first object of the present invention is to provide a semiconductor wafer to solve the problem that the current semiconductor wafer is easy to crack in the cutting process and the yield is low.

In order to achieve the above object, the present invention provides the following technical solutions: a semiconductor wafer comprises a chip layer, a wafer layer and a metal layer which are connected in sequence; the chip layer comprises a plurality of chips which are arranged on the wafer layer at intervals, and scribing channels are formed on the wafer layer at intervals between every two adjacent chips; a plurality of grooves are arranged on the scribing channel at intervals.

according to the utility model provides a semiconductor wafer is equipped with a plurality of recesses on the scribing way that wafer layer and chip formed, separates into a plurality of regions of waiting to cut through the recess with the scribing way, because the existence of recess has prevented the too much dispersion of cutting stress, improves cutting efficiency, has prevented the unexpected lobe of a leaf of wafer among the cutting process moreover, and then has improved wafer output yield.

In addition, the semiconductor wafer according to the above embodiments of the present invention may further have the following additional technical features:

According to an example of the present invention, the metal layer is provided with a plurality of through holes.

According to the utility model discloses an example, in the direction perpendicular to the wafer layer, it is a plurality of the through-hole sets up with a plurality of recess one-to-one.

according to an example of the present invention, the through hole is the same as the groove shape size.

According to an example of the present invention, the projection of the recess on the metal layer coincides with the through hole.

According to an example of the present invention, the cross-section of the groove is triangular or diamond-shaped in a direction parallel to the surface of the scribe lane.

According to an example of the present invention, the depth of the groove is 18um to 28 um.

According to an example of the present invention, the scribing lanes are arranged in a staggered manner.

According to the utility model discloses an example, the scribing way includes first region and second region, the first region is crossing two scribing ways's crisscross region, be equipped with in the second region the recess.

A second object of the present invention is to provide an electronic device having the semiconductor wafer according to the above technical solution.

Advantages of the above additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

Fig. 1 is a top view of a semiconductor wafer according to an embodiment of the present invention;

FIG. 2 is an enlarged view of portion A of FIG. 1;

Fig. 3 is a schematic diagram (one) illustrating a semiconductor wafer after dicing according to an embodiment of the present invention;

Fig. 4 is a schematic diagram (ii) illustrating a semiconductor wafer after dicing according to an embodiment of the present invention;

Fig. 5 is a bottom view of a semiconductor wafer according to an embodiment of the present invention;

Fig. 6 is an enlarged view of a portion B of fig. 5.

In the drawings, the components represented by the respective reference numerals are listed below:

1. a chip; 2. a wafer layer; 3. a metal layer; 4. a groove; 5. a through hole; 6. a first region; 7. a second region; 8. and scribing the street.

Detailed Description

The principles and features of the present invention are described below in conjunction with the following drawings, the examples given are only intended to illustrate the present invention and are not intended to limit the scope of the present invention.

Example one

Referring to fig. 1-6, the present embodiment provides a semiconductor wafer, which includes a chip layer, a wafer layer 2 and a metal layer 3 connected in sequence from top to bottom; the chip layer of the embodiment comprises a plurality of chips 1 arranged on the wafer layer 2 at intervals, preferably a plurality of chips 1 are uniformly arranged at intervals to form a grid distribution form, so that the uniformity of cutting and forming is ensured; the interval between two adjacent chips 1 forms a scribe line 8 (also called as a scribe line) on the wafer layer 2, and as shown in fig. 1 and 2, it can be seen that the scribe line 8 of the present embodiment is a plurality of cross scribe lines.

In combination with the problems described in the background art, the first improvement of the semiconductor wafer of this embodiment is that the scribe line 8 formed by the wafer layer 2 and the chip 1 is provided with a plurality of grooves 4, and due to the existence of the grooves 4, the cutting stress is prevented from being dispersed too much, the cutting efficiency is improved, unexpected wafer cracking during the cutting process is prevented, and further, the yield of the wafer is improved.

as shown in fig. 3-6, based on the above structure, in order to further improve the cutting efficiency and the yield of the wafer, the embodiment further has a plurality of through holes 5 on the metal layer 3, so as to prevent the cutting stress applied to the metal layer 3 from being dispersed, thereby facilitating the cutting of the metal layer 3.

Preferably, in the direction perpendicular to the wafer layer 2, the plurality of through holes 5 and the plurality of grooves 4 of the present embodiment are arranged in a one-to-one correspondence, that is, the through holes 5 are located right below the grooves 4, the through holes 5 and the grooves 4 have the same shape and size, and the projection of the grooves 4 on the metal layer 3 coincides with the through holes 5. The design considers that the metal layer 3 can also influence the cutting of the upper wafer layer 2 because the metal layer 3 and the wafer layer 2 are fixedly connected during cutting, and the grooves 4 on the wafer layer 2 and the through holes 5 on the metal layer 3 are designed to be correspondingly matched, so that the cutting resistance of the lower surface of the wafer layer 2 is further reduced, the cutting stress is prevented from being dispersed, the cutting efficiency can be further improved, and the wafer cutting yield is ensured.

In addition, the present embodiment also makes a specific improvement on the structural form of the groove 4 and the through hole 5, as shown in fig. 1, 2, 5 and 6, in the direction parallel to the surface of the scribe lane 8, the groove 4 and the through hole 5 of the present embodiment are both triangular, and certainly may be rhombic, and the direction pointed at the corner of the triangular through hole 5 or the groove 4 is the length direction of the scribe lane 8, so that the scribe lane 8 can be broken in a waiting manner along the direction pointed at the corner of the groove 4 or the through hole 5 during cutting, thereby improving the cutting efficiency.

In order to ensure the structural strength of the wafer itself, the depth range of the groove 4 is limited in the embodiment, and the depth of the groove 4 is preferably 18um to 28um, so that the structural strength of the wafer is ensured, and the cutting effect is also considered.

In addition, in order to prevent the two crossing scribe lanes 8 from affecting each other during cutting, the scribe lanes 8 are divided into a first region 6 and a second region 7 in the present embodiment, the first region 6 is a staggered region of the two crossing scribe lanes 8, the regions except the first region 6 are the second region 7, and the present embodiment is provided with the above-mentioned groove 4 in the second region 7.

Example two

The present embodiment provides an electronic device having a semiconductor wafer as in the first embodiment, and the electronic device of the present embodiment may be any electronic device having a semiconductor integrated circuit, such as a controller, a mobile phone, a digital camera, a computer CPU, and the like.

In the description of the present invention, it should be understood that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.

In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral connections. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

Although embodiments of the present invention have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art without departing from the scope of the present invention.

Claims

1. The semiconductor wafer is characterized by comprising a chip layer, a wafer layer (2) and a metal layer (3) which are sequentially connected; the chip layer comprises a plurality of chips (1) which are arranged on the wafer layer (2) at intervals, and scribing channels (8) are formed on the wafer layer (2) at intervals between every two adjacent chips (1); a plurality of grooves (4) are arranged on the scribing channel (8) at intervals.

2. The semiconductor wafer according to claim 1, characterized in that the metal layer (3) is provided with a plurality of through holes (5).

3. the semiconductor wafer according to claim 2, wherein a plurality of the through holes (5) and a plurality of the grooves (4) are arranged in a one-to-one correspondence in a direction perpendicular to the wafer layer (2).

4. The semiconductor wafer according to claim 3, wherein the through hole (5) and the groove (4) are the same in shape and size.

5. The semiconductor wafer according to claim 4, wherein a projection of the recess (4) on the metal layer (3) coincides with the via (5).

6. A semiconductor wafer according to any of claims 1 to 5, characterized in that the cross-section of the grooves (4) in a direction parallel to the surface of the scribe lanes (8) is triangular or diamond-shaped.

7. The semiconductor wafer according to any of claims 1 to 5, wherein the depth of the grooves (4) is between 18um and 28 um.

8. A semiconductor wafer according to any of claims 1 to 5, characterized in that a plurality of said scribe lanes (8) are arranged staggered laterally and longitudinally.

9. the semiconductor wafer according to claim 8, wherein the scribe lanes (8) comprise a first region (6) and a second region (7), the first region (6) being a staggered region intersecting the two scribe lanes (8), the second region (7) having the grooves (4) therein.

10. An electronic device having the semiconductor wafer of any one of claims 1-9.