CN209640752U - A kind of sync control device of high performance computation SoC - Google Patents
A kind of sync control device of high performance computation SoC Download PDFInfo
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- CN209640752U CN209640752U CN201920533403.0U CN201920533403U CN209640752U CN 209640752 U CN209640752 U CN 209640752U CN 201920533403 U CN201920533403 U CN 201920533403U CN 209640752 U CN209640752 U CN 209640752U
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Abstract
The utility model discloses the sync control devices of high performance computation SoC a kind of, comprising: the pulse input outside the detection of pulse detection module, when detecting external pulse input, triggering gate clock module refresh clock Configuration Values are the first clock Configuration Values；Clock selection module obtains external input clock according to the first clock Configuration Values, and external input clock is connected to SoC operational module, runs SoC operational module according to external input clock；When detecting that external pulse input stops, pulse detection module triggering gate clock module refresh clock Configuration Values are second clock Configuration Values, clock selection module disconnects the connection of external input clock and SoC operational module according to second clock Configuration Values, and SoC operational module is out of service.The technical solution of the utility model can make the working condition of each concatenated SoC synchronous, avoid the occurrence of the case where partial pressure imbalance causes SoC to damage.
Description
Technical field
The utility model belongs to field of communication technology, is to be related to the synchronous control of high performance computation SoC a kind of more specifically
Device processed.
Background technique
SoC (System on Chip) is known as system level chip, is one and is integrated into computer or other electronic systems
The integrated circuit of one chip can handle the even more high-frequency signal of digital signal, analog signal, mixed signal.
In system application, when needing biggish operational capability, more high performance computation SoC can be allowed to form one together
A entirety cooperates.Since the calculation resources of high performance computation SoC are very big, power consumption can relatively other functions SoC it is big
Very much, so that electric current is excessive, electric current is excessive for the increase meeting of power consumption, and requirement of system design can be made very high, the design meeting of whole system
Become very complicated.
The power consumption and performance of SoC is that a pair of of needs are combined into two factors for trading off and considering, because when SoC's
When operating voltage is relatively high, the working frequency limit of SoC also can be relatively high, and correspondingly the operational capability of SoC is relatively high,
But the power consumption of SoC also compares height simultaneously.And when the operating voltage of SoC is relatively low, the working frequency limit of SoC also can be opposite
Lower, correspondingly the operational capability of SoC is relatively low, but the power consumption of SoC also can be relatively low simultaneously.In high-performance SoC system
In, generally this index of power consumption of power can be calculated with unit to measure the superiority and inferiority of system, wherein the power consumption that unit calculates power refers to
SoC completes power consumption corresponding when unit computing capability, can reflect power consumption and two factors of performance simultaneously.In more high-performance
In the system that SoC is formed by concatenated mode, when the working condition of different SoC is asynchronous, it will lead to the power consumption of SoC not
Balance and the partial pressure of entire series-fed will be uneven, it is possible that the feelings of system cisco unity malfunction under serious situation
Condition, or even SoC can be caused to burn out because of the overtension of certain SoC.
Utility model content
The utility model embodiment provides the synchronizing device of high performance computation SoC a kind of, with solve SoC partial pressure it is uneven and
The problem of damage system.
A kind of sync control device of high performance computation SoC, comprising: pulse detection module, gated clock module, clock choosing
Select module and SoC operational module；
The pulse detection module, for detecting external pulse input, when detecting external pulse input, triggering
The gated clock module refresh clock Configuration Values are the first clock Configuration Values；When the pulse input for detecting the outside stops
When, triggering the gated clock module to update the clock Configuration Values is second clock Configuration Values；
The gated clock module is for when detecting external pulse input, updating the clock Configuration Values
One clock Configuration Values；When the pulse input for detecting the outside stops, updating the clock Configuration Values and match for second clock
Set value；
The clock selection module, for obtaining external input clock according to the first clock Configuration Values, and will be described
External input clock is connected to the SoC operational module；The external input clock and institute are disconnected according to second clock Configuration Values
State the connection of SoC operational module；
The SoC operational module, including N number of concatenated high performance computation SoC, for being transported according to the external input clock
Row；Out of service when the connection of the external input clock disconnects, wherein N is the positive integer greater than 1.
Compared with prior art, the sync control device of above-mentioned high performance computation SoC, it is each in SoC operational module by making
The concatenated SoC same time starts to work, and the same time stops working, and works in same clock frequency, can make each string
The working condition of the SoC of connection is synchronous, and power consumption keeps the state of balance, and operating voltage is also at the state of balance, avoids the occurrence of point
The case where pressure imbalance causes SoC to damage.On the other hand, due to using gated clock, the power consumption of a part is saved, and pass through
Unified clock frequency is set, SoC operational module can also be made to remain that working in unit calculates power operating point least in power-consuming.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of the technical scheme in the embodiment of the utility model
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only that this is practical new
Some embodiments of type for those of ordinary skill in the art without any creative labor, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the method flow diagram of the sync control device of high performance computation SoC in an embodiment of the present invention；
Fig. 2 is a functional block diagram of the sync control device of high performance computation SoC in an embodiment of the present invention；
Fig. 3 is the concatenated signal of SOC of the sync control device of high performance computation SoC in an embodiment of the present invention
Figure；
Fig. 4 is another functional block diagram of the sync control device of high performance computation SoC in an embodiment of the present invention；
Fig. 5 is a specific example figure of the sync control device of high performance computation SoC in an embodiment of the present invention.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
It clearly and completely describes, it is clear that the embodiments are a part of the embodiments of the present invention, rather than whole implementation
Example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without creative efforts
The every other embodiment obtained, fall within the protection scope of the utility model.
In one embodiment, as shown in Figure 1, providing a kind of synchronously control of the sync control device of high performance computation SoC
Method includes the following steps:
S10: the pulse input outside the detection of pulse detection module, when detecting external pulse input, triggering gate
Clock module refresh clock Configuration Values are the first clock Configuration Values.
Wherein, external pulse input refers to external system, such as MCU, to the pulse input of SoC operational module, pulse inspection
Surveying module can be detected whether by the variation of the low and high level of the pin of SoC operational module in the presence of external pulse input.
When the variation of low and high level occurs for the pin of SoC operational module, such as being turned to high level, or being turned to low level,
External system may input SoC operational module and instruct at this time, and SoC operational module is made to be transmitted the behaviour such as data or transmission address
Make, pulse detection module can be determined that the pulse input in the presence of outside at this time.When the pin of SoC operational module does not have low and high level
Variation when, be in idle condition at this time for SoC operational module, pulse detection module can be determined that not external pulse is defeated
Enter.
Clock Configuration Values refer to the clock Configuration Values in gated clock module, and the clock by the way that gated clock is arranged configures
Value can make gated clock module select external input clock, and external input clock is input to SoC operational module, or
The connection of external input clock and SoC operational module is disconnected.Wherein, the first clock Configuration Values are to instigate gated clock module will
External input clock is input to the value of SoC operational module.It can specifically be configured according to actual needs, here with no restrictions.
S20: clock selection module obtains external input clock according to the first clock Configuration Values, and external input clock is connected
It is connected to SoC operational module, runs SoC operational module according to external input clock, wherein SoC operational module is N number of concatenated
High performance computation SoC, N are the positive integer greater than 1.
Wherein, external input clock refers to the externally input clock of SoC operational module.
Specifically, when the clock Configuration Values of gated clock module are updated to the first clock Configuration Values, clock selection module
External input clock is obtained, and external input clock is connected to SoC operational module, makes SoC operational module according to external input
Clock operation, SoC operational module initially enters working condition at this time.Wherein, SoC operational module is N number of concatenated high-performance fortune
SoC is calculated, N is the positive integer greater than 1.It since each high performance computation SoC being together in series in SoC operational module, and is all
The Gao Xingtong operation SoC one external input clock of unified input being together in series, therefore each SoC in SoC operational module
Simultaneously into when work, and have unified working frequency, so as to so that the partial pressure for the high performance computation SoC being together in series is in
The state of balance avoids dividing unbalanced situation appearance and damaging SoC.It optionally, can be with when designing SoC operational module
The identical or close SoC of resistance is together in series, each SoC in such SoC operational module can be regarded as equivalent resistance, into
One step balances the partial pressure of each high performance computation SoC.
S30: when detecting that external pulse input stops, pulse detection module triggering gate clock module refresh clock
Configuration Values are second clock Configuration Values, and clock selection module disconnects external input clock and SoC work according to second clock Configuration Values
Make the connection of module, SoC operational module is out of service.
Wherein, second clock Configuration Values refer to what gated clock module disconnected external input clock and SoC operational module
Value.
Specifically, when detecting that external pulse input stops, pulse detection module triggering gate clock module updates
Clock Configuration Values are second clock Configuration Values.When the clock Configuration Values of gated clock module are updated to second clock Configuration Values,
Clock selection module disconnects the connection of external input clock and SoC operational module, and SoC operational module is out of service at this time.It is logical
Cross and SoC operational module be uniformly accessed into external input clock, SoC operational module brings into operation, or uniformly by external input when
Clock and SoC operational module disconnect, and SoC operational module is out of service, keeps each SoC in SoC operational module synchronous always
State avoids the case where damaging SoC since the asynchronous caused partial pressure of SoC is uneven.
Optionally, clock selection module is connected with clock output module, when gated clock module refresh clock Configuration Values
When, clock selection module obtains the clock of clock output module output as external input clock.
Specifically, when gated clock module refresh clock Configuration Values are the first clock Configuration Values or second clock Configuration Values
When, clock selection module obtains the clock of clock output module output as external input clock.Alternatively, working as gated clock module
When refresh clock Configuration Values are the first clock Configuration Values, clock selection module obtains the clock of clock output module as external defeated
Enter clock, and when gated clock module refresh clock Configuration Values are second clock Configuration Values, when clock selection module does not obtain
The clock of clock output module output.
Optionally, clock output module includes the first clock output unit and second clock output unit, wherein when first
Clock output unit can export single times of clock, and second clock output unit can export frequency doubling clock.Optionally, second clock is defeated
The multiple of the frequency doubling clock of unit output is based on the frequency of the first clock output unit out.
When gated clock module refresh clock Configuration Values, when clock selection module is according to clock selecting parameter selection the first
The output clock of clock output unit or second clock output unit is as external input clock.
Wherein, clock selecting parameter can be arranged accordingly by external system (such as application software), clock selecting
The clocks that module is exported according to the first clock output unit of different selections of clock selecting parameter, or selection second clock output
The clock of unit output is as external input clock.For example, when clock selection parameter is parameter a period of time, clock selection module selection
The clock of first clock output unit output is as external input clock；When clock selection parameter is parameter two, clock selecting
The clock that module selects second clock output unit to export is as external input clock.Clock selecting parameter can be according to practical need
It is specifically set, herein with no restrictions.
In a specific embodiment, second clock output unit is phase-locked loop clock output unit.
Wherein, phase-locked loop clock output unit includes the structure of phaselocked loop, the structure of phaselocked loop in the present embodiment, in addition to
Play the role of being locked into except clock frequency, be also used to export with the frequency doubling clock of the first clock output unit certain multiple,
In, times for the clock frequency that the clock frequency that second clock output unit is exported is exported relative to the first clock output unit
Number can be set to fixed multiple, can also be set as different multiples according to the input of external system.Optionally, second
The clock frequency that clock output unit is exported and the clock frequency that the first clock output unit is exported are not related, i.e., and second
When the clock frequency that is exported of bracelet output unit based on other preset frequency.Wherein, in addition preset
Frequency can be configured according to actual needs, be not specifically limited here.
Optionally, gated clock module includes clock signal unit and clock gating unit, when the pulse for detecting outside
When input, the clock Configuration Values in clock signal unit refresh clock signal element are the first clock Configuration Values, meanwhile, clock gate
Controlling the clock Configuration Values in unit refresh clock door control unit is the first clock Configuration Values.
Specifically, clock Configuration Values are individually present in clock signal unit and clock gating unit, it is external when detecting
When pulse input, it is the first clock that pulse detection module, which triggers the clock Configuration Values in clock signal unit refresh clock signal element,
Configuration Values, and triggering the clock Configuration Values in clock gating unit refresh clock door control unit simultaneously is the first clock Configuration Values.
Clock signal unit is connected with clock selection module, clock selection module updated according to clock signal unit
One clock Configuration Values obtain external input clock.
Clock gating unit is connected with clock selection module and SoC operational module, and clock gating unit is according to update
External input clock is connected to SoC operational module by the first clock Configuration Values, at this point, SoC operational module is in external input clock
Frequency under run.
Optionally, clock signal unit includes the first allocating cache device and the first configuration register, external when detecting
When pulse input, the first clock Configuration Values are updated to the first configuration register by the first allocating cache device.
Clock gating unit includes the second allocating cache device and the second configuration register, when the pulse input for detecting outside
When, the first clock Configuration Values are updated to the second configuration register by the second allocating cache device.
Specifically, when detecting external pulse input, first in pulse detector triggering clock signal unit matches
It sets buffer and the first clock Configuration Values is updated to the first configuration register, while triggering the second configuration in clock gating unit
First clock Configuration Values are updated to the second configuration register by buffer.
Optionally, when the first clock Configuration Values are updated to the first configuration register by the first allocating cache device, clock choosing
It selects module and obtains external input clock；
When the first clock Configuration Values are updated to the second configuration register by the second allocating cache device, clock gating unit will
Clock selection module is connected to SoC operational module.
Specifically, when the first clock Configuration Values are updated to the first configuration register by the first allocating cache device, clock choosing
It selects module and obtains the clock of clock output module output as external input clock.And work as the second allocating cache device for the first clock
When Configuration Values are updated to the second configuration register, clock selection module is connected to SoC operational module by clock gating unit, due to
Clock selection module obtains the clock of clock output module output as external input clock, therefore external input clock connects
To SoC operational module, SoC operational module is run according to external input clock at this time.
Optionally, when detecting that external pulse input stops, the first allocating cache device by second clock Configuration Values more
Newly to the first configuration register, second clock Configuration Values are updated to the second configuration register by the second allocating cache device；
When second clock Configuration Values are updated to the second configuration register by the second allocating cache device, clock gating unit will
Clock selection module is disconnected with SoC operational module.
Specifically, when detecting that external pulse input stops, pulse detection module is triggered in clock signal unit
Second clock Configuration Values are updated to the first configuration register by the first allocating cache device, and clock selection module can maintain to obtain at this time
The clock for taking clock output module to export can also stop the clock for obtaining the output of clock output module.It is external when detecting
When pulse input stops, pulse detection module can trigger the second allocating cache device in clock gating unit for second clock simultaneously
Configuration Values are updated to the second configuration register, at this time clock gating unit according to second clock Configuration Values by clock selection module with
SoC operational module disconnects, and SoC operational module is out of service.
Compared with prior art, the sync control device of high performance computation SoC provided by the embodiment of the utility model is same
Control method is walked, by making each concatenated SoC same time in SoC operational module start to work, the same time stops working, and
Same clock frequency is worked in, the working condition of each concatenated SoC can be made synchronous, power consumption keeps the state of balance, work
Voltage is also at the state of balance, avoids the occurrence of the case where partial pressure imbalance causes SoC to damage.On the other hand, due to using door
Clock is controlled, the power consumption of a part is saved, and by the way that unified clock frequency is arranged, SoC operational module can also be made to protect always
It holds and works in unit calculation power operating point least in power-consuming.
It should be understood that the size of the serial number of each step is not meant that the order of the execution order in above-described embodiment, each process
Execution sequence should be determined by its function and internal logic, without cope with the utility model embodiment implementation process constitute it is any
It limits.
In one embodiment, the sync control device of high performance computation SoC a kind of is provided, high performance computation SoC's is same
The synchronisation control means for walking high performance computation SoC in control device and above-described embodiment corresponds.As shown in Fig. 2, the high property
The sync control device of energy operation SoC includes pulse detection module 10, gated clock module 20, clock selection module 30 and SoC
Operational module 40.Detailed description are as follows for each functional module:
Pulse detection module 10, for detecting external pulse input, when detecting external pulse input, trigger gate
Control 20 refresh clock Configuration Values of clock module are the first clock Configuration Values；When detecting that external pulse input stops, triggering
20 refresh clock Configuration Values of gated clock module are second clock Configuration Values；
Gated clock module 20, for when detecting external pulse input, refresh clock Configuration Values to be the first clock
Configuration Values；When detecting that external pulse input stops, refresh clock Configuration Values are second clock Configuration Values；
Clock selection module 30, for obtaining external input clock according to the first clock Configuration Values, and when by external input
Clock is connected to SoC operational module 40；The company of external input clock and SoC operational module 40 is disconnected according to second clock Configuration Values
It connects；
SoC operational module 40, including N number of concatenated high performance computation SoC, for being run according to external input clock；When
Out of service when the connection of external input clock disconnects, wherein N is the positive integer greater than 1.
As shown in figure 3, N number of high performance computation SoC, which is together in series, forms SoC operational module 40, refer to N number of high-performance
Operation SoC is connected in series between the VDD_SYS and VSS_SYS of system power supply, and SoC operational module is by input pin
UP_SYNC output, is exported by output pin DN_SYNC, is connected to the input pin UP_SYNC of downlink SoC, external to control synchronous
Signal processed is input to the input pin UP_SYNC of first SoC, then is exported by the output pin DN_SYNC of first SoC to
The connection and so on of the input pin UP_SYNC, other SoC of two SoC.
Optionally, it as shown in figure 4, the sync control device of high performance computation SoC further includes clock output module 50, is used for
Export external input clock；
Clock selection module 30 is also used to connect with clock output module 50, when 20 refresh clock of gated clock module is matched
When setting value, the clock of the output of clock output module 50 is obtained as external input clock.
Optionally, clock output module 50 includes the first clock output unit and second clock output unit, the first clock
Output unit is for exporting single times of clock, and second clock output unit is for exporting frequency doubling clock；
Clock selection module 30 is also used to be joined when 20 refresh clock Configuration Values of gated clock module according to clock selecting
Number selects the output clock of the first clock output unit or second clock output unit as external input clock.
Optionally, second clock output unit is phase-locked loop clock output unit.
Optionally, gated clock module 20 includes clock signal unit and clock gating unit；
Clock signal unit, for when detecting external pulse input, the clock in refresh clock signal element to be matched
Setting value is the first clock Configuration Values；
Clock gating unit, for when detecting external pulse input, the clock in refresh clock door control unit to be matched
Setting value is the first clock Configuration Values；
Clock selection module 30 is also used to be connected with clock signal unit, first updated according to clock signal unit
External input clock is connected to SoC operational module by clock Configuration Values.
Optionally, clock signal member includes the first allocating cache device and the first configuration register, and clock signal unit is also used
In when detecting external pulse input, the first clock Configuration Values are updated to the first configuration and deposited by the first allocating cache device
Device；
Clock gating unit includes the second allocating cache device and the second configuration register, and clock gating unit is also used to when inspection
When measuring external pulse input, the first clock Configuration Values are updated to the second configuration register by the second allocating cache device.
Optionally, clock selection module 30 is also used to that the first clock Configuration Values are updated to first when the first allocating cache device
When configuration register, external input clock is obtained；
Clock gating unit is also used to that the first clock Configuration Values are updated to the second configuration deposit when the second allocating cache device
When device, clock selection module 30 is connected to SoC operational module 40.
Optionally, clock signal unit is also used to when detecting that external pulse input stops, the first allocating cache device
Second clock Configuration Values are updated to the first configuration register；
Clock gating unit is also used to when detecting that external pulse input stops, when the second allocating cache device is by second
Clock Configuration Values are updated to the second configuration register；It is posted when second clock Configuration Values are updated to the second configuration by the second allocating cache device
When storage, clock selection module 30 and SoC operational module 40 is disconnected.
As shown in figure 5, it is an exemplary functional block diagram of the utility model embodiment.PlsDet is pulse detection mould
Block 10, Buf0 are the first allocating cache device, and Reg0 is the first configuration register, and Buf1 is the second allocating cache device, Reg1 the
Two configuration registers, CLKI are the first clock output unit, and PLL is that (second clock output is single for phase-locked loop clock output unit
Member), CkMux is clock selection module 30, and Core_i is SOC operational module 40.
The specific restriction of sync control device about high performance computation SoC may refer to above for high performance computation
The restriction of the synchronisation control means of SoC, details are not described herein.It is each in the sync control device of above-mentioned high performance computation SoC
Module is all realized by hardware and combinations thereof.Above-mentioned each module is that example, in hardware is embedded in or independently of in computer equipment
Processor in, execute the corresponding operation of above modules in order to which processor calls.
It is apparent to those skilled in the art that for convenience of description and succinctly, only with above-mentioned each function
Can unit, module division progress for example, in practical application, can according to need and by above-mentioned function distribution by different
Functional unit, module are completed, i.e., the internal structure of described device is divided into different functional unit or module, more than completing
The all or part of function of description.
Embodiment described above is only to illustrate the technical solution of the utility model, rather than its limitations；Although referring to before
Embodiment is stated the utility model is described in detail, those skilled in the art should understand that: it still can be with
It modifies the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；And
These are modified or replaceed, the spirit for various embodiments of the utility model technical solution that it does not separate the essence of the corresponding technical solution
And range, it should be included within the scope of protection of this utility model.
Claims (8)
1. a kind of sync control device of high performance computation SoC characterized by comprising pulse detection module, gated clock mould
Block, clock selection module and SoC operational module；
The pulse detection module, for detecting external pulse input, when detecting external pulse input, described in triggering
Gated clock module refresh clock Configuration Values are the first clock Configuration Values；When the pulse input for detecting the outside stops,
Triggering the gated clock module to update the clock Configuration Values is second clock Configuration Values；
When the gated clock module for updating the clock Configuration Values when detecting external pulse input is first
Clock Configuration Values；When the pulse input for detecting the outside stops, updating the clock Configuration Values is second clock Configuration Values；
The clock selection module, for obtaining external input clock according to the first clock Configuration Values, and by the outside
Input clock is connected to the SoC operational module；The external input clock and the SoC are disconnected according to second clock Configuration Values
The connection of operational module；
The SoC operational module, including N number of concatenated high performance computation SoC, for being run according to the external input clock；
Out of service when the connection of the external input clock disconnects, wherein N is the positive integer greater than 1.
2. the sync control device of high performance computation SoC as described in claim 1, which is characterized in that further include clock output
Module, for exporting the external input clock；
The clock selection module is also used to connect with the clock output module, described in gated clock module update
When clock Configuration Values, the clock of the clock output module output is obtained as the external input clock.
3. the sync control device of high performance computation SoC as claimed in claim 2, which is characterized in that the clock output mould
Block includes the first clock output unit and second clock output unit, and the first clock output unit is for when exporting single times
Clock, the second clock output unit is for exporting frequency doubling clock；
The clock selection module is also used to be selected when the gated clock module updates the clock Configuration Values according to clock
It is defeated as the outside to select the output clock of the first clock output unit or the second clock output unit described in parameter selection
Enter clock.
4. the sync control device of high performance computation SoC as claimed in claim 3, which is characterized in that the second clock is defeated
Unit is phase-locked loop clock output unit out.
5. the sync control device of high performance computation SoC according to any one of claims 1-4, which is characterized in that the door
Controlling clock module includes clock signal unit and clock gating unit；
The clock signal unit, for when detecting the pulse input of the outside, updating in the clock signal unit
The clock Configuration Values be the first clock Configuration Values；
The clock gating unit, for updating in the clock gating unit when detecting the pulse input of the outside
The clock Configuration Values be the first clock Configuration Values；
The clock selection module is also used to be connected with the clock signal unit, is updated according to the clock signal unit
The first clock Configuration Values the external input clock is connected to the SoC operational module.
6. the sync control device of high performance computation SoC as claimed in claim 5, which is characterized in that the clock signal list
Member includes the first allocating cache device and the first configuration register, and the clock signal unit is also used to when the pulse for detecting outside
When input, the first clock Configuration Values are updated to first configuration register by the first allocating cache device；
The clock gating unit includes the second allocating cache device and the second configuration register, and the clock gating unit is also used to
When detecting external pulse input, the first clock Configuration Values are updated to described second by the second allocating cache device
Configuration register.
7. the sync control device of high performance computation SoC as claimed in claim 6, which is characterized in that the clock selecting mould
Block is also used to obtain when the first clock Configuration Values are updated to first configuration register by the first allocating cache device
Take the external input clock；
The clock gating unit is also used to that the first clock Configuration Values are updated to second when the second allocating cache device
When configuration register, the clock selection module is connected to the SoC operational module.
8. the sync control device of high performance computation SoC as claimed in claim 7, which is characterized in that the clock signal list
Member is also used to when the pulse input for detecting the outside stops, and the first allocating cache device configures the second clock
Value is updated to first configuration register；
The clock gating unit is also used to when the pulse input for detecting the outside stops, the second allocating cache device
The second clock Configuration Values are updated to second configuration register；When the second allocating cache device is by described second
When clock Configuration Values are updated to second configuration register, the clock selection module and the SoC operational module are disconnected and connected
It connects.
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|---|---|---|---|
| CN201920533403.0U CN209640752U (en) | 2019-04-16 | 2019-04-16 | A kind of sync control device of high performance computation SoC |
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| CN201920533403.0U CN209640752U (en) | 2019-04-16 | 2019-04-16 | A kind of sync control device of high performance computation SoC |
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| CN209640752U true CN209640752U (en) | 2019-11-15 |
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| CN201920533403.0U Expired - Fee Related CN209640752U (en) | 2019-04-16 | 2019-04-16 | A kind of sync control device of high performance computation SoC |
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