CN209627344U - A kind of input signal holding circuit - Google Patents
A kind of input signal holding circuit Download PDFInfo
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- CN209627344U CN209627344U CN201920539515.7U CN201920539515U CN209627344U CN 209627344 U CN209627344 U CN 209627344U CN 201920539515 U CN201920539515 U CN 201920539515U CN 209627344 U CN209627344 U CN 209627344U
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- 230000009471 action Effects 0.000 abstract description 4
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- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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Abstract
The utility model relates to signal control field, spy is related to a kind of input signal holding circuit.The utility model obtains control signal using the clamping action of the partial pressure and Zener diode of the 6th resistance and 3rd resistor, and it is indirect by MCU control signal directly control, input control signal is utilized to control the conducting of bleeder circuit P-channel MOSFET pipe in circuit simultaneously, ensure to control maintaining certainly for input signal, the input signal of driving circuit remains unchanged when realizing microcontroller power down.
Description
Technical field
The utility model relates to signal control field, spy is related to a kind of input signal holding circuit.
Background technique
The low and high level that normal driving circuit input signal is provided from microcontroller, after microcontroller power down,
Input signal will be unable to maintain original level state and high-impedance state is presented.
In battery management system, the switching characteristic of Chang Liyong MOSFET goes the cutting of control battery supplying power for outside major loop
And closure needs battery management system microcontroller is restarted or is upgraded while in the scene of some uninterruptible power supplies
In the process, the on state of MOSFET does not change, and maintains original state.In addition in the design for pursuing extremely low power dissipation
In, we also can cut off other peripheral hardwares other than system base chip in the state of battery management system deep-sleep
Power supply is to achieve the purpose that reduce power consumption.Under above-mentioned various scenes, the control dropout (control of MOSFET driving can mean that
Signal processed is in high impedance status), in order to guarantee the external normal power supply of battery, we just need the conducting of major loop MOSFET
State maintains the state before controlling dropout and can maintain steadily in the long term.
Fig. 2 is to select from a kind of patent 105322930A (" short time power down holding electricity for DC solid-state power controller
Road "), there is a situation where power down for the program, the first capacitor C1 in figure in RC short time power down holding circuit and described
Under the collective effect of one resistance R1, so that the grid of the first power MOSFET in the power MOSFET driving circuit drives
Dynamic voltage can maintain certain voltage level during power down, can maintain the first power MOSFET in a short time
On state.
Exist in the above-mentioned prior art referred to apparent the disadvantage is that capacitor C1 can continue externally to discharge, voltage meeting
It is continuous to reduce, until gate drive voltage needed for power MOSFET (Q1) conducting in figure can not be provided, cause MOSFET disconnected
It opens, the program can not maintain the state of MOSFET for a long time.In long-time power down or actively cut off the scene of control circuit power supply
Under, the program is clearly to be unable to satisfy requirement, for this reason, it may be necessary to which the long-time power down for designing a kind of power MOSFET keeps electricity
Road.
Summary of the invention
In view of the deficiencies of the prior art, the utility model provides a kind of input signal holding circuit.The utility model benefit
Obtain control signal with the clamping action of the partial pressure and Zener diode of the 6th resistance and 3rd resistor, and it is indirect by
MCU control signal directly controls, while input control signal is utilized to control leading for bleeder circuit P-channel MOSFET pipe in circuit
It is logical, it is ensured that control maintaining certainly for input signal, the input signal of driving circuit remains unchanged when realizing microcontroller power down.
The technical solution of the utility model is: a kind of input signal holding circuit, including N-channel MOS FET pipe, P-channel
MOSFET pipe, first resistor, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, Zener
Diode, the first optocoupler, the second optocoupler, the first optocoupler, the second optocoupler control terminal respectively with control signal 2 and control signal 1
Connection, it is characterised in that: the emitter of the second optocoupler is grounded, the emitter of the first optocoupler, driving circuit input, the 7th resistance
One end is connect with the collector of the second optocoupler, and the cathode of Zener diode is connect with the collector of the second optocoupler, Zener diode
Anode connect with the emitter of the second optocoupler, 3rd resistor is in parallel with Zener diode, the other end and N-channel of the 7th resistance
The grid of MOSFET pipe connects, the source electrode ground connection of N-channel MOS FET pipe, the drain series first resistor of N-channel MOS FET pipe, the
Two resistance connect to power supply, and one end of the 5th resistance is connect with the tie point of first resistor, second resistance, the 5th resistance it is another
End is connect with the grid of P-channel MOSFET pipe, yin of the drain electrode of P-channel MOSFET pipe after the 6th resistance with Zener diode
Pole connection, the source electrode of P-channel MOSFET pipe connects to power supply, the 4th resistance both ends collector with power supply and the first optocoupler respectively
Connection.
According to a kind of input signal holding circuit as described above, it is characterised in that: N-channel MOS FET pipe replaces with NPN
Triode, P-channel MOSFET pipe replace with PNP triode, and the base stage of triode replaces the grid of MOSFET pipe, the collection of triode
Electrode replaces the drain electrode of MOSFET pipe, and the emitter of triode replaces the source electrode of MOSFET pipe.
According to a kind of input signal holding circuit as described above, it is characterised in that: the first optocoupler and the replacement of the second optocoupler
Base stage for NPN triode, triode is connect with control signal, and the emitter of triode replaces the emitter of optocoupler, triode
Collector replace optocoupler collector.
According to a kind of input signal holding circuit as described above, it is characterised in that: first resistor, second resistance, third
Resistance, the 4th resistance, the resistance that the 6th resistance is 56K Ω.
According to a kind of input signal holding circuit as described above, it is characterised in that: the 5th resistance, the 7th resistance are 1K Ω
Resistance.
The beneficial effects of the utility model are: first is that the input signal of driving circuit is kept not when realizing microcontroller power down
Become.Second is that changing control signal input voltage by force by the first optocoupler of control, the second optocoupler, original balance is broken with this,
Change the state that input control signal maintains.Third is that improvement is in the front end of driving circuit, rather than the driving of existing scheme is electric
After road, the disconnection of this programme MOSFET and closure can be faster relative to the existing scheme response time for increasing capacitor C1.Fourth is that
The holding of voltage is from external uninterrupted voltage, relative to the gate drive voltage during existing scheme-power down from electricity
Hold C1, the utility model can maintain the time of gate drive voltage longer, more stable during power down.
Detailed description of the invention
Fig. 1 is the circuit diagram of the utility model.
Fig. 2 is existing power-down retaining circuit)
Description of symbols: N-channel MOS FET pipe Q1, P-channel MOSFET pipe Q2, first resistor R1, second resistance R2,
Three resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9,
Three MOSFET pipe Q3, Zener diode D1, the first optocoupler U1A, the second optocoupler U2A, power supply VCC.
Specific embodiment
The technical solution of the utility model is described further below in conjunction with attached drawing.
As shown in Figure 1, the input signal holding circuit of the utility model, including N-channel MOS FET pipe Q1, P-channel
MOSFET pipe Q2, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6,
7th resistance R7, Zener diode D1, the first optocoupler U1A, the second optocoupler U2A, the control of the first optocoupler U1A, the second optocoupler U2A
End is connect with control signal 2 and control signal 1 respectively, the emitter ground connection of the second optocoupler U2A, the emitter of the first optocoupler U1A,
Driving circuit input, the 7th resistance R7 one end connect with the collector of the second optocoupler U2A, the cathode of Zener diode D1 and the
The collector of two optocoupler U2A connects, and the anode of Zener diode D1 is connect with the emitter of the second optocoupler U2A, 3rd resistor R3
In parallel with Zener diode D1, the other end of the 7th resistance R7 is connect with the grid of N-channel MOS FET pipe Q1, N-channel MOS FET
The source electrode of pipe Q1 is grounded, and drain series first resistor R1, the second resistance R2 of N-channel MOS FET pipe Q1 is connect with power supply VCC, the
One end of five resistance R5 is connect with the tie point of first resistor R1, second resistance R2, the other end and P-channel of the 5th resistance R5
The grid of MOSFET pipe Q2 connects, cathode of the drain electrode of P-channel MOSFET pipe Q2 after the 6th resistance R6 with Zener diode D1
Connection, the source electrode of P-channel MOSFET pipe Q2 connect with power supply VCC, the 4th both ends resistance R4 respectively with power supply VCC and the first optocoupler
The collector of U1A connects.
In the utility model, N-channel MOS FET pipe Q1 could alternatively be NPN triode, and P-channel MOSFET pipe Q2 can be replaced
It is changed to PNP triode, the base stage of triode replaces the grid of MOSFET pipe, and the collector of triode replaces the leakage of MOSFET pipe
Pole, the emitter of triode replace the source electrode of MOSFET pipe.
In the utility model, the first optocoupler U1A and the second optocoupler U2A could alternatively be NPN triode.The base stage of triode
It is connect with control signal, the emitter of triode replaces the emitter of optocoupler, and the collector of triode replaces the collector of optocoupler.
The first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 6th resistance R6 of the utility model can
Think that the resistance of 56K Ω, the 5th resistance R5, the 7th resistance R7 can be the resistance of 1K Ω.
As shown in Figure 1, the main circuit power supply of the utility model includes the 8th resistance R8, the 9th resistance R9, the 3rd MOSFET
Pipe Q3 and load, driving circuit output end and the 8th resistance R8, in order to realize the 3rd MOSFET pipe Q3 it is long when power down keep, need
Guarantee that the gate drive voltage of the 3rd MOSFET pipe Q3 remains unchanged during power down, and the 3rd MOSFET pipe Q3 driving voltage comes
Derived from driving circuit, driving circuit is battery powered, so only needing to guarantee the input control signal of driving circuit during power down
Do not change can be realized the 3rd MOSFET pipe Q3 it is long when power down keep function.
The utility model is to utilize the partial pressure of the 6th resistance R6 and 3rd resistor R3 from the core technology scheme of holding circuit
And the clamping action of Zener diode D1 obtains control signal, and it is indirect directly controlled by MCU control signal, while electricity
Input control signal is utilized to control the conducting of bleeder circuit P-channel MOSFET pipe Q2 in road, it is ensured that controls oneself of input signal
It maintains.In entire circuit, MCU control signal is to change control letter by force by the first optocoupler U1A of control, the second optocoupler U2A
Number input voltage breaks original balance with this, changes the state that input control signal maintains.
The working principle of the utility model is: when MCU control signal 1 provides high level, in the grid of N-channel MOS FET pipe Q1
Pole will have the driving voltage (3V~9V) of 1/2VCC, due to the work of Zener diode D1 (selection stable voltage is 5.1V)
With the driving voltage of the grid of N-channel MOS FET pipe Q1 can be clamped at 5.1V, the i.e. gate driving of N-channel MOS FET pipe Q1
Voltage range is 3V~5.1V, chooses N-channel MOS FET of the conduction threshold lower than 3V as Q1, that is, can guarantee N-channel MOS FET
Pipe Q1's is fully on, and is supplied to the grid 1/ of P-channel MOSFET pipe Q2 by the partial pressure of first resistor R1, second resistance R2
2VCC driving voltage (3V~9V), same P-channel MOSFET of the conduction threshold lower than 3V that choose can guarantee P-channel as Q2
MOSFET pipe Q2 conducting,
So at this moment the gate drive voltage of N-channel MOS FET pipe Q1 will be increased to by 1/2VCC 2/3VCC (4V~
12V), equally become (4V~5.1V) under Zener diode D1 clamping action, N-channel MOS FET pipe Q1 still can guarantee
Full conducting, if MCU controls signal 1 since power down lacks presentation high-impedance state, the grid electricity of N-channel MOS FET pipe Q1 at this time
Pressing the partial pressure of the 6th resistance R6 and 3rd resistor R3 that pass through still may remain in 1/2VCC (3V~5.1V), maintain driving electricity
The input voltage on road is high level.Similarly, when MCU control signal 2 gives high level, the gate driving of N-channel MOS FET pipe Q1
Voltage will become 0, and N-channel MOS FET pipe Q1 is disconnected, and the gate source voltage of P-channel MOSFET pipe Q2 also becomes 0, Q2 disconnection, if
MCU controls signal since power down is lost, then the gate drive voltage of N-channel MOS FET pipe Q1 can be due to P-channel at this time
Under conditions of MOSFET pipe Q2 is disconnected, close to 0V, N-channel MOS FET pipe Q1 is caused to keep off-state, maintains driving electricity
The input voltage on road is low level.
Claims (5)
1. a kind of input signal holding circuit, including N-channel MOS FET pipe, P-channel MOSFET pipe, first resistor, second resistance,
3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, Zener diode, the first optocoupler, the second optocoupler, the
One optocoupler, the second optocoupler control terminal respectively with control signal 2 and control signal 1 connect, it is characterised in that: the hair of the second optocoupler
Emitter grounding, emitter, the driving circuit of the first optocoupler input, one end of the 7th resistance is connect with the collector of the second optocoupler,
The cathode of Zener diode is connect with the collector of the second optocoupler, and the emitter of the anode of Zener diode and the second optocoupler connects
It connects, 3rd resistor is in parallel with Zener diode, and the other end of the 7th resistance is connect with the grid of N-channel MOS FET pipe, N-channel
The source electrode of MOSFET pipe is grounded, and drain series first resistor, the second resistance of N-channel MOS FET pipe connect to power supply, the 5th electricity
One end of resistance is connect with the tie point of first resistor, second resistance, the other end of the 5th resistance and the grid of P-channel MOSFET pipe
Connection, the drain electrode of P-channel MOSFET pipe are connect after the 6th resistance with the cathode of Zener diode, P-channel MOSFET pipe
Source electrode connects to power supply, and the 4th resistance both ends are connect with the collector of power supply and the first optocoupler respectively.
2. a kind of input signal holding circuit according to claim 1, it is characterised in that: N-channel MOS FET pipe replaces with
NPN triode, P-channel MOSFET pipe replace with PNP triode, and the base stage of triode replaces the grid of MOSFET pipe, triode
Collector replace the drain electrode of MOSFET pipe, the emitter of triode replaces the source electrode of MOSFET pipe.
3. a kind of input signal holding circuit according to claim 1, it is characterised in that: the first optocoupler and the second optocoupler replace
It is changed to NPN triode, the base stage of triode is connect with control signal, and the emitter of triode replaces the emitter of optocoupler, three poles
The collector of pipe replaces the collector of optocoupler.
4. a kind of input signal holding circuit according to claim 1, it is characterised in that: first resistor, second resistance,
Three resistance, the 4th resistance, the resistance that the 6th resistance is 56K Ω.
5. a kind of input signal holding circuit according to claim 1, it is characterised in that: the 5th resistance, the 7th resistance are
The resistance of 1K Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920539515.7U CN209627344U (en) | 2019-04-19 | 2019-04-19 | A kind of input signal holding circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920539515.7U CN209627344U (en) | 2019-04-19 | 2019-04-19 | A kind of input signal holding circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209627344U true CN209627344U (en) | 2019-11-12 |
Family
ID=68458708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920539515.7U Withdrawn - After Issue CN209627344U (en) | 2019-04-19 | 2019-04-19 | A kind of input signal holding circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN209627344U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109921772A (en) * | 2019-04-19 | 2019-06-21 | 骆驼集团武汉光谷研发中心有限公司 | A kind of input signal holding circuit |
-
2019
- 2019-04-19 CN CN201920539515.7U patent/CN209627344U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109921772A (en) * | 2019-04-19 | 2019-06-21 | 骆驼集团武汉光谷研发中心有限公司 | A kind of input signal holding circuit |
| CN109921772B (en) * | 2019-04-19 | 2023-12-15 | 骆驼集团武汉光谷研发中心有限公司 | Input signal holding circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20191112 Effective date of abandoning: 20231215 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20191112 Effective date of abandoning: 20231215 |