CN209608625U - A kind of crystal filter circuit with frequency compensation automatic regulation function - Google Patents
A kind of crystal filter circuit with frequency compensation automatic regulation function Download PDFInfo
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- CN209608625U CN209608625U CN201920582411.4U CN201920582411U CN209608625U CN 209608625 U CN209608625 U CN 209608625U CN 201920582411 U CN201920582411 U CN 201920582411U CN 209608625 U CN209608625 U CN 209608625U
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- crystal filter
- inductance
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- automatic regulation
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Abstract
The utility model discloses a kind of crystal filter circuits with frequency compensation automatic regulation function, belong to wireless transmit-receive technology field, including first crystal filter XF401, the second crystal filter XF402 and on-site programmable gate array FPGA, first crystal filter XF401 and the second crystal filter XF402 cascade；Resonance circuit is parallel between first crystal filter XF401 and the grade of the second crystal filter XF402, the resonant tank includes the second inductance L402 and the second varactor CVD402 in parallel；The output end of the on-site programmable gate array FPGA is connect by third latch, third digital analog converter D/A and third driving circuit with the cathode of the second varactor CVD402.Bias voltage changes its capacitance after being applied to varactor, and bias voltage is adjusted based on the corresponding signal that crystal filter inputs frequency sweep, it is achieved that frequency compensated automatic regulation function.
Description
Technical field
It is the utility model relates to wireless transmit-receive technology field, in particular to a kind of with frequency compensation automatic regulation function
Crystal filter circuit.
Background technique
It is logical to be widely used to super-heterodyne radio as intermediate frequency filtering device for crystal filter, also known as crystal resonator
Believe in equipment.Due to factors such as device consistency deficiency, aging and temperature changes, device parameters, which change, to can hardly be avoided, therefore
The matching of crystal filter and its front and back circuit and frequency compensation remain to effectively keep being a problem for a long time after equipment factory.
Notification number is that the Chinese utility model patent of CN201830216U discloses a kind of crystal filter circuit, by two-stage
Crystal filter cascades.Shunt-resonant circuit between two-stage is used for frequency characteristic compensation.The L-type filter at both ends can
Advantageously to carry out impedance matching adjusting.Frequency compensation can not be adjusted in above-mentioned crystal filter circuit, and it is steady to influence work
It is qualitative.
Utility model content
The utility model provides a kind of crystal filter circuit with frequency compensation automatic regulation function, its advantage is that
Frequency compensation automatic adjustment can be carried out, and degree of regulation is higher, protect and can demonstrate,prove the reliable long-term working of crystal filter.
The above-mentioned purpose of the utility model is achieved through the following technical solutions, and one kind having frequency compensation automatic adjustment
The crystal filter circuit of function, including first crystal filter XF401, the second crystal filter XF402 and field-programmable
Gate array FPGA, first crystal filter XF401 and the second crystal filter XF402 cascade, the field programmable gate array
The output end of FPGA is connect by the first digital analog converter D/A and the first driving circuit with first crystal filter XF401, and second
Crystal filter XF402 is connected by high-speed AD converter A/D with the input terminal of on-site programmable gate array FPGA；First is brilliant
Resonance circuit is parallel between fluid filter XF401 and the grade of the second crystal filter XF402, the resonant tank includes in parallel
Second inductance L402 and the second varactor CVD402；The input terminal of first crystal filter XF401 is in series with the first inductance
L401 and it is parallel with the first varactor CVD401, the output end of the second crystal filter XF402 is in series with third inductance
L403 and it is parallel with third varactor CVD403, the first varactor CVD401, the second varactor
The anode of CVD402 and third varactor CVD403 is grounded；The output end of the on-site programmable gate array FPGA passes through
Second latch, the second digital analog converter D/A and the second driving circuit are connect with the cathode of the first varactor CVD401, institute
The output end for stating on-site programmable gate array FPGA passes through third latch, third digital analog converter D/A and third driving circuit
It is connect with the cathode of the second varactor CVD402, the output end of the on-site programmable gate array FPGA is latched by the 4th
Device, the 4th digital analog converter D/A and the 4th driving circuit are connect with the cathode of third varactor CVD403.
The utility model is further arranged to, and the first inductance L401 and third inductance L403 are the electricity of same size
Sense.
The utility model is further arranged to, and is connected between second driving circuit and the first varactor CVD401
There is the 4th inductance L404, be in series with the 5th inductance L405 between the third driving circuit and the second varactor CVD402,
The 6th inductance L406 is in series between 4th driving circuit and third varactor CVD403.
The utility model is further arranged to, and the 4th inductance L404, the 5th inductance L405 and the 6th inductance L406 are
Same size inductance.
The utility model is further arranged to, and the first electricity is in series between first driving circuit and the first inductance L401
Hold C1, the second capacitor C2 is in series between the third inductance and high-speed AD converter A/D.
The utility model is further arranged to, and first capacitor C1 and the second capacitor C2 are the capacitor of same size.
The utility model is further arranged to, and two-stage crystal filter is identical.
The utility model is further arranged to, and is in series with first between first driving circuit and the first inductance L401 and is penetrated
Frequency switchs, and the second RF switch, first RF switch are in series between the third inductance and high-speed AD converter A/D
It is single-pole double throw RF switch with the second RF switch, the control signal end of first RF switch and the second RF switch
It is connect with on-site programmable gate array FPGA.
In conclusion the beneficial effects of the utility model have:
1. shunt-resonant circuit between two-stage is used for frequency characteristic compensation, the inductance at both ends can easily with front and back circuit
Impedance carry out matching adjusting, bias voltage information is stored in latch by on-site programmable gate array FPGA, through digital-to-analogue when needing
Converter D/A generates analog signal, then forms above-mentioned bias voltage through driving circuit, after bias voltage is applied to varactor
The capacitor for changing varactor is set, and bias voltage information of voltage is formulated by the output signal of crystal filter, therefore is realized
Frequency compensated automatic regulation function；
2. frequency compensation automatic regulation function and relevant other can be fast implemented based on on-site programmable gate array FPGA
Digital signal processing function, such as finite impulse response (FIR) (Finite Impulse Response, FIR) digital filtering；
3. if the aging of device and the variation (such as temperature) of environment cause device parameters to change, so that frequency compensation is lost
Effect, equipment can be adjusted by changing the bias voltage on the varactor in frequency compensated circuit, to improve crystal filter
The frequency characteristic of wave device；
4. bias voltage is determined by D/A circuit evolving, degree of regulation by D/A precision, at present due to high-precision D/A technology
Through maturation, it is achieved that the feasibility that high-precision is adjusted is guaranteed；
5. the second inductance is used to block the radio-frequency component in biasing voltage signal, the reliability of system is improved.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of embodiment one, in figure, L401, L402, L403, L404, L405, L406 be inductance and
L401 is identical with L403, and L404, L405, L406 are identical, and CVD401, CVD402 and CVD403 are identical varactor,
XF401, XF402 are identical crystal resonator；
Fig. 2 is the structure chart that first capacitor C1 and the second position capacitor C2 are embodied in embodiment two.
Specific embodiment
The specific embodiment that according to the present invention will be described in detail below with reference to the accompanying drawings.
Embodiment one: referring to Fig. 1, a kind of crystal filter circuit with frequency compensation automatic regulation function, including the
One crystal filter XF401, the second crystal filter XF402 and on-site programmable gate array FPGA, first crystal filter
XF401 and the second crystal filter XF402 cascade, two-stage crystal filter is identical, the output of on-site programmable gate array FPGA
End is connect by the first digital analog converter D/A and the first driving circuit with first crystal filter XF401, the second crystal filter
XF402 is connected by high-speed AD converter A/D with the input terminal of on-site programmable gate array FPGA.First crystal filter
Resonance circuit is parallel between XF401 and the grade of the second crystal filter XF402, the resonant tank includes the second inductance in parallel
The effect of L402 and the second varactor CVD402, resonant tank carry out frequency characteristic compensation to crystal filter.First
The input terminal of crystal filter XF401 is in series with the first inductance L401 and is parallel with the first varactor CVD401, and second is brilliant
The output end of fluid filter XF402 is in series with third inductance L403 and is parallel with third varactor CVD403, the first transfiguration
The anode of diode CVD401, the second varactor CVD402 and third varactor CVD403 are grounded, the first inductance
L401 and third inductance L403 is the inductance of same size.The output end of on-site programmable gate array FPGA is latched by second
Device, the second digital analog converter D/A and the second driving circuit are connect with the cathode of the first varactor CVD401, field-programmable
The output end of gate array FPGA passes through third latch, third digital analog converter D/A and third driving circuit and the second transfiguration two
The cathode of pole pipe CVD402 connects, and the output end of on-site programmable gate array FPGA passes through the 4th latch, the 4th digital-to-analogue conversion
Device D/A and the 4th driving circuit are connect with the cathode of third varactor CVD403.Second driving circuit and the first transfiguration two
It is in series with the 4th inductance L404 between pole pipe CVD401, is in series between third driving circuit and the second varactor CVD402
5th inductance L405 is in series with the 6th inductance L406 between the 4th driving circuit and third varactor CVD403.4th electricity
Feel L404, the 5th inductance L405 and the 6th inductance L406 are same size inductance, the 4th inductance L404, the 5th inductance L405 and the
The effect of six inductance L406 is isolation AC signal.
As shown in Figure 1, first crystal filter XF401 and the second crystal filter XF402 are used in exemplary circuit
10.7MHz crystal, the first inductance L401 and third inductance L403 select 6.8 μ H inductance, and the second inductance L402 selects 8.2 μ H electricity
Sense, the 4th inductance L404, the 5th inductance L405 and the 6th inductance L406 selection 10mH inductance, the first varactor CVD401,
Second varactor CVD402 and third varactor CVD403 selects the varactor of 1 ~ 10pF, can in actual circuit
According to circumstances carry out appropriate adjustment.
Regulating step is as follows: step 1: FPGA exports the swept-frequency signal of a constant amplitude, frequency coverage work by D/A
The centre frequency of work, in the range of the several times of crystal filter circuit target bandwidth；Step 2: FPGA acquires crystal by A/D and filters
The swept-frequency signal of wave device circuit output；Step 3: FPGA analyzes said two devices signal, obtains the frequency characteristic of crystal filter；The
4 steps: the information of the acquisition based on step 3, for wherein a certain varactor, FPGA output includes the number of above-mentioned bias voltage information
Character code is stored in latch, then generates analog signal through digital analog converter D/A, then form above-mentioned biased electrical through driving circuit
Pressure, applies to varactor, to adjust its capacitance, presses this execution to each varactor；5. executing step 3, obtain
The frequency characteristic of crystal filter is taken, if its still backlog demand, repeatedly 1-4 is walked, if it has met the requirements, all steps
Suddenly terminate.
Embodiment two: Fig. 1 and Fig. 2 is referred to, wherein based on the circuit in Fig. 1 and Fig. 1 is omitted in the circuit in Fig. 2
In the circuit that has shown.On the basis of example 1, it is in series between the first driving circuit and the first inductance L401
First capacitor C1 is in series with the second capacitor C2, first capacitor C1 and between the third inductance and high-speed AD converter A/D
Two capacitor C2 are the capacitor of same size, the effect stopping direct current of first capacitor C1 and the second capacitor C2.First driving circuit and
It is in series with the first RF switch between one inductance L401, second is in series between third inductance and high-speed AD converter A/D and is penetrated
Frequency switchs, and the first RF switch and the second RF switch are single-pole double throw RF switch, specifically opens up in optional Shenzhen
The Agilent 8765A single-pole double throw RF switch of overseas Electronics Co., Ltd.'s production or Chuan Feijie Science and Technology Ltd., Shenzhen
The control signal end of the SEM123T NARDA/ single-pole double throw RF switch of production, the first RF switch and the second RF switch with
On-site programmable gate array FPGA connection.First RF switch and the second RF switch synchronism switching, pass through the first RF switch
With the second RF switch by the intermediate-frequency channel of crystal filter access receiver, when needing to be implemented frequency compensation automatic regulation function
When, FPGA issues control signal " 0 " cutting crystal filter circuit and its front and back circuit in the connection of intermediate-frequency channel, mends to frequency
After repaying completion, FPGA issues control signal " 1 " and resets RF switch, makes receiver restore to work normally, simplifies adjusting
Process.
Above-described is only preferred embodiments of the present invention, it is noted that for the ordinary skill of this field
For personnel, without departing from the concept of the present invention, various modifications and improvements can be made, these all belong to
In the protection scope of the utility model.
Claims (8)
1. a kind of crystal filter circuit with frequency compensation automatic regulation function, which is characterized in that filtered including first crystal
Wave device XF401, the second crystal filter XF402 and on-site programmable gate array FPGA, first crystal filter XF401 and second
Crystal filter XF402 cascade, the output end of the on-site programmable gate array FPGA pass through the first digital analog converter D/A and the
One drive circuit is connect with first crystal filter XF401, and the second crystal filter XF402 passes through high-speed AD converter A/D
It is connected with the input terminal of on-site programmable gate array FPGA；First crystal filter XF401's and the second crystal filter XF402
Resonance circuit is parallel between grade, the resonance circuit includes the second inductance L402 and the second varactor CVD402 in parallel；
The input terminal of first crystal filter XF401 is in series with the first inductance L401 and is parallel with the first varactor CVD401, the
The output end of two crystal filter XF402 is in series with third inductance L403 and is parallel with third varactor CVD403, described
The anode of first varactor CVD401, the second varactor CVD402 and third varactor CVD403 are grounded；
The output end of the on-site programmable gate array FPGA passes through the second latch, the driving electricity of the second digital analog converter D/A and second
Road is connect with the cathode of the first varactor CVD401, and the output end of the on-site programmable gate array FPGA is locked by third
Storage, third digital analog converter D/A and third driving circuit are connect with the cathode of the second varactor CVD402, the scene
The output end of programmable gate array FPGA passes through the 4th latch, the 4th digital analog converter D/A and the 4th driving circuit and third
The cathode of varactor CVD403 connects.
2. the crystal filter circuit according to claim 1 with frequency compensation automatic regulation function, which is characterized in that
The first inductance L401 and third inductance L403 is the inductance of same size.
3. the crystal filter circuit according to claim 1 with frequency compensation automatic regulation function, which is characterized in that
The 4th inductance L404, the third driving circuit are in series between second driving circuit and the first varactor CVD401
The 5th inductance L405, the 4th driving circuit and third varactor are in series between the second varactor CVD402
The 6th inductance L406 is in series between CVD403.
4. the crystal filter circuit according to claim 3 with frequency compensation automatic regulation function, which is characterized in that
The 4th inductance L404, the 5th inductance L405 and the 6th inductance L406 are same size inductance.
5. the crystal filter circuit according to claim 1 with frequency compensation automatic regulation function, which is characterized in that
First capacitor C1, the third inductance and high speed analog-to-digital conversion are in series between first driving circuit and the first inductance L401
The second capacitor C2 is in series between device A/D.
6. the crystal filter circuit according to claim 5 with frequency compensation automatic regulation function, which is characterized in that
First capacitor C1 and the second capacitor C2 is the capacitor of same size.
7. the crystal filter circuit according to claim 1 with frequency compensation automatic regulation function, which is characterized in that
Two-stage crystal filter is identical.
8. the crystal filter circuit according to claim 1 with frequency compensation automatic regulation function, which is characterized in that
The first RF switch is in series between first driving circuit and the first inductance L401, the third inductance and high speed analog-digital conversion turn
The second RF switch is in series between parallel operation A/D, first RF switch and the second RF switch are single-pole double-throw radio frequency
The control signal end of switch, first RF switch and the second RF switch is connect with on-site programmable gate array FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920582411.4U CN209608625U (en) | 2019-04-26 | 2019-04-26 | A kind of crystal filter circuit with frequency compensation automatic regulation function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920582411.4U CN209608625U (en) | 2019-04-26 | 2019-04-26 | A kind of crystal filter circuit with frequency compensation automatic regulation function |
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| Publication Number | Publication Date |
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| CN209608625U true CN209608625U (en) | 2019-11-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201920582411.4U Active CN209608625U (en) | 2019-04-26 | 2019-04-26 | A kind of crystal filter circuit with frequency compensation automatic regulation function |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111934699A (en) * | 2020-07-30 | 2020-11-13 | 吉林省全星航空技术有限公司 | ADS-B data acquisition device and system |
| CN114499436A (en) * | 2021-02-05 | 2022-05-13 | 井芯微电子技术(天津)有限公司 | Passive crystal frequency trimming circuit |
-
2019
- 2019-04-26 CN CN201920582411.4U patent/CN209608625U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111934699A (en) * | 2020-07-30 | 2020-11-13 | 吉林省全星航空技术有限公司 | ADS-B data acquisition device and system |
| CN114499436A (en) * | 2021-02-05 | 2022-05-13 | 井芯微电子技术(天津)有限公司 | Passive crystal frequency trimming circuit |
| CN114499436B (en) * | 2021-02-05 | 2022-11-15 | 井芯微电子技术(天津)有限公司 | Passive crystal frequency trimming circuit |
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