CN209526699U - A kind of low-power consumption D master-slave flip-flop with reset terminal - Google Patents
A kind of low-power consumption D master-slave flip-flop with reset terminal Download PDFInfo
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- CN209526699U CN209526699U CN201920538482.4U CN201920538482U CN209526699U CN 209526699 U CN209526699 U CN 209526699U CN 201920538482 U CN201920538482 U CN 201920538482U CN 209526699 U CN209526699 U CN 209526699U
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Abstract
A kind of low-power consumption D master-slave flip-flop with reset terminal of the utility model is related to a kind of d type flip flop, in order to overcome the problems, such as that existing master-slave D flip-flop power consumption is larger, including d type flip flop circuit and double gating circuits；Double gating circuits include the first gating circuit and the second gating circuit；First gating circuit, for the level state according to clock signal clk, signal D, signal Q, signal DB and signal QB, output signal CKMB: signal CKMB logic non-signal is signal CKM；Second gating circuit, for the level state according to clock signal clk, signal D, signal Q, signal DB and signal QB, output signal CKSB: signal CKSB logic non-signal is signal CKS；Signal CKMB and signal CKM are loaded on the both ends of transmission gate in master flip-flop respectively, signal CKSB and signal CKS are loaded on to the both ends of transmission gate in slave flipflop respectively by double gating circuits, and then control the state of output signal Q.
Description
Technical field
The utility model relates to a kind of d type flip flops, and in particular to be triggered using the master-slave D that gating circuit is controlled
Device.
Background technique
D type flip flop is widely used in a variety of applications and studies because having many advantages, such as that structure is simple, perfect in shape and function.But due to
Clock signal is changing, and master-slave flip-flop will alternately work, to generate dynamic power consumption.Excessively high power consumption not only makes
It is dfficult to apply in portable device, and will cause chip overheating cause its performance decline, the lost of life, it is in addition excessive
Power consumption also requires circuit using expensive encapsulation and heat dissipation equipment, to guarantee the normal work of circuit.
Utility model content
The purpose of this utility model is to overcome the problems that existing master-slave D flip-flop power consumption is larger, provide a kind of band
The low-power consumption D master-slave flip-flop of reset terminal.
A kind of low-power consumption D master-slave flip-flop with reset terminal of the utility model, including d type flip flop circuit, the D triggering
Device circuit is used for input signal D, output signal Q, signal DB and signal QB；And signal D and signal DB logic NOT relationship each other；It is defeated
Signal Q and signal QB logic NOT relationship each other out；
D master-slave flip-flop further includes double gating circuits；
Double gating circuits include the first gating circuit and the second gating circuit；
First gating circuit, for the level according to clock signal clk, signal D, signal Q, signal DB and signal QB
State, output signal CKMB: signal CKMB logic non-signal are signal CKM；
Second gating circuit, for the level according to clock signal clk, signal D, signal Q, signal DB and signal QB
State, output signal CKSB: signal CKSB logic non-signal are signal CKS；
Signal CKMB and signal CKM are loaded on the both ends of transmission gate in master flip-flop, by signal by double gating circuits respectively
CKSB and signal CKS loads on the both ends of transmission gate in slave flipflop respectively, and then controls the state of output signal Q；
And clock signal clk, signal D, signal Q, signal CKMB and signal CKSB meet following relationship:
The beneficial effects of the utility model are: the utility model proposes a kind of based on double gated with reset terminal
D type flip flop power consumption can be significantly reduced in low-power consumption D master-slave flip-flop.Using being passed in two-door control circuit control d type flip flop circuit
Defeated door, so that the reset D master-slave flip-flop power consumption based on Clock Gating Technique of the utility model is only standard reset D master-slave flip-flop
About 50%, achieved the effect that low-power consumption.
Detailed description of the invention
Fig. 1 is a kind of circuit diagram of low-power consumption D master-slave flip-flop with reset terminal of the utility model；
Fig. 2 is the equivalent circuit diagram of Fig. 1；
Fig. 3 is a kind of analogous diagram of low-power consumption D master-slave flip-flop with reset terminal of the utility model.
Specific embodiment
Specific embodiment 1: a kind of low-power consumption D master-slave flip-flop with reset terminal of present embodiment, including D triggering
Device circuit 1, d type flip flop circuit 1 are used for input signal D, output signal Q, signal DB and signal QB；And signal D and signal DB are mutual
For logic NOT relationship；Output signal Q and signal QB logic NOT relationship each other；
D master-slave flip-flop further includes double gating circuits；
Double gating circuits include the first gating circuit 2-1 and the second gating circuit 2-2；
First gating circuit 2-1, for the level according to clock signal clk, signal D, signal Q, signal DB and signal QB
State, output signal CKMB: signal CKMB logic non-signal are signal CKM；
Second gating circuit 2-2, for the level according to clock signal clk, signal D, signal Q, signal DB and signal QB
State, output signal CKSB: signal CKSB logic non-signal are signal CKS；
Signal CKMB and signal CKM are loaded on the both ends of transmission gate in master flip-flop, by signal by double gating circuits respectively
CKSB and signal CKS loads on the both ends of transmission gate in slave flipflop respectively, and then controls the state of output signal Q；
And clock signal clk, signal D, signal Q, signal CKMB and signal CKSB meet following relationship:
Specifically, Clock Gating Technique is one kind of low power consumption design method conditional control technology.Its principle is in electricity
Road is in idle condition, i.e., the input of trigger and output phase etc. whens, by control transmission gate shutdown allow entire circuit no longer
Work.
D type flip flop circuit 1 in present embodiment is single edging trigger.Assuming that the period of clock signal is 3ms, input letter
Number period be 20ms, then in the time of 3 clock cycle, input signal will not all change, and export will not
It changes.But since clock signal is changing, master-slave flip-flop will alternately work, and generate dynamic power consumption.This
The principle of embodiment is one gating structure of addition in circuit so that clock signal changes in any case, input with it is defeated
It when equal out, does not all act on effectively, can solve since clock signal is changing, master-slave flip-flop alternately works
Lead to the problem of dynamic power consumption.
Specific embodiment 2: present embodiment is the further explanation of specific embodiment one, wherein
First gating circuit 2-1 includes the first POMS, the 2nd PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, first
NMOS, the 2nd NMOS, the 3rd NMOS, the 4th NMOS and the 5th NMOS；
The grid of first NMOS and CLK signal output end are electrically connected, the source electrode of the first NMOS simultaneously with the 2nd NMOS and
The drain electrode of 3rd NMOS is electrically connected, the drain electrode of the first NMOS while the source electrode with the first POMS, the 2nd PMOS and the 3rd PMOS
It is electrically connected and the drain electrode of the first NMOS is as CKMB signal output end；
The drain electrode electricity of the grid of 2nd NMOS and the electrical connection of DB signal output end, the source electrode of the 2nd NMOS and the 4th NMOS
Gas connection；Grid and Q signal the output end electrical connection of 4th NMOS, the source electrode of the 4th NMOS are grounded；
The drain electrode electricity of the grid of 3rd NMOS and the electrical connection of D signal output end, the source electrode of the 3rd NMOS and the 5th NMOS
Gas connection；Grid and QB the signal output end electrical connection of 5th NMOS, the source electrode of the 5th NMOS are grounded；
The electrical connection of grid and CLK signal output end, the drain electrode of the first POMS of first POMS meets VDD；
Grid and Q signal the output end electrical connection of 2nd PMOS, the drain electrode of the 2nd PMOS and the source electrode electricity of the 4th PMOS
Gas connection；The electrical connection of grid and D signal output end, the drain electrode of the 4th PMOS of 4th PMOS meets VDD；
Grid and QB the signal output end electrical connection of 3rd PMOS, the drain electrode of the 3rd PMOS and the source electrode electricity of the 5th PMOS
Gas connection；The electrical connection of grid and DB signal output end, the drain electrode of the 5th PMOS of 5th PMOS meets VDD
Specific embodiment 3: present embodiment is the further explanation of specific embodiment two, wherein
Second gating circuit 2-2 includes the 6th PMOS, the 7th PMOS, the 8th PMOS, the 9th PMOS, the tenth PMOS, the 6th
NMOS, the 7th NMOS, the 8th NMOS, the 9th NMOS and the tenth NMOS；
The grid of 6th PMOS and CLK signal output end are electrically connected, the drain electrode of the 6th PMOS simultaneously with the 7th PMOS and
The source electrode of 8th PMOS is electrically connected, the drain electrode with the 6th NMOS, the 7th NMOS and the 8th NMOS simultaneously of the source electrode of the 6th PMOS
The source electrode of electrical connection and the 6th PMOS are as CKSB signal output end；
Grid and D the signal output end electrical connection of 7th PMOS, the drain electrode of the 7th PMOS and the source electrode electricity of the 9th PMOS
Gas connection；The electrical connection of grid and QB signal output end, the drain electrode of the 9th PMOS of 9th PMOS meets VDD；
Grid and DB signal the output end electrical connection of 8th PMOS, the drain electrode of the 8th PMOS and the source electrode electricity of the tenth PMOS
Gas connection；The electrical connection of grid and Q signal output end, the drain electrode of the tenth PMOS of tenth PMOS meets VDD；
Grid and CLK signal the output end electrical connection of 6th NMOS, the source electrode of the 6th NMOS are grounded；
The drain electrode electricity of the grid of 7th NMOS and the electrical connection of QB signal output end, the source electrode of the 7th NMOS and the 9th NMOS
Gas connection；Grid and QB the signal output end electrical connection of 9th NMOS, the source electrode of the 9th NMOS are grounded；
The drain electrode electricity of the grid of 8th NMOS and the electrical connection of D signal output end, the source electrode of the 8th NMOS and the tenth NMOS
Gas connection；Grid and Q signal the output end electrical connection of tenth NMOS, the source electrode of the tenth NMOS are grounded.
Specific embodiment 4: present embodiment is the further explanation of specific embodiment one, two or three, wherein D touching
The master flip-flop for sending out device circuit 1 includes phase inverter INV3, phase inverter INV4, transmission gate TG1, transmission gate TG2 and NAND gate
NAND1；
The input terminal of phase inverter INV3 and the electrical connection of Q signal output end, output end respectively as DB signal output end with
And it is electrically connected with one of input/output terminal of transmission gate TG1, another input/output terminal and phase inverter of transmission gate TG1
The input terminal of INV4 is electrically connected；Transmission gate TG1'sEnd with CKMB signal output end be electrically connected, the C-terminal of transmission gate TG1 with
The electrical connection of CKM signal output end；
One of input terminal of NAND gate NAND1 with reset rb signal output end electrical connection, NAND gate NAND1 it is another
The output end of one input terminal and phase inverter INV4 are electrically connected, and wherein the one of the output end of NAND gate NAND1 and transmission gate TG2
A input/output terminal electrical connection；Another input/output terminal of transmission gate TG2 and the input terminal of phase inverter INV4 are electrically connected；
Transmission gate TG2'sEnd is electrically connected with CKM signal output end, and C-terminal and the CKMB signal output end of transmission gate TG2 electrically connects
It connects；
The slave flipflop of d type flip flop circuit 1 include transmission gate TG3, transmission gate TG4, NAND gate NAND2, phase inverter INV5,
Phase inverter INV6 and phase inverter INV7；
The output end of one of input/output terminal of transmission gate TG3 and phase inverter INV4 electrical connection, transmission gate TG3
One of input terminal of another input/output terminal and NAND gate NAND2 are electrically connected；Transmission gate TG3'sBelieve with CKSB at end
The electrical connection of number output end, the C-terminal and CKS signal output end of transmission gate TG3 are electrically connected；
Another input terminal of NAND gate NAND2 and the electrical connection of electrical connection rb signal output end, NAND gate NAND2
The input terminal of output end and phase inverter INV5 are electrically connected, and the output end of phase inverter INV5 is as Q signal output end；
The input terminal of one of input/output terminal of transmission gate TG4 and phase inverter INV7 electrical connection, transmission gate TG4
One of input terminal of another input/output terminal and NAND gate NAND2 are electrically connected；Transmission gate TG4'sBelieve with CKS at end
The electrical connection of number output end, the C-terminal and CKSB signal output end of transmission gate TG4 are electrically connected；
The output end of phase inverter INV7 is as QB signal output end；The input terminal of phase inverter INV6 is defeated with phase inverter INV5's
The input terminal for entering end electrical connection, the output end of phase inverter INV6 and phase inverter INV7 is electrically connected.
Specifically, as shown in Figure 1, a kind of circuit diagram of the low-power consumption D master-slave flip-flop with reset terminal is that two-door control is added
The master-slave D flip-flop circuit with reset function of circuit structure, when the rising edge of clock signal clk arrives, trigger touching
Hair.
This flip-flop circuit is made of 7 phase inverters, 4 transmission gates, 2 NAND gates, 10 PMOS and 10 NMOS.And
Fig. 2 is the equivalent circuit diagram of Fig. 1.
Specifically, the first gating circuit 2-1 in Fig. 2 in double gating circuits 1 controls the main touching in d type flip flop circuit 1
Device is sent out, thus double gating circuits 1 generate a signal CKMB, then generate signal CKM, two signals via a phase inverter INV1
It is respectively connected to the both ends of transmission gate in master flip-flop；Second gating circuit 2-2 controls the slave flipflop in d type flip flop circuit 1
Principle is also identical with this.
Specific embodiment 5: present embodiment is the further explanation of specific embodiment four, wherein further include reverse phase
Device INV1 and phase inverter INV2；
The input terminal and CKMB signal output end of phase inverter INV1 is electrically connected, the output end of phase inverter INV1 is as CKM
Signal output end；
The input terminal and CKSB signal output end of phase inverter INV2 is electrically connected, the output end of phase inverter INV2 is as CKS
Signal output end.
Entire circuit analysis can be obtained, if D=Q, i.e., when the input of d type flip flop circuit 1 is equal to output, if CLK=
0, then the pulldown network conducting of upper pull-up network conducting CKMB=1, CKM=0, the second the gating circuit 2-2 of the first gating circuit 2-1
CKSB=0, CKS=1, transmission gate TG1 is turned off in d type flip flop circuit 1 at this time, transmission gate TG2 conducting；Transmission gate TG3 conducting, passes
Defeated door TG4 shutdown.
If CLK=1, then CKMB=1, CKM=0, the second gating circuit is connected in the upper pull-up network of the first gating circuit 2-1
CKSB=0, CKS=1, transmission gate TG1 shutdown, transmission gate TG2 conducting, transmission gate TG3 conducting, biography is connected in the pulldown network of 2-2
Defeated door TG4 shutdown.It therefore deduces that, when input remains equal with output signal in certain time, then regardless of clock
How signal CLK changes, and the transmission gate TG1 of master flip-flop is turned off always, and d type flip flop circuit 1 does not work.
If D ≠ Q, i.e., when the input of d type flip flop circuit 1 is not equal to output, if CLK=0, then the first gating circuit 2-
CKSB=1, CKS=0 is connected in the upper pull-up network of 1 upper pull-up network conducting CKMB=1, CKM=0, the second gating circuit 2-2, passes
Defeated door TG1 shutdown, input data can not be transmitted by transmission gate.
If CLK=1, then CKMB=0, CKM=1, the second gating circuit is connected in the pulldown network of the first gating circuit 2-1
The pulldown network of 2-2 is connected CKSB=0, CKS=1, transmission gate TG1 conducting, d type flip flop circuit 1 start master flip-flop and from
Signal is acquired between trigger, but be off due to the transmission gate TG3 at this moment, output signal can only be maintained at main touching
The signal acquisition point between device and slave flipflop is sent out, is exported unchanged.Until the jump of next clock signal clk, i.e. CLK=0
When, transmission gate TG3 conducting, the data for being stored in 1 signal acquisition point of d type flip flop circuit can just be transferred to output end.
It is illustrated in figure 3 the simulation result that gated clock resets master-slave D flip-flop.The period of clock CLK is 3s, input
The period of signal D is 20s, and the period of reset signal rb is 72s.
At the t1 moment, rb=1, D=Q, no matter clock signal clk is equal to 0 or 1 at this time, and CKMB is equal to 1, CKSB etc.
In 0.T1 is to t2 clock, D ≠ Q, CLK=0, corresponding CKMB=1, CKSB=1.T2 moment, D ≠ Q, due to clock signal clk
The arrival of rising edge, so that output signal Q=D, CKMB=1, CKSB=0.T3 is to the t4 moment, also because of D ≠ Q, CLK by
When high level 1 jumps to low level 0, CLK=1, CKMB=0, CKSB=0, when CLK=0, CKMB=1, CKSB=1.When t4
It carves, D ≠ Q, CLK rising edge arrives, output signal Q=D.T5 moment, rb play a leading role, rb=0, export Q=0, and not
It is influenced by signal D and CLK.
Output signal QB is always anti-(the two is logic NOT relationship) of signal Q, and CKM is anti-equal to CKMB's, and CKS is equal to
CKSB's is anti-, and simulation result is corresponding with circuit theory, so, function is correct.
From simulation waveform as can be seen that the time of D=Q accounts for about 90%, D ≠ Q time and only accounts for about in input waveform
10%, then based on Clock Gating Technique reset D master-slave flip-flop switch activity factor-alpha=8*0.9+32*0.1=10.4,
And under the conditions of identical input signal, switch activity α=20*0.9+20*0.1=20 of common reset D master-slave flip-flop, by
This as it can be seen that the reset D master-slave flip-flop power consumption based on Clock Gating Technique is only about the 50% of standard reset D master-slave flip-flop,
The design requirement of low-power consumption is reached.
Claims (5)
1. a kind of low-power consumption D master-slave flip-flop with reset terminal, including d type flip flop circuit (1), the d type flip flop circuit (1) is used
In input signal D, output signal Q, signal DB and signal QB；And signal D and signal DB logic NOT relationship each other；Output signal Q
With signal QB logic NOT relationship each other；
It is characterized in that, D master-slave flip-flop further includes double gating circuits；
Double gating circuits include the first gating circuit (2-1) and the second gating circuit (2-2)；
First gating circuit (2-1), for the electricity according to clock signal clk, signal D, signal Q, signal DB and signal QB
Level state, output signal CKMB: signal CKMB logic non-signal are signal CKM；
Second gating circuit (2-2), for the electricity according to clock signal clk, signal D, signal Q, signal DB and signal QB
Level state, output signal CKSB: signal CKSB logic non-signal are signal CKS；
Signal CKMB and signal CKM are loaded on transmission gate in the master flip-flop of d type flip flop circuit (1) by double gating circuits respectively
Both ends, the both ends that signal CKSB and signal CKS are loaded on to transmission gate in the slave flipflop of d type flip flop circuit (1) respectively, in turn
Control the state of output signal Q；
And clock signal clk, signal D, signal Q, signal CKMB and signal CKSB meet following relationship:
2. a kind of low-power consumption D master-slave flip-flop with reset terminal according to claim 1, which is characterized in that
First gating circuit (2-1) includes the first POMS, the 2nd PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, first
NMOS, the 2nd NMOS, the 3rd NMOS, the 4th NMOS and the 5th NMOS；
The grid of first NMOS and CLK signal output end are electrically connected, the source electrode of the first NMOS simultaneously with the 2nd NMOS and third
The drain electrode of NMOS is electrically connected, and the drain electrode of the first NMOS is electrical with the source electrode of the first POMS, the 2nd PMOS and the 3rd PMOS simultaneously
It connects and the drain electrode of the first NMOS is as CKMB signal output end；
The grid of 2nd NMOS is electrically connected with DB signal output end, the drain electrode of the source electrode and the 4th NMOS of the 2nd NMOS electrically connects
It connects；Grid and Q signal the output end electrical connection of 4th NMOS, the source electrode of the 4th NMOS are grounded；
The grid of 3rd NMOS is electrically connected with D signal output end, the drain electrode of the source electrode and the 5th NMOS of the 3rd NMOS electrically connects
It connects；Grid and QB the signal output end electrical connection of 5th NMOS, the source electrode of the 5th NMOS are grounded；
The electrical connection of grid and CLK signal output end, the drain electrode of the first POMS of first POMS meets VDD；
The grid of 2nd PMOS and the source electrode of the electrical connection of Q signal output end, the drain electrode of the 2nd PMOS and the 4th PMOS electrically connect
It connects；The electrical connection of grid and D signal output end, the drain electrode of the 4th PMOS of 4th PMOS meets VDD；
The grid of 3rd PMOS and the source electrode of the electrical connection of QB signal output end, the drain electrode of the 3rd PMOS and the 5th PMOS electrically connect
It connects；The electrical connection of grid and DB signal output end, the drain electrode of the 5th PMOS of 5th PMOS meets VDD。
3. a kind of low-power consumption D master-slave flip-flop with reset terminal according to claim 2, which is characterized in that
Second gating circuit (2-2) includes the 6th PMOS, the 7th PMOS, the 8th PMOS, the 9th PMOS, the tenth PMOS, the 6th
NMOS, the 7th NMOS, the 8th NMOS, the 9th NMOS and the tenth NMOS；
The grid of 6th PMOS and CLK signal output end are electrically connected, the drain electrode of the 6th PMOS simultaneously with the 7th PMOS and the 8th
The source electrode of PMOS is electrically connected, and the source electrode of the 6th PMOS is electrical with the drain electrode of the 6th NMOS, the 7th NMOS and the 8th NMOS simultaneously
The source electrode of connection and the 6th PMOS are as CKSB signal output end；
The grid of 7th PMOS and the source electrode of the electrical connection of D signal output end, the drain electrode of the 7th PMOS and the 9th PMOS electrically connect
It connects；The electrical connection of grid and QB signal output end, the drain electrode of the 9th PMOS of 9th PMOS meets VDD；
The grid of 8th PMOS and the source electrode of the electrical connection of DB signal output end, the drain electrode of the 8th PMOS and the tenth PMOS electrically connect
It connects；The electrical connection of grid and Q signal output end, the drain electrode of the tenth PMOS of tenth PMOS meets VDD；
Grid and CLK signal the output end electrical connection of 6th NMOS, the source electrode of the 6th NMOS are grounded；
The grid of 7th NMOS is electrically connected with QB signal output end, the drain electrode of the source electrode and the 9th NMOS of the 7th NMOS electrically connects
It connects；Grid and QB the signal output end electrical connection of 9th NMOS, the source electrode of the 9th NMOS are grounded；
The grid of 8th NMOS is electrically connected with D signal output end, the drain electrode of the source electrode and the tenth NMOS of the 8th NMOS electrically connects
It connects；Grid and Q signal the output end electrical connection of tenth NMOS, the source electrode of the tenth NMOS are grounded.
4. a kind of low-power consumption D master-slave flip-flop with reset terminal according to claim 1,2 or 3, which is characterized in that
The master flip-flop of the d type flip flop circuit (1) includes phase inverter INV3, phase inverter INV4, transmission gate TG1, transmission gate TG2
With NAND gate NAND1；
The input terminal of phase inverter INV3 and the electrical connection of Q signal output end, output end respectively as DB signal output end and with
One of input/output terminal of transmission gate TG1 is electrically connected, another input/output terminal and phase inverter INV4 of transmission gate TG1
Input terminal electrical connection；The C-terminal and CKMB signal output end of transmission gate TG1 is electrically connected, and the C-terminal and CKM of transmission gate TG1 is believed
The electrical connection of number output end；
One of input terminal of NAND gate NAND1 and reset the electrical connection of rb signal output end, NAND gate NAND1 another
The output end of input terminal and phase inverter INV4 are electrically connected, and one of them of the output end of NAND gate NAND1 and transmission gate TG2 are defeated
Enter output end electrical connection；Another input/output terminal of transmission gate TG2 and the input terminal of phase inverter INV4 are electrically connected；Transmission
The C-terminal and CKM signal output end of door TG2 is electrically connected, and the C-terminal and CKMB signal output end of transmission gate TG2 is electrically connected；
The slave flipflop of the d type flip flop circuit (1) includes transmission gate TG3, transmission gate TG4, NAND gate NAND2, phase inverter
INV5, phase inverter INV6 and phase inverter INV7；
The output end electrical connection of one of input/output terminal of transmission gate TG3 and phase inverter INV4, transmission gate TG3 it is another
One of input terminal of a input/output terminal and NAND gate NAND2 are electrically connected；The C-terminal of transmission gate TG3 and CKSB signal are defeated
Outlet electrical connection, the C-terminal and CKS signal output end of transmission gate TG3 are electrically connected；
Another input terminal of NAND gate NAND2 and the electrical connection of electrical connection rb signal output end, the output of NAND gate NAND2
End and the input terminal of phase inverter INV5 are electrically connected, and the output end of phase inverter INV5 is as Q signal output end；
The input terminal electrical connection of one of input/output terminal of transmission gate TG4 and phase inverter INV7, transmission gate TG4 it is another
One of input terminal of a input/output terminal and NAND gate NAND2 are electrically connected；The C-terminal and CKS signal of transmission gate TG4 exports
End electrical connection, the C-terminal and CKSB signal output end of transmission gate TG4 are electrically connected；
The output end of phase inverter INV7 is as QB signal output end；The input terminal of phase inverter INV6 and the input terminal of phase inverter INV5
The input terminal of electrical connection, the output end of phase inverter INV6 and phase inverter INV7 is electrically connected.
5. a kind of low-power consumption D master-slave flip-flop with reset terminal according to claim 4, which is characterized in that further include anti-
Phase device INV1 and phase inverter INV2；
The input terminal and CKMB signal output end of the phase inverter INV1 is electrically connected, the output end of phase inverter INV1 is as CKM
Signal output end；
The input terminal and CKSB signal output end of the phase inverter INV2 is electrically connected, the output end of phase inverter INV2 is as CKS
Signal output end.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920538482.4U CN209526699U (en) | 2019-04-19 | 2019-04-19 | A kind of low-power consumption D master-slave flip-flop with reset terminal |
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| CN201920538482.4U CN209526699U (en) | 2019-04-19 | 2019-04-19 | A kind of low-power consumption D master-slave flip-flop with reset terminal |
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Granted publication date: 20191022 Termination date: 20200419 |