CN209526699U - A low-power master-slave D flip-flop with reset terminal - Google Patents

Abstract

A low-power master-slave D flip-flop with a reset terminal of the utility model relates to a D flip-flop, the purpose is to overcome the problem of large power consumption of the existing master-slave D flip-flop, including a D flip-flop circuit and a dual Gate control circuit; the double gate control circuit includes a first gate control circuit and a second gate control circuit; the first gate control circuit is used for clock signal CLK, signal D, signal Q, signal DB and signal QB Level state, output signal CKMB: the logical negation signal of signal CKMB is signal CKM; the second gating circuit is used to output Signal CKSB: The logical negation signal of signal CKSB is signal CKS; the double-gated circuit loads signal CKMB and signal CKM on both ends of the transmission gate in the master flip-flop, respectively loads signal CKSB and signal CKS on the slave flip-flop for transmission The two ends of the gate, and then control the state of the output signal Q.

Description

A low-power master-slave D flip-flop with reset terminal

technical field

The utility model relates to a D flip-flop, in particular to a master-slave D flip-flop controlled by a gate control circuit.

Background technique

D flip-flop has been widely used and researched because of its simple structure and perfect function. However, since the clock signal is changing, the master-slave flip-flops will work alternately, resulting in dynamic power consumption. Excessive power consumption not only makes it difficult to apply to portable devices, but also causes overheating of the chip, resulting in reduced performance and shortened life. In addition, excessive power consumption also requires the circuit to use expensive packaging and heat dissipation equipment to ensure the circuit. normal work.

Utility model content

The purpose of the utility model is to provide a low-power master-slave D flip-flop with a reset terminal in order to overcome the problem of large power consumption of the existing master-slave D flip-flop.

A low-power master-slave D flip-flop with a reset terminal of the utility model includes a D flip-flop circuit, the D flip-flop circuit is used for input signal D, output signal Q, signal DB and signal QB; and signal D and Signal DB is mutually logically negated; output signal Q and signal QB are mutually logically negated;

The master-slave D flip-flop also includes a double gating circuit;

The double gating circuit includes a first gating circuit and a second gating circuit;

The first gating circuit is configured to output the signal CKMB according to the level states of the clock signal CLK, the signal D, the signal Q, the signal DB, and the signal QB: the logic negation signal of the signal CKMB is the signal CKM;

The second gating circuit is configured to output the signal CKSB according to the level states of the clock signal CLK, the signal D, the signal Q, the signal DB, and the signal QB: the logic negation signal of the signal CKSB is the signal CKS;

The double gating circuit loads the signal CKMB and the signal CKM on both ends of the transmission gate in the master flip-flop, respectively loads the signal CKSB and the signal CKS on both ends of the transmission gate in the slave flip-flop, and then controls the state of the output signal Q;

And the clock signal CLK, signal D, signal Q, signal CKMB and signal CKSB satisfy the following relationship:

The beneficial effects of the utility model are: the utility model proposes a low-power master-slave D flip-flop with a reset terminal based on double-gate technology, which can significantly reduce the power consumption of the D flip-flop. The transmission gate in the D flip-flop circuit is controlled by the double gating circuit, so that the power consumption of the reset master-slave D flip-flop based on the gating clock technology is only about 50% of that of the ordinary reset master-slave D flip-flop, achieving low effect on power consumption.

Description of drawings

Fig. 1 is the circuit diagram of a kind of low power consumption master-slave D flip-flop with reset terminal of the present utility model;

Fig. 2 is the equivalent circuit diagram of Fig. 1;

FIG. 3 is a simulation diagram of a low-power master-slave D flip-flop with a reset terminal of the present invention.

Detailed ways

Embodiment 1: A low-power master-slave D flip-flop with a reset terminal in this embodiment includes a D flip-flop circuit 1, and the D flip-flop circuit 1 is used for input signal D, output signal Q, signal DB and signal QB ; And the signal D and the signal DB are mutually logical non-relationships; the output signal Q and the signal QB are mutually logical non-relationships;

The master-slave D flip-flop also includes a double gating circuit;

The double gating circuit includes a first gating circuit 2-1 and a second gating circuit 2-2;

The first gating circuit 2-1 is configured to output the signal CKMB according to the level states of the clock signal CLK, the signal D, the signal Q, the signal DB and the signal QB: the logic negation signal of the signal CKMB is the signal CKM;

The second gate control circuit 2-2 is used to output the signal CKSB according to the level states of the clock signal CLK, the signal D, the signal Q, the signal DB and the signal QB: the logic negation signal of the signal CKSB is the signal CKS;

The double gating circuit loads the signal CKMB and the signal CKM on both ends of the transmission gate in the master flip-flop, respectively loads the signal CKSB and the signal CKS on both ends of the transmission gate in the slave flip-flop, and then controls the state of the output signal Q;

And the clock signal CLK, signal D, signal Q, signal CKMB and signal CKSB satisfy the following relationship:

Specifically, the clock gating technology is a kind of conditional control technology in the low power consumption design method. The principle is that when the circuit is in an idle state, that is, when the input and output of the flip-flop are equal, the entire circuit will no longer work by controlling the shutdown of the transmission gate.

The D flip-flop circuit 1 in this embodiment is triggered by a single edge. Assuming that the cycle of the clock signal is 3 ms and the cycle of the input signal is 20 ms, the input signal will not change and the output will not change during the 3 clock cycles. However, since the clock signal is changing, the master-slave flip-flops will work alternately, resulting in dynamic power consumption. The principle of this embodiment is to add a gating structure in the circuit, so that no matter how the clock signal changes, when the input and output are equal, there is no effective effect, which can solve the problem that the master-slave flip-flops alternately perform due to the clock signal changing. The problem of working creates dynamic power consumption.

Embodiment 2: This embodiment is a further description of Embodiment 1, wherein,

The first gating circuit 2-1 includes a first POMS, a second PMOS, a third PMOS, a fourth PMOS, a fifth PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS and a fifth NMOS;

The gate of the first NMOS is electrically connected to the CLK signal output terminal, the source of the first NMOS is electrically connected to the drains of the second NMOS and the third NMOS at the same time, and the drain of the first NMOS is simultaneously connected to the first POMS and the second PMOS electrically connected to the source of the third PMOS, and the drain of the first NMOS serves as the CKMB signal output terminal;

The gate of the second NMOS is electrically connected to the DB signal output end, the source of the second NMOS is electrically connected to the drain of the fourth NMOS; the gate of the fourth NMOS is electrically connected to the Q signal output end, and the source of the fourth NMOS grounding;

The gate of the third NMOS is electrically connected to the D signal output terminal, the source of the third NMOS is electrically connected to the drain of the fifth NMOS; the gate of the fifth NMOS is electrically connected to the QB signal output terminal, and the source of the fifth NMOS grounding;

The gate of the first POMS is electrically connected to the CLK signal output terminal, and the drain of the first POMS is connected to V _DD ;

The gate of the second PMOS is electrically connected to the Q signal output end, the drain of the second PMOS is electrically connected to the source of the fourth PMOS; the gate of the fourth PMOS is electrically connected to the D signal output end, and the drain of the fourth PMOS connected to V _DD ;

The gate of the third PMOS is electrically connected to the QB signal output terminal, the drain of the third PMOS is electrically connected to the source of the fifth PMOS; the gate of the fifth PMOS is electrically connected to the DB signal output terminal, and the drain of the fifth PMOS connected to V _DD

Embodiment 3: This embodiment is a further description of Embodiment 2, wherein,

The second gating circuit 2-2 includes a sixth PMOS, a seventh PMOS, an eighth PMOS, a ninth PMOS, a tenth PMOS, a sixth NMOS, a seventh NMOS, an eighth NMOS, a ninth NMOS, and a tenth NMOS;

The gate of the sixth PMOS is electrically connected to the CLK signal output terminal, the drain of the sixth PMOS is electrically connected to the sources of the seventh PMOS and the eighth PMOS, and the source of the sixth PMOS is simultaneously connected to the sixth NMOS and the seventh NMOS electrically connected to the drain of the eighth NMOS, and the source of the sixth PMOS serves as the CKSB signal output terminal;

The gate of the seventh PMOS is electrically connected to the D signal output end, the drain of the seventh PMOS is electrically connected to the source of the ninth PMOS; the gate of the ninth PMOS is electrically connected to the QB signal output end, and the drain of the ninth PMOS connected to V _DD ;

The gate of the eighth PMOS is electrically connected to the DB signal output end, the drain of the eighth PMOS is electrically connected to the source of the tenth PMOS; the gate of the tenth PMOS is electrically connected to the Q signal output end, and the drain of the tenth PMOS connected to V _DD ;

The gate of the sixth NMOS is electrically connected to the CLK signal output terminal, and the source of the sixth NMOS is grounded;

The gate of the seventh NMOS is electrically connected to the QB signal output terminal, the source of the seventh NMOS is electrically connected to the drain of the ninth NMOS; the gate of the ninth NMOS is electrically connected to the QB signal output terminal, and the source of the ninth NMOS grounding;

The gate of the eighth NMOS is electrically connected to the D signal output terminal, the source of the eighth NMOS is electrically connected to the drain of the tenth NMOS; the gate of the tenth NMOS is electrically connected to the Q signal output terminal, and the source of the tenth NMOS grounded.

Embodiment 4: This embodiment is a further description of Embodiment 1, 2 or 3, wherein the main flip-flop of the D flip-flop circuit 1 includes an inverter INV3, an inverter INV4, a transmission gate TG1, and a transmission gate TG2 And NAND gate NAND1;

The input terminal of the inverter INV3 is electrically connected to the Q signal output terminal, and the output terminal is respectively used as the DB signal output terminal and electrically connected to one of the input and output terminals of the transmission gate TG1, and the other input and output terminal of the transmission gate TG1 is connected to the inverter The input terminal of INV4 is electrically connected; the transmission gate TG1's terminal is electrically connected to the CKMB signal output terminal, and the C terminal of the transmission gate TG1 is electrically connected to the CKM signal output terminal;

One of the input terminals of the NAND gate NAND1 is electrically connected to the output terminal of the reset rb signal, the other input terminal of the NAND gate NAND1 is electrically connected to the output terminal of the inverter INV4, and the output terminal of the NAND gate NAND1 is electrically connected to the output terminal of the transmission gate TG2 One of the input and output terminals is electrically connected; the other input and output terminal of the transmission gate TG2 is electrically connected to the input terminal of the inverter INV4; the transmission gate TG2 terminal is electrically connected to the CKM signal output terminal, and the C terminal of the transmission gate TG2 is electrically connected to the CKMB signal output terminal;

The slave flip-flop of the D flip-flop circuit 1 includes a transmission gate TG3, a transmission gate TG4, a NAND gate NAND2, an inverter INV5, an inverter INV6 and an inverter INV7;

One of the input and output terminals of the transmission gate TG3 is electrically connected to the output terminal of the inverter INV4, and the other input and output terminal of the transmission gate TG3 is electrically connected to one of the input terminals of the NAND gate NAND2; the transmission gate TG3 terminal is electrically connected to the CKSB signal output terminal, and the C terminal of the transmission gate TG3 is electrically connected to the CKS signal output terminal;

The other input end of the NAND gate NAND2 is electrically connected to the output end of the rb signal, the output end of the NAND gate NAND2 is electrically connected to the input end of the inverter INV5, and the output end of the inverter INV5 is used as the Q signal output end;

One of the input and output terminals of the transmission gate TG4 is electrically connected to the input terminal of the inverter INV7, and the other input and output terminal of the transmission gate TG4 is electrically connected to one of the input terminals of the NAND gate NAND2; terminal is electrically connected to the CKS signal output terminal, and the C terminal of the transmission gate TG4 is electrically connected to the CKSB signal output terminal;

The output terminal of the inverter INV7 is used as the output terminal of the QB signal; the input terminal of the inverter INV6 is electrically connected to the input terminal of the inverter INV5, and the output terminal of the inverter INV6 is electrically connected to the input terminal of the inverter INV7.

Specifically, as shown in Figure 1, a circuit diagram of a low-power master-slave D flip-flop with a reset terminal is a master-slave D flip-flop circuit with a reset function added to a double-gated circuit structure. When the clock signal CLK rises When the edge comes, the flip-flop fires.

This flip-flop circuit consists of 7 inverters, 4 transmission gates, 2 NAND gates, 10 PMOS and 10 NMOS. Fig. 2 is an equivalent circuit diagram of Fig. 1 .

Specifically, the first gate control circuit 2-1 in the double gate control circuit 1 in FIG. The phaser INV1 generates the signal CKM, and the two signals are respectively connected to the two ends of the transmission gate in the master flip-flop; the principle of the second gate control circuit 2-2 controlling the slave flip-flop in the D flip-flop circuit 1 is also the same.

Embodiment 5: This embodiment is a further description of Embodiment 4, which also includes an inverter INV1 and an inverter INV2;

The input terminal of the inverter INV1 is electrically connected to the output terminal of the CKMB signal, and the output terminal of the inverter INV1 is used as the output terminal of the CKM signal;

The input terminal of the inverter INV2 is electrically connected to the output terminal of the CKSB signal, and the output terminal of the inverter INV2 is used as the output terminal of the CKS signal.

The whole circuit analysis can be obtained, if D=Q, that is, when the input of D flip-flop circuit 1 is equal to the output, if CLK=0, then the pull-up network of the first gate control circuit 2-1 is turned on CKMB=1, CKM= 0, the pull-down network of the second gating circuit 2-2 is turned on CKSB=0, CKS=1, at this time, the transmission gate TG1 in the D flip-flop circuit 1 is turned off, the transmission gate TG2 is turned on; the transmission gate TG3 is turned on, and the transmission Gate TG4 is closed.

If CLK=1, then the pull-up network of the first gating circuit 2-1 is turned on CKMB=1, CKM=0, the pull-down network of the second gating circuit 2-2 is turned on CKSB=0, CKS=1, transmission The gate TG1 is turned off, the transmission gate TG2 is turned on, the transmission gate TG3 is turned on, and the transmission gate TG4 is turned off. It can be concluded from this that when the input and output signals are always equal for a certain period of time, no matter how the clock signal CLK changes, the transmission gate TG1 of the main flip-flop is always turned off, and the D flip-flop circuit 1 does not work.

If D≠Q, that is, when the input of D flip-flop circuit 1 is not equal to the output, if CLK=0, the pull-up network of the first gate control circuit 2-1 is turned on CKMB=1, CKM=0, and the second gate control The pull-up network of circuit 2-2 is turned on CKSB=1, CKS=0, the transmission gate TG1 is turned off, and the input data cannot be transmitted through the transmission gate.

If CLK=1, the pull-down network of the first gating circuit 2-1 is turned on CKMB=0, CKM=1, the pull-down network of the second gating circuit 2-2 is turned on CKSB=0, CKS=1, and the transmission gate TG1 is turned on, D flip-flop circuit 1 starts to collect signals between the master flip-flop and the slave flip-flop, but since the transmission gate TG3 is turned off at this moment, the output signal can only be kept between the master flip-flop and the slave flip-flop There is no change in the output between the signal collection points. When the next clock signal CLK jumps, that is, when CLK=0, the transmission gate TG3 is turned on, and the data stored in the signal collection point of the D flip-flop circuit 1 is transmitted to the output terminal.

As shown in Figure 3, it is the simulation result of the master-slave D flip-flop reset by the gated clock. The period of the clock CLK is 3s, the period of the input signal D is 20s, and the period of the reset signal rb is 72s.

At time t1, rb=1, D=Q, at this time, whether the clock signal CLK is equal to 0 or 1, CKMB is equal to 1, and CKSB is equal to 0. t1 to t2 clock, D≠Q, CLK=0, corresponding CKMB=1, CKSB=1. At time t2, D≠Q, due to the arrival of the rising edge of the clock signal CLK, the output signal Q=D, CKMB=1, CKSB=0. From t3 to t4, also because D≠Q, CLK jumps from high level 1 to low level 0, when CLK=1, CKMB=0, CKSB=0, when CLK=0, CKMB=1, CKSB= 1. At time t4, D≠Q, the rising edge of CLK arrives, and the output signal Q=D. At T5, rb plays a leading role, rb=0, the output Q=0, and is not affected by signals D and CLK.

The output signal QB is always the inverse of the signal Q (the two are logically non-relational), CKM is equal to the inverse of CKMB, and CKS is equal to the inverse of CKSB. The simulation result corresponds to the circuit principle, so the function is correct.

It can be seen from the simulation waveform diagram that the time of D=Q in the input waveform accounts for about 90%, and the time of D≠Q only accounts for about 10%. Then the switching activity factor α of the reset master-slave D flip-flop based on the gating clock technology =8*0.9+32*0.1=10.4, and under the same input signal conditions, the switching activity of the ordinary reset master-slave D flip-flop α=20*0.9+20*0.1=20, it can be seen that based on the gated clock The power consumption of the technical reset master-slave D flip-flop is only about 50% of that of the ordinary reset master-slave D flip-flop, which meets the design requirements of low power consumption.

Claims (5)

1. a kind of low power consumption master-slave D flip-flop with reset terminal, comprise D flip-flop circuit (1), described D flip-flop circuit (1) is used for input signal D, output signal Q, signal DB and signal QB; And the signal D and the signal DB are mutually logically negated; the output signal Q and the signal QB are mutually logically negated; It is characterized in that the master-slave D flip-flop also includes a double gate control circuit; The double gating circuit includes a first gating circuit (2-1) and a second gating circuit (2-2); The first gating circuit (2-1) is configured to output the signal CKMB according to the level states of the clock signal CLK, the signal D, the signal Q, the signal DB, and the signal QB: the logic negation signal of the signal CKMB is the signal CKM; The second gating circuit (2-2) is configured to output the signal CKSB according to the level states of the clock signal CLK, the signal D, the signal Q, the signal DB and the signal QB: the logic negation signal of the signal CKSB is the signal CKS; The double gating circuit loads the signal CKMB and the signal CKM on both ends of the transmission gate in the master flip-flop of the D flip-flop circuit (1), and loads the signal CKSB and the signal CKS on the slave trigger of the D flip-flop circuit (1). The two ends of the transmission gate in the device, and then control the state of the output signal Q; And the clock signal CLK, signal D, signal Q, signal CKMB and signal CKSB satisfy the following relationship: 2. a kind of low power consumption master-slave D flip-flop with reset terminal according to claim 1, is characterized in that, The first gating circuit (2-1) includes a first POMS, a second PMOS, a third PMOS, a fourth PMOS, a fifth PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS and a fifth NMOS ; The gate of the first NMOS is electrically connected to the CLK signal output terminal, the source of the first NMOS is electrically connected to the drains of the second NMOS and the third NMOS at the same time, and the drain of the first NMOS is simultaneously connected to the first POMS and the second PMOS electrically connected to the source of the third PMOS, and the drain of the first NMOS serves as the CKMB signal output terminal; The gate of the second NMOS is electrically connected to the DB signal output end, the source of the second NMOS is electrically connected to the drain of the fourth NMOS; the gate of the fourth NMOS is electrically connected to the Q signal output end, and the source of the fourth NMOS grounding; The gate of the third NMOS is electrically connected to the D signal output terminal, the source of the third NMOS is electrically connected to the drain of the fifth NMOS; the gate of the fifth NMOS is electrically connected to the QB signal output terminal, and the source of the fifth NMOS grounding; The gate of the first POMS is electrically connected to the CLK signal output terminal, and the drain of the first POMS is connected to V _DD ; The gate of the second PMOS is electrically connected to the Q signal output end, the drain of the second PMOS is electrically connected to the source of the fourth PMOS; the gate of the fourth PMOS is electrically connected to the D signal output end, and the drain of the fourth PMOS connected to V _DD ; The gate of the third PMOS is electrically connected to the QB signal output terminal, the drain of the third PMOS is electrically connected to the source of the fifth PMOS; the gate of the fifth PMOS is electrically connected to the DB signal output terminal, and the drain of the fifth PMOS Connect to V _DD . 3. a kind of low power consumption master-slave D flip-flop with reset terminal according to claim 2, is characterized in that, The second gating circuit (2-2) includes a sixth PMOS, a seventh PMOS, an eighth PMOS, a ninth PMOS, a tenth PMOS, a sixth NMOS, a seventh NMOS, an eighth NMOS, a ninth NMOS, and a tenth NMOS ; The gate of the sixth PMOS is electrically connected to the CLK signal output terminal, the drain of the sixth PMOS is electrically connected to the sources of the seventh PMOS and the eighth PMOS, and the source of the sixth PMOS is simultaneously connected to the sixth NMOS and the seventh NMOS electrically connected to the drain of the eighth NMOS, and the source of the sixth PMOS serves as the CKSB signal output terminal; The gate of the seventh PMOS is electrically connected to the D signal output end, the drain of the seventh PMOS is electrically connected to the source of the ninth PMOS; the gate of the ninth PMOS is electrically connected to the QB signal output end, and the drain of the ninth PMOS connected to V _DD ; The gate of the eighth PMOS is electrically connected to the DB signal output end, the drain of the eighth PMOS is electrically connected to the source of the tenth PMOS; the gate of the tenth PMOS is electrically connected to the Q signal output end, and the drain of the tenth PMOS connected to V _DD ; The gate of the sixth NMOS is electrically connected to the CLK signal output terminal, and the source of the sixth NMOS is grounded; The gate of the seventh NMOS is electrically connected to the QB signal output terminal, the source of the seventh NMOS is electrically connected to the drain of the ninth NMOS; the gate of the ninth NMOS is electrically connected to the QB signal output terminal, and the source of the ninth NMOS grounding; The gate of the eighth NMOS is electrically connected to the D signal output terminal, the source of the eighth NMOS is electrically connected to the drain of the tenth NMOS; the gate of the tenth NMOS is electrically connected to the Q signal output terminal, and the source of the tenth NMOS grounded. 4. a kind of low power consumption master-slave D flip-flop with reset terminal according to claim 1, 2 or 3, is characterized in that, The main flip-flop of the D flip-flop circuit (1) includes an inverter INV3, an inverter INV4, a transmission gate TG1, a transmission gate TG2 and a NAND gate NAND1; The input terminal of the inverter INV3 is electrically connected to the Q signal output terminal, and the output terminal is respectively used as the DB signal output terminal and electrically connected to one of the input and output terminals of the transmission gate TG1, and the other input and output terminal of the transmission gate TG1 is connected to the inverter The input terminal of INV4 is electrically connected; the C terminal of the transmission gate TG1 is electrically connected with the CKMB signal output terminal, and the C terminal of the transmission gate TG1 is electrically connected with the CKM signal output terminal; One of the input terminals of the NAND gate NAND1 is electrically connected to the output terminal of the reset rb signal, the other input terminal of the NAND gate NAND1 is electrically connected to the output terminal of the inverter INV4, and the output terminal of the NAND gate NAND1 is electrically connected to the output terminal of the transmission gate TG2 One of the input and output terminals is electrically connected; the other input and output terminal of the transmission gate TG2 is electrically connected to the input terminal of the inverter INV4; the C terminal of the transmission gate TG2 is electrically connected to the CKM signal output terminal, and the C terminal of the transmission gate TG2 is connected to the CKMB Electrical connection of the signal output terminal; The slave flip-flop of the D flip-flop circuit (1) includes a transmission gate TG3, a transmission gate TG4, a NAND gate NAND2, an inverter INV5, an inverter INV6 and an inverter INV7; One of the input and output terminals of the transmission gate TG3 is electrically connected to the output terminal of the inverter INV4, and the other input and output terminal of the transmission gate TG3 is electrically connected to one of the input terminals of the NAND gate NAND2; the C terminal of the transmission gate TG3 is connected to the CKSB The signal output terminal is electrically connected, and the C terminal of the transmission gate TG3 is electrically connected to the CKS signal output terminal; The other input end of the NAND gate NAND2 is electrically connected to the output end of the rb signal, the output end of the NAND gate NAND2 is electrically connected to the input end of the inverter INV5, and the output end of the inverter INV5 is used as the Q signal output end; One of the input and output terminals of the transmission gate TG4 is electrically connected to the input terminal of the inverter INV7, and the other input and output terminal of the transmission gate TG4 is electrically connected to one of the input terminals of the NAND gate NAND2; the C terminal of the transmission gate TG4 is connected to the CKS The signal output terminal is electrically connected, and the C terminal of the transmission gate TG4 is electrically connected to the CKSB signal output terminal; The output terminal of the inverter INV7 is used as the output terminal of the QB signal; the input terminal of the inverter INV6 is electrically connected to the input terminal of the inverter INV5, and the output terminal of the inverter INV6 is electrically connected to the input terminal of the inverter INV7. 5. a kind of low power consumption master-slave D flip-flop with reset terminal according to claim 4, is characterized in that, also comprises inverter INV1 and inverter INV2; The input terminal of the inverter INV1 is electrically connected to the CKMB signal output terminal, and the output terminal of the inverter INV1 is used as the CKM signal output terminal; The input terminal of the inverter INV2 is electrically connected to the output terminal of the CKSB signal, and the output terminal of the inverter INV2 is used as the output terminal of the CKS signal.