CN209514845U - A kind of simple signal warning circuit - Google Patents
A kind of simple signal warning circuit Download PDFInfo
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- CN209514845U CN209514845U CN201821691504.2U CN201821691504U CN209514845U CN 209514845 U CN209514845 U CN 209514845U CN 201821691504 U CN201821691504 U CN 201821691504U CN 209514845 U CN209514845 U CN 209514845U
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- 238000013461 design Methods 0.000 description 6
- 230000001788 irregular Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 238000011835 investigation Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
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Abstract
The utility model provides a kind of simple signal warning circuit, it include: the alarm signal reset unit for resetting and releasing alarm signal latch mode, for detecting the alarm signal detection and latch units of simultaneously latched system fault-signal, it is used to indicate the alarm condition display unit of system alarm state.
Description
Technical field
The utility model relates to a kind of circuit, especially a kind of simple signal warning circuit.
Background technique
Warning circuit can be used for the real-time monitoring to important system, circuit unit working condition, when system or circuit list
When job failure occurs in member, warning circuit can issue in time alarm signal by forms such as sound, light, electricity, prompt to need to being
System carries out accident analysis and investigation, to reduce or prevent the further damage to system or circuit unit, therefore is a kind of
Very widely used circuit structure.
Currently, the design method of warning circuit is relatively more, summing up them can be mainly divided into following two categories:
First major class is the design method using MCU chip etc. for Detection & Controling core, and this kind of design takes full advantage of
The PLC technology feature of MCU chip can flexibly carry out detection and the alert process of fault-signal.This circuit is because draw
The programmable logic devices such as MCU chip are entered, " run and fly " or " crash " etc., reliability phase are easy under extraneous complex electromagnetic environment
To lower, therefore application receives certain restrictions.In addition, relative cost is also relatively high.
Second major class is set using various passive devices (such as resistance, capacitor) and active device (such as triode, amplifier)
Warning circuit is counted, this kind of design comparison is flexible, and form is also more changeable, has relatively low cost and higher reliability etc.
Feature.But these designs are general only to issue alarm signal under system failure persistent state, after system removes fault-signal certainly
Dynamic synchronous releasing alarm signal.
However, in practical applications, circuit system of a few thing under complex electromagnetic environment during the work time may
Irregular, transient state or unsustainable alarm signal can be issued, system can quickly " be restored " automatically and continue to run later.Such as
This kind of situation of fruit repeatedly occurs and searches reason not in time, and serious security risk may be will cause and cause by taking care of the pence
Great failure, to cause serious loss.
Utility model content
The purpose of this utility model is to provide a kind of simple signal warning circuits, comprising: for resetting and releasing alarm
The alarm signal reset unit of signal latch state, for detecting the alarm signal detection of simultaneously latched system fault-signal and latching
Unit is used to indicate the alarm condition display unit of system alarm state.
It further include enabled control circuit using foregoing circuit, which exports height in generating system failure
Level signal can be used for blocking with making to can control and the effective circuit unit of low level or system.
Alarm signal reset unit includes power supply, reset button, first resistor R1, second resistance R2, first capacitor C1,
One schmitt inverter U1,3rd resistor R3, the first transistor Q1, the 5th resistance R5, first diode D1, the second capacitor C2,
4th resistance R4；One end of reset button connects power supply, and the other end of reset button connects the one end first resistor R1 and second respectively
The one end resistance R2, the second resistance R2 other end connect the first schmitt inverter U1 input terminal and the one end first capacitor C1 respectively, the
One schmitt inverter U1 output end distinguishes the first transistor Q1 base stage and the one end 3rd resistor R3, the first transistor Q1 collector
Power supply and the 5th one end resistance R5 are connect respectively, and the first transistor Q1 emitter connects the 4th one end resistance R4, first diode respectively
D1 cathode and second one end capacitor C2, another termination first diode D1 other end of the 5th resistance R5, the first resistor R1 other end,
The first capacitor C1 other end, the 3rd resistor R3 other end, the 4th resistance R4 other end, second capacitor C2 other end ground connection.
Using foregoing circuit, alarm signal detection and latch units include second Schmidt's NAND gate U2, the 8th resistance R8,
Third schmitt inverter U3, the second diode D2, the 6th resistance R6, the 5th diode D5；Second Schmidt's NAND gate U2
One input the 5th resistance R5 other end of termination, second Schmidt's NAND gate the second input terminal of U2 connect the 5th diode D5 yin respectively
Pole, the 6th resistance R6 other end, the second diode D2 cathode, second Schmidt's NAND gate U2 output end meet the 8th resistance R8 respectively
The other end, third schmitt inverter U3 input terminal, the 5th diode D5 anode connect Error Signal, the 8th one end resistance R8
Ground connection, the 6th one end resistance R6 ground connection, the second diode D2 anode connect third schmitt inverter U3 output end.
Using foregoing circuit, alarm condition display unit includes that third diode D3, the 7th resistance R7, the 4th Schmidt are anti-
Phase device U4, the 5th schmitt inverter U5, the 4th light emitting diode D4, the 9th resistance R9；Third diode D3 anode connects second
Diode D2 anode, third diode D3 cathode connect the 7th resistance R7 other end, the 4th schmitt inverter U4 input terminal respectively,
7th one end resistance R7 ground connection.4th schmitt inverter U4 output the 5th schmitt inverter U5 input terminal of termination, the 5th applies
Close spy phase inverter U5 output the 4th light emitting diode D4 anode of termination, the 4th light emitting diode D4 cathode connect enabled control circuit.
Using foregoing circuit, enabling control circuit includes the 5th diode R5, the 9th resistance R9；9th resistance R9 mono- termination
Ground, the 9th resistance R9 other end meet the 5th diode D5 anode and the 4th light emitting diode D4 cathode, the 5th diode D5 respectively
Cathode, which connects, makes can control signal Enable.
The utility model compared with prior art, has the advantage that the simple signal alarm electricity of the utility model design
Road can be immediately detected fault-signal and be latched when important system or circuit unit break down, and pass through alarm condition
Display unit indicates that monitored system or circuit unit are in malfunction or failure once occurred, overcomes traditional alert
Circuit is to certain unsustainable, irregular or transient fault the problem of failing to report.In addition, enabled control circuit can detect
It is blocked after alarm signal with making to can control and the correlation output control function of the effective circuit unit of low level or system, is reduced
Further damage.The utility model realizes that with strong antijamming capability, cost is relatively low, is easy to apply by discrete part
The features such as.
The utility model is further described with reference to the accompanying drawings of the specification.
Detailed description of the invention
Fig. 1 is the main circuit diagram of the utility model.
Fig. 2 is the circuit system with enabled protection.
Specific embodiment
A kind of simple signal warning circuit, including the detection of alarm signal reset unit, alarm signal and latch units, alarm
Status display unit, enabled control circuit.Alarm signal reset unit is alarmed for resetting and releasing alarm signal latch mode
For detection and latched system fault-signal, alarm condition display unit is used to indicate system alarm for signal detection and latch units
State, enabled control circuit export high level signal in generating system failure, can be used for blocking with making to can control and low electricity
Equal effective circuit unit or system.
The applicable system failure occurring mode of the utility model and fault-signal Error Signal type have following special
Sign:
(1) it can be continued for malfunction after system jam, can restore and remove automatically after of short duration failure
Fall fault-signal, is also applied for other irregular system failure types.
(2) system failure signal Error Signal can be high electricity by low level signal jump in generating system failure
Ordinary mail number, and high level state is always maintained at until malfunction disappearance during the system failure continues, then jump is low again
Level signal；An instantaneous high level pulse signal, Huo Zheqi can also be only exported in the when Error Signal to break down
There is the signal of rising edge in it.
(3) alarm signal detection once detects system failure signal Error Signal with latch units, can be immediately
Latched system fault-signal Error Signal simultaneously indicates system alarm state until system event by alarm condition display unit
Barrier signal Error Signal restores low level state and carries out alarm condition reset.
As shown in Figure 1, setting the voltage of power Vcc in the utility model as 15V, R5/R4=17.5, i.e. the resistance value of R4 is remote
Less than R5.
Alarm signal reset unit for resetting and releasing alarm signal latch mode includes power Vcc, reset button
Reset, first resistor R1, second resistance R2, first capacitor C1, the first schmitt inverter U1,3rd resistor R3, first crystal
Pipe Q1, the 5th resistance R5, first diode D1, the second capacitor C2, the 4th resistance R4.
Wherein, reset button Reset one end connect power Vcc, the other end pass through respectively first resistor R1 be connected to Gnd and
Second resistance R2 is connected to the input terminal of the first schmitt inverter U1, and the output of the first schmitt inverter U1 is connected to the first crystalline substance
The base stage of body pipe Q1.One end of first capacitor C1 connects the input terminal of the first schmitt inverter U1, another to be connected to Gnd.The
The base stage of one end connection the first transistor Q1 of three resistance R3, it is another to be connected to Gnd.The collector of the first transistor Q1 connects electricity
Source Vcc, emitter are connected to Gnd by first resistor R4.The anode of first diode D1 passes through the 5th resistance R5 connection power supply
Vcc, cathode connects the emitter of the first transistor Q1, while cathode is connected to Gnd by the second capacitor C2.
In normal state, reset button Reset will not be pressed, and the current potential of A point pulled down to Gnd at this time, under stable state
The current potential of U1 input terminal equally pulled down to Gnd, therefore U1 output is high level, Q1 conducting.The current potential of B point is electrically charged in C2
The value of stable to approximate power Vcc afterwards.The current potential of D1 anode has relationship as follows
The current potential of B point < D1 anode current potential < power Vcc current potential
Therefore, in normal state, the current potential of D1 anode can be approximately high level.
After generating system failure, when needing to reset alarm signal detection with latch units, reset button is pressed
Reset.The current potential of A point is pulled to rapidly power Vcc, and the current potential of the input terminal of U1 will not be jumped because of the presence of capacitor C1
Become.The effect of C1 is the input terminal electricity that A point current potential high rate intermittent phenomenon makes U1 caused by preventing the movement because of reset button Reset
Also there is high rate intermittent situation in position, that is, has the function of that button disappears and tremble.
The about value of power Vcc, therefore U1 output low level, Q1 cut-off after the current potential of U1 input terminal is stable.Q1 cut-off
The current potential at moment, B point is still approximately the value of Vcc, and hereafter C2 begins through R4 electric discharge.According to predetermined R5/R4=17.5
Quantitative relation it is found that B point current potential stablize extremely:
The current potential of D1 anode is slightly above the current potential of B point, but still is approximately low level.
The discharge time of C2 is also related with the resistance value of the capacitance of C2 itself and R4 in addition to related with the stable potential of B point,
Assume that discharge time is Δ t in the utility model.
Therefore, when being resetted, the time for pressing reset button Reset is at least greater than time Δ t and just can guarantee D1
The current potential of anode is changed into low level from high level, to reset alarm signal detection and latch units.
For detect and latched system fault-signal alarm signal detection with latch units including the second Schmidt with it is non-
Door U2, the 8th resistance R8, third schmitt inverter U3, the second diode D2, the 6th resistance R6, the 5th diode D5.
Wherein, the pin 1 of U2 connects the anode of D1, and pin 2 connects the cathode of D2, and output end is connected to Gnd by resistance R8.
The input terminal of U3 and the output end of U2 connect, and output end connects the anode of D2.The cathode of D2 is connected to Gnd by R6.Error
The anode of Signal connection D5, the pin 2 of the cathode connection U2 of D5.
According to analysis above it is found that in normal state, Error Signal is low level, the current potential of U2 pin 1 is
High level, pin 2 is pulled down to Gnd by R6, therefore U2 exports high level.Output is low level after U3 reverse phase, and D2 forward direction is cut
Only.
After generating system failure, the rising edge that a high level occurs in jump occurs for Error Signal, and D5 moment is just
To conducting, and occurs high level on R6.Occurs state flat for high point simultaneously on the pin 1 and pin 2 of U2, then U2 output is low
Level, U3 export high level, and D2 forward conduction simultaneously forms high level on R6.Hereafter, the pin 1 of U2 continues to keep with pin 2
It is simultaneously the state of high level, even if Error Signal removes high level state, which can be also sustained, and be realized
The alarm signal of the system failure is latched.
According to analysis it is found that as long as the rising edge that high level occurs in Error Signal will trigger above-mentioned alarm signal lock
Mechanism is deposited, is therefore particularly suitable for that real-time detection is irregular or transient state, the unsustainable system failure of Error Signal.
After accident analysis and investigation, reset button Reset and at least duration of Δ t are pressed, by point before
Analysis is it is found that the current potential of U2 pin 1 is pulled down to low level, and U2 exports high level, and U3 output is low level, the cut-off of D2 forward direction, U2
Pin 2 is pulled down to low level by R6.After unclamping reset button Reset, the pin 1 of U2 becomes high level again, and pin 1 is low electricity
It is flat, the latch to former alarm signal is released, and restart to be monitored Error Signal.
The alarm condition display unit for being used to indicate system alarm state includes third diode D3, the 7th resistance R7,
Four schmitt inverter U4, the 5th schmitt inverter U5, the 4th light emitting diode D4 and the 9th resistance R9.
According to analysis above it is found that in normal state, U3 exports low level, therefore D3 forward direction is ended, the input of U4
Terminal potential is pulled down to low level by R7, and U4 exports high level, and U5 exports low level, and the cut-off of D4 forward direction does not shine, and expression is not examined
Measure the system failure.In generating system failure, U3 exports high level, therefore D3 forward conduction, on the input terminal potential of U4
It is pulled to high level, U4 exports low level, and U5 exports high level, and D4 forward conduction shines, and expression detects the system failure.D4 hair
Light, which is continued until after system removes Error Signal and Reset reset Δ t, to be terminated.
It enables the 5th diode D5 of control circuit and makes to can control signal Enable, wherein the yin of the anode connection D4 of D5
Pole.As the above analysis, in normal state, the anode of D5 is pulled down to low level, the cut-off of D5 forward direction by R9；Detection system event
After barrier, the anode of D5 is high level, forward conduction.
As shown in Fig. 2, the cathode of D5 can be connected to protected circuit system, the circuit system have enabled control terminal and
Low level is effective.After detecting the system failure, the cathode level of D5 is high level, therefore circuit system is removed enabled letter
Number, corresponding output is blocked and plays a protective role.
System failure signal Error Signal accesses Warning signal monitoring and latch units, under normal condition, Error
Signal is low level signal；When a system failure occurs, there is the jump of high level rising edge in Error Signal, to trigger
Alarm signal testing mechanism is simultaneously latched.At this point, alarm condition display unit indicator light D4 is lighted, generating system failure is indicated.
After carrying out accident analysis and investigation, after pressing the reset button Reset in alarm condition reset unit and continuing the Δ t time
It unclamps, if indicator light D4 extinguishes, then it represents that the system failure has released, and cancels the latch to former alarm signal, and restart
Error Signal is monitored；, whereas if indicator light D4 is still lighted, then it represents that system is still faulty.
Claims (5)
1. a kind of simple signal warning circuit characterized by comprising
For resetting and releasing the alarm signal reset unit of alarm signal latch mode,
For detecting the alarm signal detection and latch units of simultaneously latched system fault-signal,
It is used to indicate the alarm condition display unit of system alarm state；
Alarm signal reset unit include power supply, reset button, first resistor (R1), second resistance (R2), first capacitor (C1),
First schmitt inverter (U1), 3rd resistor (R3), the first transistor (Q1), the 5th resistance (R5), first diode (D1),
Second capacitor (C2), the 4th resistance (R4)；Wherein
One end of reset button connects power supply,
The other end of reset button connects first resistor one end (R1) and the one end second resistance (R2) respectively,
Second resistance (R2) other end connects the first schmitt inverter (U1) input terminal and the one end first capacitor (C1) respectively,
First schmitt inverter (U1) output end distinguishes the first transistor (Q1) base stage and the one end 3rd resistor (R3),
The first transistor (Q1) collector connects power supply and the 5th one end resistance (R5) respectively,
The first transistor (Q1) emitter connects the 4th one end resistance (R4), first diode (D1) cathode and the second capacitor respectively
(C2) one end,
Another termination first diode (D1) other end of 5th resistance (R5),
First resistor (R1) other end, first capacitor (C1) other end, 3rd resistor (R3) other end, the 4th resistance (R4) are another
End, the second capacitor (C2) other end ground connection；
Alarm signal detection is anti-including second Schmidt's NAND gate (U2), the 8th resistance (R8), third Schmidt with latch units
Phase device (U3), the second diode (D2), the 6th resistance (R6), the 5th diode (D5)；Wherein
Second Schmidt's NAND gate (U2) first input end connects the 5th resistance (R5) other end,
It is another that second the second input terminal of Schmidt's NAND gate (U2) connects the 5th diode (D5) cathode, the 6th resistance (R6) respectively
End, the second diode (D2) cathode,
It is defeated that second Schmidt's NAND gate (U2) output end connects the 8th resistance (R8) other end, third schmitt inverter (U3) respectively
Enter end,
5th diode (D5) anode meets Error Signal,
8th resistance one end (R8) ground connection,
6th resistance one end (R6) ground connection,
Second diode (D2) anode connects third schmitt inverter (U3) output end.
2. circuit according to claim 1, which is characterized in that further include enabled control circuit, which exists
High level signal is exported when generating system failure, can be used for blocking with making to can control and the effective circuit unit of low level or be
System.
3. circuit according to claim 2, which is characterized in that alarm signal detection includes the second Schmidt with latch units
NAND gate (U2), the 8th resistance (R8), third schmitt inverter (U3), the second diode (D2), the 6th resistance (R6), the 5th
Diode (D5)；Wherein
Second Schmidt's NAND gate (U2) first input end connects the 5th resistance (R5) other end,
It is another that second the second input terminal of Schmidt's NAND gate (U2) connects the 5th diode (D5) cathode, the 6th resistance (R6) respectively
End, the second diode (D2) cathode,
It is defeated that second Schmidt's NAND gate (U2) output end connects the 8th resistance (R8) other end, third schmitt inverter (U3) respectively
Enter end,
5th diode (D5) anode meets Error Signal,
8th resistance one end (R8) ground connection,
6th resistance one end (R6) ground connection,
Second diode (D2) anode connects third schmitt inverter (U3) output end.
4. circuit according to claim 3, which is characterized in that alarm condition display unit include third diode (D3),
7th resistance (R7), the 4th schmitt inverter (U4), the 5th schmitt inverter (U5), the 4th light emitting diode (D4),
Nine resistance (R9)；Wherein
Third diode (D3) anode connects the second diode (D2) anode,
Third diode (D3) cathode connects the 7th resistance (R7) other end, the 4th schmitt inverter (U4) input terminal respectively,
7th resistance one end (R7) ground connection,
4th schmitt inverter (U4) output the 5th schmitt inverter (U5) input terminal of termination,
5th schmitt inverter (U5) output the 4th light emitting diode (D4) anode of termination,
4th light emitting diode (D4) cathode connects enabled control circuit.
5. circuit according to claim 4, which is characterized in that enabled control circuit includes the 5th diode (R5), the 9th
Resistance (R9)；Wherein
9th resistance one end (R9) ground connection,
9th resistance (R9) other end connects the 5th diode (D5) anode and the 4th light emitting diode (D4) cathode respectively,
5th diode (D5) cathode, which connects, makes can control signal Enable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821691504.2U CN209514845U (en) | 2018-10-18 | 2018-10-18 | A kind of simple signal warning circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821691504.2U CN209514845U (en) | 2018-10-18 | 2018-10-18 | A kind of simple signal warning circuit |
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| CN209514845U true CN209514845U (en) | 2019-10-18 |
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| CN201821691504.2U Withdrawn - After Issue CN209514845U (en) | 2018-10-18 | 2018-10-18 | A kind of simple signal warning circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109326092A (en) * | 2018-10-18 | 2019-02-12 | 中国船舶重工集团公司第七六研究所 | A kind of simple signal warning circuit |
-
2018
- 2018-10-18 CN CN201821691504.2U patent/CN209514845U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109326092A (en) * | 2018-10-18 | 2019-02-12 | 中国船舶重工集团公司第七六研究所 | A kind of simple signal warning circuit |
| CN109326092B (en) * | 2018-10-18 | 2024-04-05 | 中国船舶集团有限公司第七一六研究所 | Simple signal alarm circuit |
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Effective date of registration: 20201118 Address after: 222061 Jiangsu city of Lianyungang Province Lake Road No. 18 Patentee after: 716TH RESEARCH INSTITUTE OF CHINA SHIPBUILDING INDUSTRY Corp. Patentee after: CSIC Information Technology Co.,Ltd. Address before: 222061 Jiangsu city of Lianyungang Province Lake Road No. 18 Patentee before: 716TH RESEARCH INSTITUTE OF CHINA SHIPBUILDING INDUSTRY Corp. Patentee before: JIANGSU JARI TECHNOLOGY GROUP Co.,Ltd. |
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| TR01 | Transfer of patent right | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 222061 No.18, Shenghu Road, Lianyungang City, Jiangsu Province Patentee after: The 716th Research Institute of China Shipbuilding Corp. Patentee after: CSIC Information Technology Co.,Ltd. Address before: 222061 No.18, Shenghu Road, Lianyungang City, Jiangsu Province Patentee before: 716TH RESEARCH INSTITUTE OF CHINA SHIPBUILDING INDUSTRY Corp. Patentee before: CSIC Information Technology Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 222061 No.18, Shenghu Road, Lianyungang City, Jiangsu Province Patentee after: The 716th Research Institute of China Shipbuilding Corp. Patentee after: China Shipbuilding Digital Information Technology Co.,Ltd. Address before: 222061 No.18, Shenghu Road, Lianyungang City, Jiangsu Province Patentee before: The 716th Research Institute of China Shipbuilding Corp. Patentee before: CSIC Information Technology Co.,Ltd. |
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