CN209401632U - A kind of crystal of molybdenum disulfide pipe - Google Patents
A kind of crystal of molybdenum disulfide pipe Download PDFInfo
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- CN209401632U CN209401632U CN201821530305.3U CN201821530305U CN209401632U CN 209401632 U CN209401632 U CN 209401632U CN 201821530305 U CN201821530305 U CN 201821530305U CN 209401632 U CN209401632 U CN 209401632U
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Abstract
The utility model discloses a kind of crystal of molybdenum disulfide pipes, with PMMA/SiO2 for lower dielectric layer in the transistor, using PMMA as upper dielectric layer, so that the interface conditions of transistor channel are greatly improved, so that high-field effect electron mobility and minimum lag may be implemented in crystal of molybdenum disulfide pipe, device performance is greatly improved.
Description
The utility model obtains the special " micro nano biochemical sensitive of state key research and development plan " the advanced electronic material of strategy " emphasis
The support of material and device " project (2017YFB0405400).
Technical field
The utility model relates to a kind of transistor more particularly to two-dimensional material transistors.
Background technique
Since Geim in 2004 is tested with Novoselov team for the first time and to be separated graphene, two-dimensional material is unique because of its
Property has many applications.With graphene, molybdenum disulfide, tungsten selenide, hexagonal boron nitride, phosphorus alkene, silene, the discovery of tin alkene and
Research, two-dimensional material family is in lasting growth.Molybdenum disulfide in two-dimensional material family member, in transient metal sulfide
It represents and studies one of material the most deep, because it has forbidden bandwidth and high carrier mobility with its current maturation
Production method is extremely superior as next-generation electronics and photoelectronic semiconductor channel material.Application for electronic device,
Molybdenum disulfide has had shown that outstanding transmission performance, i.e., can be more than with the transistor mobility that high k dielectric layer makees top-gated
100cm2/Vs.For its photovoltaic applications, molybdenum disulfide has the band gap related with thickness of 1.3eV to 1.8eV, transistor
Has 734.5AW-1Optical responsivity and the 5ms under illumination illumination and it is dark under short response and recovery time.
However it remains about improve molybdenum disulfide device performance be not solved the problem of, for example, why curing
Can molybdenum transistor degenerate for a long time at room temperature, what is the mechanism lagged in transfer characteristic?
Firstly, the transistor in the molybdenum disulfide of non-industrial laboratories production is often stored under air environment and is passed through after a few days
Go through the degeneration of electric property.Oxygen and hydrone in air can lead to performance degradation in the absorption of molybdenum disulfide channel surface.
Secondly, the transfer curve of molybdenum disulfide field effect transistor is usually in the forward scan of grid voltage and reverse scan
Between show lag.Hysteresis is derived from electric stress caused by grid bias, by water in environment and oxygen molecule in molybdenum disulfide
Caused by the adsorption and desorption on surface.
Carrier scattering is often derived from a coulomb impurity, and the defect of trap and molybdenum disulfide, this serious can influence device
Performance.In the case where the short time is exposed to environmental condition, the on-state current of molybdenum disulfide device is remarkably decreased, this may be due to two sulphur
Change the increase of additional scattering center caused by the upper adsorbate of molybdenum defect sites.In fact, when use hafnium oxide dielectric or
When interlayer boron nitride dielectric, the carrier scattering as caused by coulomb impurity can be inhibited and be shielded by dielectric.
In general, these modes for improving carrier mobility need vacuum probe platform or low-temperature test condition or complexity
Passivation Treatment.However, not yet occurring fully considering that the inhibition of interface carrier scattering and long term electrical stability are kept and stagnant
Strategy afterwards.
Summary of the invention
The utility model discloses a kind of crystal of molybdenum disulfide pipes, have the carrier mobility improved, have simultaneously
Minimum lag and threshold voltage shift.
The utility model discloses a kind of crystal of molybdenum disulfide pipes, and transfer characteristic in crystal of molybdenum disulfide pipe may be implemented
Lag minimizes the electrical stability at least five weeks or more in curve.In brief, we use the double-layer structure of PMMA, i.e.,
Improve boundary condition together as compound medium layer in bottom-gate device using PMMA and silica first, secondly uses PMMA
It is covered on molybdenum disulfide channel surface and plays the role of encapsulation, the carrier mobility of crystal of molybdenum disulfide pipe can be significantly improved
Rate, and make it have minimum lag.
The molybdenum disulfide of the utility model includes:
Semiconductor substrate；
It is provided with grid on a semiconductor substrate；
First medium layer is provided on grid；
Second dielectric layer is provided on first medium layer；
There is two-dimensional semiconductor layer in second dielectric layer；
On two-dimensional semiconductor layer and its side has source/drain electrode；
There is third dielectric layer on two-dimensional semiconductor layer and source/drain electrode；Wherein,
The first medium layer is silica；
The second dielectric layer is PMMA；
The two-dimensional semiconductor layer is molybdenum disulfide；
The third dielectric layer is PMMA.
Wherein, the preferred silicon wafer of substrate；
Grid can be the gate portion directly formed on a semiconductor substrate by heavy doping；
The first medium layer with a thickness of 50-150nm；The second dielectric layer with a thickness of 200-300nm；The third is situated between
Matter layer with a thickness of 200-300nm；
Preferably, the first medium layer with a thickness of 80-120nm；The second dielectric layer with a thickness of 230-270nm；It should
Third dielectric layer with a thickness of 230-270nm；
Preferably, the first medium layer with a thickness of 100nm, the second dielectric layer with a thickness of 250nm；The third medium
Layer with a thickness of 250nm.
Preferably, the material of source/drain electrode is titanium/billon.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the crystal of molybdenum disulfide pipe of the utility model.
Fig. 2 is the structural representation of transistor in each step in the manufacturing method of the crystal of molybdenum disulfide pipe of the utility model
Figure.
Fig. 3 are as follows: Fig. 3 a is the scanning electron microscope image of crystal of molybdenum disulfide pipe；Fig. 3 b is two sulphur in the transistor
Change the atomic force microscope shape appearance figure and altitude profile of molybdenum film.Fig. 3 c is the Raman spectrum of molybdenum disulfide film；Fig. 3 d is two
Vulcanize the PL spectrum picture of molybdenum film.
Fig. 4 shows the transfer characteristic curve of the molybdenum disulfide field effect transistor of four kinds of different structures.
Fig. 5 shows the molybdenum disulfide field effect transistor of the grid biases different with two kinds of four kinds of different type structures
Transfer characteristic.
Fig. 6 shows the long-time electrical stability of the molybdenum disulfide field effect transistor of four kinds of different structures.
Fig. 7 shows the energy band diagram of the crystal of molybdenum disulfide pipe of three kinds of different structures.
Specific embodiment
The utility model discloses a kind of antivacuum schemes of simplicity, improve for interface.The two of conventional thermal oxide
Polymeric layer is introduced in silicon oxide substrate, and is used in conjunction with polymer encapsulated device.Using PMMA/SiO2As gate dielectric
Layer, the electron mobility of field effect transistor can be up to 104.6cm2/ Vs is mentioned compared with traditional silicon dioxide dielectric layers
It is 2.5 times high.In addition, the electrical stability of transfer characteristic is greatly mentioned when the grid voltage of ± 35V applies 300s
The offset of height, threshold voltage can be ignored, i.e. 0.1V.With use traditional silicon dioxide dielectric layer device 5.8V threshold voltage
Offset is compared, this is a representative progress.In addition, the molybdenum disulfide device of PMMA encapsulation stores 35 in outdoor placement
After it, electrical stability and field-effect mobility can be very good to keep.
In order to make the clearer molybdenum disulfide field effect transistor for understanding the utility model of those skilled in the art and its
Manufacturing method, the principle of the utility model technical concept, and the mechanism of beneficial effect is generated, it specifically illustrates with reference to the accompanying drawing
The promotion of the electrical stability of the crystal of molybdenum disulfide pipe of the utility model.
As shown in Figure 1, the molybdenum disulfide of the utility model includes:
Semiconductor substrate 1；
It is provided with grid (not shown) on semiconductor substrate 1；
First medium layer 2 is provided on grid；
Second dielectric layer 3 is provided on first medium layer；
There is two-dimensional semiconductor layer 4 in second dielectric layer；
On semiconductor layer 4 and its side has source/drain electrode 5；
There is third dielectric layer 6 on semiconductor layer 4 and source/drain electrode 5；Wherein,
The first medium layer 2 is silica；
The second dielectric layer 3 is PMMA；
The two-dimensional semiconductor layer 4 is molybdenum disulfide；
The third dielectric layer 6 is PMMA.
Wherein, the preferred silicon wafer of substrate；
Grid is preferably the gate portion directly formed on a semiconductor substrate by heavy doping；
The first medium layer with a thickness of 50-150nm；The second dielectric layer with a thickness of 200-300nm；The third is situated between
Matter layer with a thickness of 200-300nm；
Preferably, the first medium layer with a thickness of 80-120nm；The second dielectric layer with a thickness of 230-270nm；It should
Third dielectric layer with a thickness of 230-270nm；
Preferably, the first medium layer with a thickness of 100nm, the second dielectric layer with a thickness of 250nm；The third is situated between
Matter layer with a thickness of 250nm.
Preferably, the material of source/drain electrode is titanium/billon.
As shown in Fig. 2, the manufacturing method of the crystal of molybdenum disulfide pipe of the utility model, includes the following steps:
Prepare semiconductor substrate 1；
Grid is formed on semiconductor substrate 1；
First medium layer 2 is deposited on grid；
Second dielectric layer 3 is formed on first medium layer 2；
Two-dimensional semiconductor layer 4 is formed in second dielectric layer 3；
Source/drain electrode 5 is formed on two-dimensional semiconductor layer 4；
Third dielectric layer 6 is formed in two-dimensional semiconductor layer 4 and source/drain electrode 5；Wherein,
The first medium layer is silica；
The second dielectric layer is PMMA；
The two-dimensional semiconductor layer is molybdenum disulfide；
The third dielectric layer is PMMA.
Specifically, the manufacturing method of the crystal of molybdenum disulfide pipe of the utility model includes the following steps:
Prepare semiconductor substrate 1, the preferred silicon wafer of substrate；
Grid (not shown) is formed on silicon wafer；Grid is preferably directly on a semiconductor substrate by heavy doping formation
Gate portion；
First medium layer 2 is formed on grid, and second dielectric layer 3 is formed on first medium layer 2；
Specifically, the first medium layer 2 is silica, which is PMMA；
Specifically, the first medium layer with a thickness of 50-150nm；The second dielectric layer with a thickness of 200-300nm；It should
Third dielectric layer with a thickness of 200-300nm；
Preferably, the first medium layer with a thickness of 80-120nm；The second dielectric layer with a thickness of 230-270nm；It should
Third dielectric layer with a thickness of 230-270nm；
Preferably, the first medium layer with a thickness of 100nm, the second dielectric layer with a thickness of 250nm；The third is situated between
Matter layer with a thickness of 250nm.
Specifically, the method for forming silica is thermal oxide；The method for forming PMMA second dielectric layer is spin coating, and
It is toasted after spin coating；The method for forming PMMA third dielectric layer is spin coating, and is toasted after spinning.
In a specific embodiment, semiconductor substrate is cleaned, silica first is formed in substrate surface after processing and is situated between
Matter layer；
Specifically, the step may include following method, (1) N is cleaned2Rifle prepurge.(2) 90 5%Decon, ultrasound
After 5min, a large amount of DI water are rinsed.(3) it after being rinsed with a large amount of DI water, is put into 1 beaker of DI water ultrasonic
5min.(4) it is put into 2 beaker of DI water and is taken out after ultrasound 5min, use N immediately2Rifle drying.(5) ultrasonic in acetone
It is taken out after 5min, is immediately placed in ethyl alcohol beaker.(6) it is taken out after ultrasound 5min in ethanol, uses N immediately2Rifle drying.
Then, 250nmPMMA is obtained within two minutes in 4000 revs/min of lower spin coatings using spin coating instrument, dry under 150 degrees Celsius
It is 1 hour roasting.
After grid, first medium layer, second dielectric layer is formed on the substrate, semiconductor is prepared again in second dielectric layer
Layer, semiconductor layer is molybdenum disulfide film.
Specifically, the method for preparing molybdenum disulfide film is, block molybdenum disulfide material is placed on adhesive tape, is sticked repeatedly
Then tear tape sticks adhesive tape on substrate, tear adhesive tape off, obtains including substrate and its molybdenum disulfide film above.
In one embodiment, using the molybdenum disulfide material of high-purity, a fritter block molybdenum disulfide is taken, is placed
On Scotch adhesive tape, then repeatedly stick tear tape, repeatedly after adhesive tape is sticked on substrate base, tear off adhesive tape obtain shape
At the multilayer molybdenum disulfide film on substrate.
After forming molybdenum disulfide semiconductor layer on dielectric layer, source/drain electrode is formed on the semiconductor layer.
Specifically, can deposit to form source/drain electrode by electron beam evaporation；The material of source/drain electrode can be titanium/gold
Alloy.
In a specific embodiment, multi-layer nano molybdenum disulfide film is positioned using optical microscopy, used
Shadowmask defines electrode position, is placed in electron beam evaporation depositing system, and titanium (Ti)/gold (Au) electricity of 5/70nm is deposited
Pole.
It forms source/drain electrode and then forms third dielectric layer on the source/drain electrodes, obtain crystal of molybdenum disulfide pipe.
Specifically, the method for forming third dielectric layer are as follows: the device rotary coating 250nmPMMA that will be made toasts 1 at 110 DEG C
Hour, it is packaged, obtains molybdenum disulfide field effect transistor.
As described in above content, the utility model in crystal of molybdenum disulfide pipe by introducing polymer architecture, Wo Mencheng
The carrier mobility and electric property for maintaining device of function remain minimum at least at follow-on test 35 days
The offset of lag and threshold voltage.Particularly, compared with the bottom gate molybdenum disulfide device for using traditional silicon dioxide dielectric layer,
The carrier mobility of device has been improved at least twice together as dielectric layer and using PMMA packaging by PMMA.This
It is to have the function of due to PMMA dual, on the one hand protects the channel of molybdenum disulfide from external chemisorption, on the other hand
Inhibit the coulomb impurity scattering at interface.This comprehensive research is not only understood that the decaying machine of the transistor based on two-dimensional material
Reason is paved the way, and provides a kind of effective ways for keeping and improving its electric property.
In order to compare the structure and its obtained device performance of crystal of molybdenum disulfide pipe of manufacturing method of the utility model, I
Manufactured four kinds of molybdenum disulfide field effect transistors with different structure, comprising: (a) traditional silicon dioxide gate dielectric
Layer；(b) traditional silicon dioxide gate dielectric layer, while being encapsulated using PMMA；(c) PMMA and the double dielectric layers of silica；(d)
PMMA and the double dielectric layers of silica, while being encapsulated using PMMA.
We are studying threshold value electricity using the transfer characteristic of Agilent B2902 parameter analyzer measurement field effect transistor
When pressure lag, drain voltage VDSIt is set as 0.1V, and grid voltage is scanned and returned from -30V to 30V.When round-trip scanning
Between be 16s (0.75V/ step).In order to verify the tolerance of stress caused by grid bias, we have studied devices at room temperature
Transfer characteristic under positive gate bias (35V) and negative gate bias (- 35V).
The scanning electron microscope image of device is as shown in Figure 3a, we select the curing with same thickness 30nm
Molybdenum film shows the atomic force microscope shape appearance figure and altitude profile of molybdenum disulfide film in Fig. 3 b.The number of plies of molybdenum disulfide
Along with E from AFM data1 2gAnd A1 gThe red shift at peak.Fig. 3 c and Fig. 3 d are respectively the Raman spectrum and PL light of molybdenum disulfide film
Spectrogram picture.
As shown in Figure 3c, Raman spectrum shows E1 2gAnd A1 gIt is peak-to-peak away from for 25cm between vibration mode-1, this shows
The molybdenum disulfide film is more than four layers.As shown in Figure 3d, luminescence generated by light (PL) spectrum of molybdenum disulfide film is also shown again
Strong peak near 950nm, it is 1.3eV that this, which corresponds to multilayer molybdenum disulfide indirect band gap,.
As shown in figure 4, including the curing of the crystal of molybdenum disulfide pipe and other three kinds of different structures of the utility model
The transfer characteristic curve of molybdenum field effect transistor.Wherein,
Fig. 4 a is silicon dioxide dielectric layers, unused PMMA third dielectric layer encapsulation.
Fig. 4 b is silicon dioxide dielectric layers, the encapsulation of PMMA third dielectric layer.
Fig. 4 c is the double dielectric layers of PMMA/ silica, unused PMMA third dielectric layer encapsulation.
Fig. 4 d is the double dielectric layers of PMMA/ silica of the utility model, and with two sulphur of PMMA third dielectric layer encapsulation
Change molybdenum transistor.
At room temperature, VDSFor 0.1V.Field-effect electron mobility is mentioned from the slope of the transfer curve range of linearity
It takes.For Fig. 4 a and Fig. 4 b, the width and length of channel are 40/27 μm.For Fig. 4 c and Fig. 4 d, the width and length of channel
Degree is 34/69 μm.
Using PMMA encapsulated layer, molybdenum disulfide field effect transistor shows higher dIDS/dVGSWith smaller lag.
From the point of view of transfer characteristic, the crystal of molybdenum disulfide pipe of the unencapsulated 30nm based on silicon dioxide dielectric layers, PMMA encapsulation based on
The transistor of silicon dioxide dielectric layers, the unencapsulated transistor based on PMMA/ silicon dioxide dielectric layers, PMMA encapsulation based on
The field-effect electron mobility of the transistor of PMMA/ silicon dioxide dielectric layers is respectively 41.8,47.7,91.8 Hes
104.6cm2/Vs。dIDS/dVGSIn VGSIt is as shown in Figure 4 to the fitting a straight line within the scope of 10V for 2.
These the experimental results showed that, PMMA is because its polarity and hydrophobicity can effectively be reduced as caused by chemisorption
Interface impurity scattering, this improves the field-effect mobility of device.In addition, there are double dielectric layers and imitated using the field of PMMA encapsulation
Answering the switching current ratio of transistor has 105The switching current ratio of the order of magnitude, the subthreshold swing of 1.3V/decade and
The grid leakage current I of 0.1pAGS。
As shown in figure 5, including the crystal of molybdenum disulfide pipe of the utility model and applying for other three kinds of different structures
The transfer characteristic of the molybdenum disulfide field effect transistor of two kinds of different grid biases.
Fig. 5 a: silicon dioxide dielectric layers, unencapsulated, grid voltage -35V.
Fig. 5 b: silicon dioxide dielectric layers, PMMA encapsulation, grid voltage -35V.
Fig. 5 c: silicon dioxide dielectric layers, unencapsulated, grid voltage 35V.
Fig. 5 d: silicon dioxide dielectric layers, PMMA encapsulation, grid voltage 35V.
The double dielectric layers of Fig. 5 e:PMMA/ silica, unencapsulated, grid voltage -35V.
Fig. 5 f: the double dielectric layers of the PMMA/ silica of the utility model, PMMA encapsulation, grid voltage -35V.
The double dielectric layers of Fig. 5 g:PMMA/ silica, unencapsulated, grid voltage 35V.
Fig. 5 h: the double dielectric layers of the PMMA/ silica of the utility model, PMMA encapsulation, grid voltage 35V.
It is maximum after the grid voltage of application -35V for based on silicon dioxide dielectric and unencapsulated transistor
Drain current is increased to 4.7 μ A from 4 μ A, and threshold voltage is to negative offset (△ Vth=5.8V), as shown in Figure 5 a.For base
In silicon dioxide dielectric and the transistor that encapsulates, after the grid voltage of application -35V, maximum drain current is from 4.7 μ A
It is increased to 5.2 μ A, and threshold voltage is to negative offset (△ Vth=2.3V), as shown in Figure 5 b.
On the contrary, maximum drain current is down to 3.3 μ A, threshold voltage from 3.9 after the grid bias stress of application+35V
To forward migration (△ Vth=-3.1V), as shown in Figure 5 c.On the other hand, for the device after encapsulation, in the grid of application+35V
After deviated stress, maximum drain current is down to 4.4 μ A from 4.7, and threshold voltage is to forward migration (△ Vth=-1.9V), such as scheme
Shown in 5d.
For based on the double dielectric layers of PMMA/ silica and unencapsulated field effect transistor, in the grid of application -35V
After voltage, maximum drain current is increased to 0.419 μ A from 0.412 μ A, and threshold voltage is to negative offset (△ Vth=
0.6V), as depicted in fig. 5e.For the transistor based on PMMA/ silicon dioxide dielectric and encapsulation, in the grid of application -35V
After voltage, maximum drain current is increased to 0.413 μ A from 0.412 μ A, and threshold voltage is to negative offset (△ Vth=
0.1V), as shown in figure 5f.
On the contrary, maximum drain current is down to 0.409 μ A, threshold from 0.412 after the grid bias stress of application+35V
Threshold voltage is to forward migration (△ Vth=-0.4V), as shown in fig. 5g.On the other hand, for the device after encapsulation, in application+35V
Grid bias stress after, maximum drain current is down to 0.410 μ A from 0.412, and threshold voltage is to forward migration (△ Vth=-
0.1V), as shown in figure 5h.Therefore, electron capture and interface scattering caused by the water and oxygen molecule by inhibiting adsorbed on interfaces,
The lag of transistor can also be effectively reduced.
As shown in fig. 6, including the curing of the crystal of molybdenum disulfide pipe and other three kinds of different structures of the utility model
The long-time electrical stability of molybdenum field effect transistor.In ten period measurements, Fig. 6 a shows the offset of threshold voltage, figure
6b shows carrier mobility before each circulation, and grid voltage applies the bias of 300s at -35V and 35V respectively.Figure
6c shows VGS=-35V, FIG. 6d shows that VGS=35V threshold voltage during continuous measurement 35 days of lasting 300s
Offset.
Fig. 6 a and Fig. 6 b compare the offset of the threshold voltage measured every time and field-effect mobility and prebias curve.It is first
First, compared with the field effect transistor of silicon dioxide dielectric layers, the field effect transistor of the double dielectric layers of PMMA/ silica exists
The offset of small more threshold voltages is shown under the grid bias stress of positive and negative.In addition, with the transistor phase before encapsulation
Than the transistor of PMMA encapsulation shows smaller threshold voltage shift under the grid bias stress of positive and negative.
For the field effect transistor of four kinds of structures, mobility be not to grid bias stress it is very sensitive, such as Fig. 6 b institute
Show.Therefore, our result is demonstrated by using the double dielectric layers of PMMA/ silica and is sealed using PMMA to channel
Dress, greatly improves the field-effect electron mobility and electrical stability of molybdenum disulfide field effect transistor.For two-dimentional material
Glassware part, performance meeting rapid decay under room temperature environment, this is the major issue for limiting its application.This phenomenon may be due to
The caused additional scattering on interface when device exposes in air.
Fig. 6 c and Fig. 6 d show the time effect of threshold voltage shift in molybdenum disulfide field effect transistor, these results
Show that the offset amplitude of threshold voltage is very big, and gradually increase, but after using PMMA encapsulation, the offset of threshold voltage is very
Small and stable, this illustrates that there is the crystal of molybdenum disulfide pipe of bilayer PMMA structure can work normally and not go out for a long time for we
Now apparent performance degradation.
Herein, the following PMMA of molybdenum disulfide provides the interface more hydrophobic than silica, and is making two sulphur
The hydrone adsorbed before changing molybdenum film is less, so that forming less scattering site, it is brilliant that this facilitates molybdenum disulfide field-effect
The increase of body pipe transfer rate.This is consistent with theory before.The theory show in oxide dielectric the chemical impurity of hydroxyl and
The carrier scattering that the hydrone of absorption is formed plays a part of core in the mobility of two-dimensional layer semiconductor transistor.Cause
This, the PMMA encapsulated layer of molybdenum disulfide upper surface protects the channel of our devices from the absorption of water and oxygen molecule, to improve
Electricity transmission performance.
In order to understand the physics and chemical property of PMMA function, we analyze the energy band diagram of crystal of molybdenum disulfide pipe, such as
Shown in Fig. 7.
Fig. 7 show include no PMMA encapsulation and the bis- dielectric layers of PMMA crystal of molybdenum disulfide pipe energy band diagram, wherein
Fig. 7 a is source-channel-drain contact (left side) and this Metals-semiconductor contacts vacuum level.
Fig. 7 b is to apply grid bias (left side) water of PMMA structure crystal of molybdenum disulfide pipe and the chemisorption of oxygen is not used
Schematic diagram and (right side) have the crystal of molybdenum disulfide pipe energy band diagram of chemisorption.
Fig. 7 c is the crystal of molybdenum disulfide pipe schematic diagram (left side) and energy band diagram with bilayer PMMA structure of the utility model
(right side), matches with vacuum condition.
Firstly, considering metal-semiconductor interface when drawing energy band diagram.In the case where no application grid deviatoric stress,
Electronics accumulation layer (Fig. 7 a) is formed in Ti/ molybdenum disulfide interface.At ambient conditions, the defect on molybdenum disulfide surface and hanging
Key can promote the absorption of oxygen and hydrone in air, to form the charge species for influencing band curvature and electron-transport.
Reacting between molybdenum disulfide and oxygen/water is as follows:
H2O+(s)+e-←→H2O(g) (2)
Wherein e-Indicate the electronics in molybdenum disulfide channel, O2(g)/H2O (g) and It indicates
Neutral and electrification oxygen/water.The oxygen and water of absorption can be from the conduction band trapped electrons of molybdenum disulfide, therefore exhaust molybdenum disulfide ditch
Road.Under these conditions, electronics must exhaust induction transmission gesture across additional small channel before entering molybdenum disulfide channel
Build q Φ1.When transistor applies positive gate bias stress, the concentration increase of electronics is conducive to the forward reaction in equation, causes
The electronics captured in molybdenum disulfide channel increases.In this case, channel exhausts potential barrier from q Φ1Increase to q Φ2, so that electric
The transmission of son is more difficult.In the case of channel exhausts induction, the reduction of electron concentration is conducive to reversed in equation in transistor
Reaction, causes to discharge electronics from the oxygen and water of capture.As a result, channel exhausts potential barrier from q Φ1It is reduced to q Φ3So that electronics
Transmission be easier.
It is adsorbed on center of the chemisorption object as scattering on two-dimensional semiconductor material surface.Electric charge capture is attributed to phase
The charge injection at interface between the electric charge transfer and semiconductor and substrate of adjacent adsorbate.When PMMA is covered on molybdenum disulfide table
When face, carrier is less likely to capture (Fig. 7 c) by the chemical substance in air in channel material, this is easier carrier
Into molybdenum disulfide channel, to increase source-drain current and carrier mobility.
By it is above-mentioned elaborate as it can be seen that the utility model crystal of molybdenum disulfide pipe by dielectric layer under PMMA/SiO2 and
PMMA upper dielectric layer successfully maintains the carrier mobility and electric property of device, at least in 35 days situations of follow-on test
Under, remain the offset of minimum lag and threshold voltage.Meanwhile two sulphur of bottom gate of silicon dioxide dielectric layers being used only with tradition
Change molybdenum device to compare, together as dielectric layer and uses PMMA as third dielectric layer in molybdenum disulfide PMMA and silica
The carrier mobility of device can be improved at least twice by packaging on semiconductor layer.To find out its cause, inventor thinks
This is because PMMA has the function of dual, on the one hand protect the channel of molybdenum disulfide from external chemisorption, another party
The coulomb impurity scattering at face inhibition interface.
Claims (9)
1. a kind of crystal of molybdenum disulfide pipe characterized by comprising
Semiconductor substrate；
It is provided with grid on a semiconductor substrate；
Silica dioxide medium layer is provided on grid；
PMMA dielectric layer is provided on silica dioxide medium layer；
There is molybdenum disulfide two-dimensional semiconductor layer on PMMA dielectric layer；
On molybdenum disulfide two-dimensional semiconductor layer and its side has source/drain electrode；
There is PMMA dielectric layer on molybdenum disulfide two-dimensional semiconductor layer and source/drain electrode；Wherein,
The semiconductor substrate is silicon wafer.
2. transistor as described in claim 1, which is characterized in that the first medium layer with a thickness of 50-150nm.
3. transistor as described in claim 1, which is characterized in that the second dielectric layer with a thickness of 200-300nm.
4. transistor as described in claim 1, which is characterized in that the third dielectric layer with a thickness of 200-300nm.
5. transistor as described in claim 1, which is characterized in that grid is directly to pass through heavy doping shape on a semiconductor substrate
At gate portion.
6. transistor as described in claim 1, which is characterized in that source/drain electrode is titanium/billon.
7. transistor as described in claim 1, which is characterized in that the first medium layer with a thickness of 80-120nm.
8. transistor as described in claim 1, which is characterized in that the second dielectric layer with a thickness of 230-270nm.
9. transistor as described in claim 1, which is characterized in that the third dielectric layer with a thickness of 230-270nm.
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2018
- 2018-09-18 CN CN201821530305.3U patent/CN209401632U/en active Active
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