CN209330095U - A kind of software radio general-purpose platform - Google Patents
A kind of software radio general-purpose platform Download PDFInfo
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- CN209330095U CN209330095U CN201920243060.4U CN201920243060U CN209330095U CN 209330095 U CN209330095 U CN 209330095U CN 201920243060 U CN201920243060 U CN 201920243060U CN 209330095 U CN209330095 U CN 209330095U
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Abstract
A kind of software radio general-purpose platform of the utility model, including analog signal processing module, baseband digital signal processing module, clock processing module and power module；Analog signal processing module includes gain adjustment circuit and programmable analog processing chip circuit；Baseband digital signal processing module includes FPGA signal processing circuit and GPP control management circuit；Gain adjustment circuit is connected to carry out gain adjustment with external radio-frequency signal；Programmable analog processing chip circuit is connected with gain adjustment circuit handles radiofrequency signal adjusted；GPP control management circuit and FPGA signal processing circuit and peripheral equipment are respectively connected with to complete base band signal process；FPGA signal processing circuit is connected with programmable analog processing chip circuit to handle chip circuit by programmable analog and externally send or receive radiofrequency signal.The software radio general-purpose platform of the utility model is small in size, low in energy consumption, high reliablity and versatile.
Description
Technical field
The utility model relates to software and radio technique field, especially a kind of software radio general-purpose platform.
Background technique
With the fast development of satellite and wireless communication, becoming increasingly complex of wireless communication technique.It wirelessly communicates substantially
Blocking includes: antenna element, radio frequency unit and Base Band Unit.Currently, there is also multiband, multi-standard, more associations for communication equipment
View and multiplex roles complexity status, it is therefore necessary to which researching and designing is a to support multiband, multi-standard, multi-protocols and multiplex roles
Software radio (SDR) general processing platform, so as to can flexibly, fast implement building, extend and rising for device product system
Grade reduces system development costs to greatly shorten the development cycle of product, improves the market competitiveness.For wireless communication
Basic framework, software radio use standardization, modular design requirement, reconstruct, update according to system function requirement
And updating apparatus system.
But existing Software Radio platform, in hardware design, radio frequency unit often uses super-heterodyne technique principle,
Cause to realize that circuit is complicated in this way, platform haves the shortcomings that volume is big, power consumption is high and reliability is not high；In addition, existing soft
Part radio platforms lack enough versatilities.
Utility model content
The main purpose of the utility model is to overcome in the prior art, propose a kind of small in size, low in energy consumption, high reliablity
Software radio general-purpose platform.
The utility model adopts the following technical solution:
A kind of software radio general-purpose platform, comprising: analog signal processing module, baseband digital signal processing module, when
Clock processing module and power module；The analog signal processing module includes gain adjustment circuit and programmable analog processing chip
Circuit；The baseband digital signal processing module includes FPGA signal processing circuit and GPP control management circuit；The gain tune
Whole circuit is connected to carry out gain adjustment with external radio-frequency signal；The programmable analog processing chip circuit and the gain
Adjustment circuit, which is connected, handles radiofrequency signal adjusted；At the GPP control management circuit and the FPGA signal
Reason circuit and peripheral equipment are respectively connected with to complete base band signal process；The FPGA signal processing circuit may be programmed with described
Simulation process chip circuit is connected to handle chip circuit by the programmable analog and externally send or receive radiofrequency signal；
The clock processing module and the programmable analog processing chip circuit and the FPGA signal processing circuit be respectively connected with
Treated clock signal is sent, the clock signal includes external timing signal or local clock pulses；The power module
It is connected with above-mentioned each module to power.
Preferably, the gain adjustment circuit includes the ADL5611ARKZ chip and HMC625ALP5E chip being connected；
The external radio-frequency signal is connected after net mate is handled with the ADL5611ARKZ chip；It is described
HMC625ALP5E chip is connected with programmable analog processing chip circuit.
Preferably, the programmable analog processing chip circuit includes AD9371BBCZ chip.
Preferably, the FPGA signal processing circuit includes XC7K325T-2FFG900I chip；The GPP control management
Circuit includes XC7Z020-1CLG484I chip.
Preferably, the clock processing module includes the AD9552 chip and AD9523 chip being connected；The AD9552
Chip connects external timing signal by REF pin, is connected with crystal resonator on the STAL pin of the AD9552 chip；Institute
AD9523 chip is stated to be respectively connected with programmable analog processing chip circuit and the FPGA signal processing circuit.
Preferably, it is provided between the programmable analog processing chip circuit and the gain adjustment circuit for impedance
The transformer of transformation.
Preferably, the programmable analog processing chip circuit is connected with the transformer for impedance transformation to outgoing
Send radiofrequency signal.
Preferably, the software radio general-purpose platform further includes high-speed AD converter circuit；The high speed analog-digital conversion turns
The input of converter circuit is connected with external radio-frequency signal, and output is connected with FPGA signal processing circuit.
Preferably, the software radio general-purpose platform further includes controlling at management circuit and FPGA signal with the GPP
The extension DDR circuit that reason circuit is respectively connected with is to store and runs software radio general-purpose platform program；The extension DDR electricity
Road includes MT41K128M16JT chip.
Preferably, the software radio general-purpose platform further include ethernet interface circuit, video signal interface circuit and
One of usb circuit is a variety of；The GPP control management circuit passes through the ethernet interface circuit, vision signal
Interface circuit and/or usb circuit are connected with the peripheral equipment.
From the above description of the utility model, it can be seen, compared with prior art, the utility model has following beneficial to effect
Fruit:
(1) a kind of software radio general-purpose platform of the utility model, radio frequency processing are designed using zero intermediate frequency, zero intermediate frequency technology
Have the characteristics that small in size, low-power consumption, high reliablity, adapt to current satellite communication and wireless telecom equipment product to it is portable,
The requirement of miniaturization trend；
(2) a kind of software radio general-purpose platform of the utility model, baseband digital signal processing module use GPP+FPGA
(general processor+field programmable logic) mode, GPP can complete the control management of system, upper-layer protocol processing, data biography
The functions such as defeated and human-computer interaction；FPGA mainly completes channel coding/decoding processing, signal except completing hardware capability reconstruct in addition to customization
The digital signal processing algorithms functions such as modulation /demodulation, digital filtering and signal cognitive function；It is set up by the way of combination, it can
Itself speciality of each hardware resource is more preferably played, so that platform allomeric function and performance are optimal, versatility is good；
(3) a kind of software radio general-purpose platform of the utility model, be provided with gigabit ethernet interface, HDMI interface and
The Peripheral Interfaces such as USB interface, favorable expandability；
(4) a kind of software radio general-purpose platform of the utility model supports local reference clock or external clock reference, when
When having external clock access, referred to using external clock；When there is no external clock reference, using local reference clock；
(5) a kind of software radio general-purpose platform of the utility model is externally sending radiofrequency signal or is receiving external radio frequency
Before signal is handled, use net mate processing to remove the reflection generated on transmission link；
(6) a kind of software radio general-purpose platform of the utility model, before handling reception external radio-frequency signal,
Gain adjustment has been carried out to improve performance.
The utility model is described in further detail with reference to the accompanying drawings and embodiments, but one kind of the utility model is soft
Part radio general-purpose platform is not limited to the embodiment.
Detailed description of the invention
Fig. 1 is the overall structure block diagram of the utility model；
Fig. 2 is the reception external radio-frequency signal circuit diagram one of the utility model；
Fig. 3 is the reception external radio-frequency signal circuit diagram two of the utility model；
Fig. 4 is the reception external radio-frequency signal circuit diagram three of the utility model；
Fig. 5 be the utility model transmissions radiofrequency signal to outside circuit diagram；
Fig. 6 is the circuit diagram of the AD9371BBCZ chip of the utility model；
Fig. 7 is the circuit diagram of the AD9552 chip of the utility model；
Fig. 8 is the circuit diagram of the AD9523 chip of the utility model；
Fig. 9 is the schematic diagram of the high-speed AD converter circuit of the utility model；
Figure 10 is the circuit diagram of the DDR memory chip of the utility model；
Figure 11 is the circuit diagram of the gigabit ethernet interface chip of the utility model；
Figure 12 is the circuit diagram of the video signal interface chip of the utility model；
Figure 13 is the circuit diagram of the USB transceiving chip of the utility model.
Specific embodiment
Below by way of specific embodiment, the utility model will be further described.
It is shown in Figure 1, a kind of software radio general-purpose platform of the utility model, comprising: analog signal processing module 1,
Baseband digital signal processing module 2, clock processing module 3 and power module 4；The analog signal processing module 1 includes gain
Adjustment circuit 11 and programmable analog handle chip circuit 12；The baseband digital signal processing module 2 includes at FPGA signal
Manage circuit 21 and GPP control management circuit 22；The gain adjustment circuit 11 is connected to carry out gain with external radio-frequency signal
Adjustment；The programmable analog processing chip circuit 12 is connected with the gain adjustment circuit 11 to radiofrequency signal adjusted
It is handled；GPP control management circuit 22 and the FPGA signal processing circuit 21 and peripheral equipment 5 be respectively connected with
Complete base band signal process；The FPGA signal processing circuit 21 and the programmable analog processing chip circuit 12 be connected with
Chip circuit 12, which is handled, by the programmable analog externally sends or receives radiofrequency signal；The clock processing module 3 and institute
It states programmable analog processing chip circuit 12 and the FPGA signal processing circuit 21 is respectively connected with to send treated clock
Signal, the clock signal include external timing signal or local clock pulses；The power module 4 is connected with above-mentioned each module
It connects to power.
Referring to fig. 2 to shown in Fig. 4, the gain adjustment circuit 11 include the ADL5611ARKZ chip being connected and
HMC625ALP5E chip；The external radio-frequency signal is connected after net mate is handled with the ADL5611ARKZ chip；
The HMC625ALP5E chip is connected with programmable analog processing chip circuit 12.
Specifically, shown in Figure 2, the net mate processing circuit includes resistance R1, resistance R11, resistance R21 and electricity
Hold C1.The RF0_RX1 of circuit output as shown in Figure 2, which is exported to programmable analog, handles chip circuit.
It is inputted corresponding to another way, if Fig. 2 and Fig. 3 circuit diagram formed includes power splitter EP2W1+ to generate
RF0_SNRXC signal, the 15th pin of the power splitter EP2W1+ export to programmable analog and handle chip circuit.
It is inputted corresponding to another way, the circuit evolving RF0_ORX2 signal formed such as Fig. 2, Fig. 3 and Fig. 4 is to export to can compile
Journey simulation process chip circuit.
It is shown in Figure 5, after the RF0_TX1 signal that programmable analog handles chip circuit output carries out net mate processing
It is sent to outside.
Shown in Figure 6, the programmable analog processing chip circuit includes AD9371BBCZ chip.
The FPGA signal processing circuit includes XC7K325T-2FFG900I chip；The GPP control manages circuit and includes
XC7Z020-1CLG484I chip.
AD9371BBCZ is a high-performance, broadband, integrated form RF transceiver, is applied designed for RF, such as the base station 4G,
Test and measure application and software-defined radio etc..The design completes analog signal processing unit point using AD9371 chip
Functions, the high integration such as function, including radio-frequency front-end processing, Up/Down Conversion, filtering, gain adjustment and AD/DA also bring body
The advantage of product, the aspect of power consumption, while simplifying system design.
AD9371BBCZ chip include double passage differential receiver (Rx), 2 input observation receivers (ORx), 3 it is defeated
The sniffer receiver (SnRx) entered further includes double passage differential transmitter to receive external radio-frequency signal (referring to fig. 2-4)
(Tx) externally to send radiofrequency signal (referring to Fig. 5).The range of input signal is 0.3GHz~6GHz；Tx synthetic bandwidth (BW) is
250MHz；Rx bandwidth is 8MHz~100MHz.
In addition, AD9371BBCZ chip supports frequency division duplex (FDD) and time division duplex (TDD) operating mode；It is fully-integrated
Independent fractional frequency division radio frequency, generated for receiving and dispatching local oscillator and clock.
AD9371BBCZ chip can facilitate the processing function of customization simulation signal processing by SPI and GPIO interface,
Including the configuration of radio-frequency front-end processing parameter, Up/Down Conversion, channel filtering bandwidth and model selection, gain adjustment (support manually or
Automatically (AGC)).AD9371BBCZ chip interior integrates ARM and handles core, and dynamic monitoring adjusts orthogonal frequency conversion parameter, including mirror
As inhibiting, the critical performance parameters such as direct current correction, to ensure the performance of orthogonal frequency-variable module.
AD9371BBCZ chip integrates ADC and DAC module simultaneously.The base-band analog signal of quadrature frequency conversion is sampled through ADC
After the completion of the XC7K325T-2FFG900I chip for sending the FPGA signal processing circuit after quantization by JESD204B digital interface
Continuous processing.The digital baseband signal completed is handled by JESD204B digital interface through DAC through the FPGA signal processing circuit
It is converted into after analog baseband signal supervention after the completion of serving frequency conversion and send processing work.Specifically, AD9371BBCZ chip has 3
JESD204B interface, communication speed reach as high as 6144Mbps, wherein 1 is used for receiving channel, come from antenna reception
Radiofrequency signal is downconverted, after filtering and AD conversion and relevant treatment, passes through JESD204B and the FPGA signal processing circuit
Docking；Another 1 user's transmission channel receives the number that need to be sent from the FPGA signal processing circuit by JESD204B and believes
Number, amplify, correct, convert and amplify and the processing such as up-conversion after, launch through external antenna.
In the present embodiment, baseband digital signal processing module uses ARM+FPGA framework, utilizes match company, Sentos Zynq
(XC7Z020)+FPGA (XC7K325) is realized.This two chip undertakes system control management function (control administrative unit) respectively
And signal processing algorithm function (signal processing unit).
Zynq integrates double-core ARM (cortex-A9), there is Peripheral Interface abundant, at the same be also equipped with fpga logic algorithm with
Hardware customized extension function.
Zynq-7000SoC family chip has the software programmable of arm processor and the hardware programmable of FPGA,
It can not only realize important analysis and hardware-accelerated, while highly integrated CPU, DSP and mixed signal function also on individual devices
Energy.Double-core Zynq-7000 device is the highest comprehensive expansible SoC platform of unit work consumptiom cost performance, can sufficiently meet software
Custom-built system application demand.
Zynq (XC7Z020) Specifeca tion speeification is as follows:
Double-core ARM Cortex-A9, processing speed are up to 1GHz；
Programmable logic cells: 125K, block RAM: 9.3Mb, DSP piece: 400
DDR3 rate: 800MHz.
Kintex-7FPGA is that optimum cost/performance/power-consumption balance is realized in design, while providing high-speed DSP and height
Cost performance encapsulation, and support the mainstream standards such as PCIe-Gen3 and 10Gigabit Ethernet.Kintex-7 series is 3G/4G
Wirelessly, the ideal chose of the applications such as flat-panel monitor and video over IP solution.
The design selects FPGA (XC7K325) chip, main resource and characteristic:
Logic unit: 326080；
DSP module: 840；
GTX transceiver: 16, supporting rate 12.5Gb/s；
RAM storage: distributed RAM, 4Mbit；Block RAM (36Kbit/ block), 445 pieces；
I/O pin: 500；
FPGA (XC7K325) undertakes platform digital signal processing unit function, other than can be with software customized hardware interface,
The function algorithms such as channel coding/decoding processing, modulating and demodulating signal, digital filtering, signal cognition, signal generation are completed emphatically.
FPGA (XC7K325) resource abundant and powerful performance, can satisfy the requirement of current high speed, the Wideband Signal Processing.This reality
It applies in example, the M6/M8 of AD9371BBCZ chip D20A is to emit enabled foot, and M5/M7 is to receive enabled foot, with XC7K325T-
The enable signal of 2FFG900I chip is connected；The A9/A10 of D20A is 1 input pin of receiving channel, and RF0_RX1 leg signal is logical
It crosses after the transformer processing for impedance transformation and is connected with A9/A10；The A5/A6 of D20A is the input pin of receiving channel 2, even
Connect another way input radio frequency signal；The J14/H14 of D20A is 1 output pin of transmission channel, and output signal is passed through by for hindering
It is connected after the transformer processing that resistance changes with RF0_TX1 pin to launch；The A2/A23 of D20A is the defeated of observation receiver 2
Enter pin, RF0_ORX2 leg signal is connected after handling by the transformer converted for impedance with A2/A23；The D2/E2 of D20A
For the input pin of sniffer receiver 3, RF0_SNRXC pin messenger cross after the transformer processing for impedance transformation with
A2/A23 is connected；In addition, the LVDS differential clock signal that the K3/K4 of D20A is JESD204B inputs；L3/L4, M3/M4 of D20A
For JESD204B LVDS synchronization signal relevant to channel reception data, it is connected with XC7K325T-2FFG900I chip；D20A's
P4/P5, P6/P7, N3/N4, N5/N6 are the output of JESD204B radio-frequency current mode differential, with XC7K325T-2FFG900I chip
It is connected；P11/P12, P13/P14, N10/N11, N12/N13 of D20A is the input of JESD204B radio-frequency current mode differential, with
XC7K325T-2FFG900I chip is connected.
Shown in referring to figs. 7 and 8, the clock processing module includes the AD9552 chip and AD9523 chip being connected；
The AD9552 chip connects external timing signal by REF pin, is connected with crystalline substance on the STAL pin of the AD9552 chip
Body resonator；The AD9523 chip and programmable analog processing chip circuit and the FPGA signal processing circuit are distinguished
It is connected.
Specifically, 22 pins of the AD9552 chip D77 are connected with 4 pins of AD9523 chip D70；The 23 of D77
Pin is connected with 3 pins of D70；26 pins of D77 are connected with 10 pins of D70；27 pins of D77 and 9 pins of D70
It is connected.58/59 pin of D70 is connected with the E7/E8 pin of AD9371BBCZ chip；31/32 pin of D70 with
The E7/E8 pin of XC7K325T-2FFG900I chip is connected；28/29 pin of D70 with
The E7/E8 pin of XC7Z020-1CLG484I chip is connected.
Shown in Figure 9, the software radio general-purpose platform further includes high-speed AD converter circuit；The high speed mould
The input of number converter circuit is connected with external radio-frequency signal, and output is connected with FPGA signal processing circuit；The height
Fast analog-digital converter circuit includes AD9680BCPZ-500 chip, to meet the analog-to-digital conversion requirement of higher precision.Specifically,
22/23/24/25/26/27/28/29 pin of AD9680BCPZ-500 chip is exported to XC7K325T-
2FFG900I chip.
Shown in Figure 10, the software radio general-purpose platform further includes controlling management circuit and FPGA with the GPP
The extension DDR circuit that signal processing circuit is respectively connected with is to store and runs software radio general-purpose platform program；The expansion
Opening up DDR circuit includes MT41K128M16JT chip.
Referring to shown in Figure 11 to Figure 13, the software radio general-purpose platform further includes ethernet interface circuit, video letter
One of number interface circuit and usb circuit are a variety of；The XC7Z020-1CLG484I core of the GPP control management circuit
Piece is connected by the ethernet interface circuit, video signal interface circuit and/or usb circuit with the peripheral equipment
It connects；The too network interface circuit includes 88E1111 chip；The video signal interface circuit includes ADV7511W chip；It is described
Usb circuit includes USB3320 chip.
The above is only the specific embodiments of the present invention, but the design concept of the present invention is not limited thereto,
All non-essential modifications to the present invention made by this concept should belong to the row for invading scope of protection of the utility model
For.
Claims (10)
1. a kind of software radio general-purpose platform characterized by comprising at analog signal processing module, baseband digital signal
Manage module, clock processing module and power module；The analog signal processing module includes gain adjustment circuit and programmable mould
Quasi- processing chip circuit；The baseband digital signal processing module includes FPGA signal processing circuit and GPP control management circuit；
The gain adjustment circuit is connected to carry out gain adjustment with external radio-frequency signal；The programmable analog handles chip circuit
It is connected with the gain adjustment circuit and radiofrequency signal adjusted is handled；GPP control management circuit with it is described
FPGA signal processing circuit and peripheral equipment are respectively connected with to complete base band signal process；The FPGA signal processing circuit with
The programmable analog processing chip circuit is connected to handle chip circuit by the programmable analog and externally send or connect
Receive radiofrequency signal；The clock processing module and programmable analog processing chip circuit and the FPGA signal processing circuit
It is respectively connected with to send treated clock signal, the clock signal includes external timing signal or local clock pulses；Institute
Power module is stated to be connected with above-mentioned each module to power.
2. software radio general-purpose platform according to claim 1, which is characterized in that the gain adjustment circuit includes phase
The ADL5611ARKZ chip and HMC625ALP5E chip of connection；The external radio-frequency signal after net mate is handled with it is described
ADL5611ARKZ chip is connected；The HMC625ALP5E chip is connected with programmable analog processing chip circuit.
3. software radio general-purpose platform according to claim 1, which is characterized in that the programmable analog handles chip
Circuit includes AD9371BBCZ chip.
4. software radio general-purpose platform according to claim 1, which is characterized in that the FPGA signal processing circuit packet
Include XC7K325T-2FFG900I chip；The GPP control management circuit includes XC7Z020-1CLG484I chip.
5. software radio general-purpose platform according to claim 1, which is characterized in that the clock processing module includes phase
The AD9552 chip and AD9523 chip of connection；The AD9552 chip connects external timing signal by REF pin, described
Crystal resonator is connected on the STAL pin of AD9552 chip；The AD9523 chip and the programmable analog handle chip
Circuit and the FPGA signal processing circuit are respectively connected with.
6. software radio general-purpose platform according to claim 1, which is characterized in that the programmable analog handles chip
The transformer for impedance transformation is provided between circuit and the gain adjustment circuit.
7. software radio general-purpose platform according to claim 1, which is characterized in that the programmable analog handles chip
Circuit is connected with the transformer for impedance transformation externally to send radiofrequency signal.
8. software radio general-purpose platform according to claim 1, which is characterized in that the software radio general-purpose platform
It further include high-speed AD converter circuit；The input of the high-speed AD converter circuit is connected with external radio-frequency signal,
Output is connected with FPGA signal processing circuit.
9. software radio general-purpose platform according to claim 1, which is characterized in that the software radio general-purpose platform
Further include control management circuit and the extension DDR circuit that is respectively connected with of FPGA signal processing circuit with the GPP to store and
Runs software radio general-purpose platform program；The extension DDR circuit includes MT41K128M16JT chip.
10. software radio general-purpose platform according to claim 1, which is characterized in that the software radio is general flat
Platform further includes one of ethernet interface circuit, video signal interface circuit and usb circuit or a variety of；The GPP control
Tubulation reason circuit is set by the ethernet interface circuit, video signal interface circuit and/or usb circuit with the periphery
It is standby to be connected.
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| CN201920243060.4U CN209330095U (en) | 2019-02-26 | 2019-02-26 | A kind of software radio general-purpose platform |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111182660A (en) * | 2019-12-31 | 2020-05-19 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Interactive wireless communication system based on general processor and ZYNQ processor |
| CN111884966A (en) * | 2020-07-20 | 2020-11-03 | 贵州航天天马机电科技有限公司 | Modulation-demodulation circuit based on GMSK technology |
-
2019
- 2019-02-26 CN CN201920243060.4U patent/CN209330095U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111182660A (en) * | 2019-12-31 | 2020-05-19 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Interactive wireless communication system based on general processor and ZYNQ processor |
| CN111884966A (en) * | 2020-07-20 | 2020-11-03 | 贵州航天天马机电科技有限公司 | Modulation-demodulation circuit based on GMSK technology |
| CN111884966B (en) * | 2020-07-20 | 2022-11-04 | 贵州航天天马机电科技有限公司 | Modulation-demodulation circuit based on GMSK technology |
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