CN209086918U - One kind supporting CPU network interface and serial communication circuit based on IDC - Google Patents
One kind supporting CPU network interface and serial communication circuit based on IDC Download PDFInfo
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- CN209086918U CN209086918U CN201821917103.4U CN201821917103U CN209086918U CN 209086918 U CN209086918 U CN 209086918U CN 201821917103 U CN201821917103 U CN 201821917103U CN 209086918 U CN209086918 U CN 209086918U
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Abstract
The utility model supports CPU network interface and serial communication circuit based on IDC, including AU circuit board in GSM_R digital optical fiber repeater system and RU circuit board, AU circuit board is connected with RU circuit board by digital fiber, it is characterized by: being provided with IDC10 connector, CPU numerical control system on AU circuit board and RU circuit board, IDC10 connector is connected with the signal wire of CPU numerical control system, power and ground；An individual debugging circuit board is separately set, the network interface and serial communication of external debugging device and AU circuit board and RU circuit board is realized, has on the debugging circuit board equipped with IDC10 connector, DB9 and RJ45 interface, network port driving chip and serial port drive chip.Network port driving chip, serial port drive chip, RJ45 connector and DB9 connector are just saved by this design scheme, on the main circuit board of AU and RU, can reduce the production cost of product.
Description
Technical field
The present invention relates to one kind to be based on insulation displacement connector (IDC, Insulation Displacement
Connector central processing unit (CPU, Central Processing Unit) network interface and serial communication circuit) are supported, especially
It is related to a kind of GSM_R (Global System for Mobile Communications-Railway) digital optical fiber direct station
The communication of middle CPU and external debugging device.
Background technique
GSM_R digital optical fiber repeater system is by two radio frequency units of AU (Access unit) and RU (Remote unit)
Composition, AU are connected with RU by digital fiber.AU is connected to RRU (Radio Remote Unit) radio frequency output port of GSM_R,
RU emits radiofrequency signal and realizes signal covering to antenna.Main control unit in AU and RU radio frequency unit is CPU, and CPU is mainly controlled
The normal work of entire signal link.Research and development and debugging maintenance stage in GSM_R system, commissioning device need through network interface or
Person's serial ports is communicated with the CPU in GSM_R system, is debugged and is upgraded to system.
Asynchronous serial refers to UART (Universal Asynchronous Receiver/Transmitter), general different
Walk reception/transmission.UART is the chip that a parallel input becomes Serial output, is generally integrated on mainboard.UART includes TTL
The serial ports of level and the serial ports of RS232 level.Transistor-Transistor Logic level is 3.3V, and RS232 is negative logic level, its definition+5~+
12V is low level, and -12~-5V is high level, and MDS2710, MDS SD4, EL805 etc. are RS232 interfaces, and EL806 has TTL
Interface.Serial line interface is divided including RS-232-C, RS-422, RS485 etc. by electrical standard and agreement.RS-232-C,RS-422
Regulation only is made to the electrical characteristic of interface with RS-485 standard, is not related to connector, cable or agreement.
RS-232 is also referred to as standard serial port, a kind of most common serial communication interface.It is in 1970 by American Electronic work
What industry association (EIA) joint Bell System, modem producer and terminal manufacturer formulated jointly is used for serial
The standard of communication.Its full name is " SERIAL BINARY DATA between data terminal equipment (DTE) and data communications equipment (DCE)
Fabric Interface technical standard ".Traditional RS-232-C interface standard has 22 lines, using 25 core D type connector assembly (DB25) of standard,
Later use is reduced to 9 core D type sockets (DB9), and now 25 core plug seats seldom use in the application.
R-45 interface be exactly we now the most common network device interface, be commonly called as " crystal head ", technical term RJ-45
Connector belongs to twisted-pair Ethernet interface type.RJ-45 plug can only be inserted into along fixed-direction, be equipped with a plastic shrapnel
It blocks with RJ-45 slot and is fallen to prevent anti-avulsion.This interface is in 10Base-T Ethernet, 100Base-TX Ethernet, 1000Base-
It can be used in TX Ethernet, transmission medium is all twisted pair, but also has different want to medium according to the difference of bandwidth
It asks, when especially 1000Base-TX gigabit Ethernet connects, at least to use CAT5E UTP cable, it is ensured that gone back if stablizing high speed
To use 6 class lines.
Summary of the invention
In traditional Design of Digital Circuit based on CPU, the driving chip of network interface and serial ports is designed together with CPU
In main control board, as shown in Figure 1.In this design, each piece of AU and RU equipment of production requires serial port drive core
Piece, network port driving chip, RJ45 connector and DB9 connector.Aiming at the problems existing in the prior art, the present invention is connected using IDC10
It connects 10 in device pins and redefines circuit connection between CPU and network port driving chip and serial port drive chip, network interface
Driving chip, serial port drive chip, RJ45 interface and DB9 interface are individually designed on a debugging circuit board.It is set by this
Network port driving chip, serial port drive chip, RJ45 connector and DB9 connector are just saved on the main circuit board of meter scheme, AU and RU,
The production cost of product can be reduced.During research and development debugging and on-site technical support, research and development engineer and after sale skill are given
Art support engineer, which provides the debugging circuit board that the certain amount present invention designs, can normally complete work.
In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention are as follows: one kind based on IDC support CPU network interface and
AU circuit board and RU circuit board in serial communication circuit, including GSM_R digital optical fiber repeater system, AU circuit board and RU circuit
Plate is connected by digital fiber, and IDC10 connector, CPU numerical control system are provided on AU circuit board and RU circuit board,
IDC10 connector is connected with the signal wire of CPU numerical control system, power and ground, and 10 pins of IDC10 connector connect
It is as follows to connect mode:
The pin 1 of IDC10 is connected to the power supply line VDD of CPU numerical control system；
The pin 2 of IDC10 is connected to the serial ports transmitting signal wire CPU_TX of CPU numerical control system；
The serial ports that the pin 3 of IDC10 is connected to CPU numerical control system receives signal wire CPU_RX；
The pin 4 of IDC10 is connected to the ground wire GND of CPU numerical control system；
The pin 5 of IDC10 is connected to the network interface signal MDI0_P of CPU numerical control system；
The pin 6 of IDC10 is connected to the network interface signal MDI0_N of CPU numerical control system；
The pin 7 of IDC10 is connected to the network interface signal MDI1_P of CPU numerical control system；
The pin 8 of IDC10 is connected to the network interface signal MDI1_N of CPU numerical control system；
The pin 9 of IDC10 is connected to the LED light control signal wire LED0 of CPU numerical control system；
The pin 10 of IDC10 is connected to the LED light control signal wire LED1 of CPU numerical control system.
The utility model supports CPU network interface and serial communication circuit based on IDC, separately adds an individually debugging electricity
Road plate (Debug Board) realizes the network interface and serial communication of external debugging device and AU and RU, the debugging circuit board
Have on (Debug Board) equipped with IDC10 connector, DB9 and RJ45 interface, network port driving chip and serial port drive chip, tool
Body connection type is as follows:
The pin 2 of DB9 interface is connected to the pin 14 of serial port drive chip；
The pin 3 of DB9 interface is connected to the pin 13 of serial port drive chip；
The specific connection type of the signal wire of serial port drive chip and IDC10 interface is as follows:
The pin 16 of serial port drive chip is connected to the power supply line of IDC10 pin 1；
The pin 11 of serial port drive chip is connected to the serial ports transmitting signal wire of IDC10 pin 2；
The serial ports that the pin 12 of serial port drive chip is connected to IDC10 pin 3 receives signal wire；
The pin 15 of serial port drive chip is connected to the debugging board of IDC10 pin 4 and the total ground wire of RU；
The connection type of RJ45 network interface interface and network port driving chip is as follows:
The pin 1 of RJ45 is connected to the pin 16 of network port driving chip；
The pin 2 of RJ45 is connected to the pin 14 of network port driving chip；
The pin 3 of RJ45 is connected to the pin 11 of network port driving chip；
The pin 6 of RJ45 is connected to the pin 9 of network port driving chip；
The pin of network port driving chip and the pin connection type of IDC10 are as follows:
The pin 1 of network port driving chip is connected to the pin 5 of IDC10；
The pin 3 of network port driving chip is connected to the pin 6 of IDC10；
The pin 6 of network port driving chip is connected to the pin 7 of IDC10；
The pin 8 of network port driving chip is connected to the pin 8 of IDC10；
The G1 and G2 of RJ45 are connected to the ground wire of debugging circuit board；
The pin 10,12 of RJ45 is connected to the power bus VDD of debugging circuit board, to two LED power supplies；
The pin 9,11 of RJ45 is connected to the pin 9 and pin 10 of IDC10, is connected to the digital control system of CPU by bus
System.
The serial port drive chip is using MAX3232 chip, and the network port driving chip is using H1102NLS
Chip.
Beneficial effect, 2 advantages of the utility model:
1, the utility model newly designs an IDC10 connector in the circuit board of AU and RU, while realizing CPU network interface and string
The communication of mouth and commissioning device.Serial port drive chip, network port driving chip, one are saved on the main circuit board of AU and RU
The peripheral component of RJ45 and DB9 connector and serial ports and network port driving chip, reduces answering for PCB printed circuit board
Miscellaneous degree, and reduce board area, the production cost of PCB printed circuit can be reduced.
2, during AU and RU equipment works normally, CPU is not needed in real time and external device communication, therefore is ground
Hair personnel and technical support personnel, which are equipped with a certain number of debugging circuit boards, can meet the needs of work, it is therefore desirable to tune
Examination circuit board quantity is far smaller than the sales volume of AU and RU equipment.Each AU and RU equipment can reduce by a RJ45, and one
DB9, the buying of a network port driving chip and a serial port drive chip, therefore adopted by the invention it is possible to further decrease
Purchase and production cost.
Detailed description of the invention
Fig. 1 is traditional Design of Digital Circuit figure based on CPU in the prior art.
Fig. 2 is the IDC10 connector circuit design drawing on the RU circuit board of the utility model.
Fig. 3 is the circuit design drawing of the debugging circuit board (Debug Board) of the utility model.
Specific embodiment
The utility model is described in further detail below in conjunction with the drawings and specific embodiments.
In the principle diagram design of AU and RU, the signal of an IDC10 connector and CPU numerical control system is newly increased
Line, power and ground are connected.As shown in Fig. 2, on newly-designed RU circuit board, the 10 pin definition of IDC10 connector
It is as follows:
The pin 1 of IDC10 is connected to the power supply line VDD of CPU numerical control system,
The pin 2 of IDC10 is connected to the serial ports transmitting signal wire CPU_TX of CPU numerical control system,
The serial ports that the pin 3 of IDC10 is connected to CPU numerical control system receives signal wire CPU_RX,
The pin 4 of IDC10 is connected to the ground wire GND of CPU numerical control system,
The pin 5 of IDC10 is connected to the network interface signal MDI0_P of CPU numerical control system,
The pin 6 of IDC10 is connected to the network interface signal MDI0_N of CPU numerical control system,
The pin 7 of IDC10 is connected to the network interface signal MDI1_P of CPU numerical control system,
The pin 8 of IDC10 is connected to the network interface signal MDI1_N of CPU numerical control system,
The pin 9 of IDC10 is connected to the LED light control signal wire LED0 of CPU numerical control system,
The pin 10 of IDC10 is connected to the LED light control signal wire LED1 of CPU numerical control system.
Because this IDC10 interface definition on AU and RU circuit board is not a standard agreement, new design is needed
One debugging circuit board (Debug Board) realizes the network interface and serial communication of external debugging device and AU and RU.Debug circuit
The design frame chart of plate is as shown in figure 3, serial port drive chip is using MAX3232 chip, network port driving in the present example
Chip is using H1102NLS chip.
The implementation concrete mode of this debugging circuit board is as follows:
1: having IDC10, DB9 and RJ45 interface on this Debug Board, while network port driving chip and serial ports are driven
Dynamic chip design is on Debug Board；
The pin 2 of 2:DB9 interface is connected to the pin 14 of serial port drive chip (MAX3232),
The pin 3 of DB9 interface is connected to the pin 13 of serial port drive chip (MAX3232)；
3: the specific connection type of the signal wire of serial port drive chip and IDC10 interface is as follows:
The pin 16 of serial port drive chip (MAX3232) is connected to the pin 1 of IDC10, this is power supply line；
The pin 11 of serial port drive chip (MAX3232) is connected to the pin 2 of IDC10, this serial ports emits signal wire；
The pin 12 of serial port drive chip (MAX3232) is connected to the pin 3 of IDC10, this serial ports receives signal wire；
The pin 15 of serial port drive chip (MAX3232) is connected to the pin 4 of IDC10, this is being total to for debugging board and RU
Ground wire；
The connection type of 4:RJ45 network interface interface and network port driving chip is as follows:
The pin 1 of RJ45 is connected to the pin 16 of network port driving chip；
The pin 2 of RJ45 is connected to the pin 14 of network port driving chip；
The pin 3 of RJ45 is connected to the pin 11 of network port driving chip；
The pin 6 of RJ45 is connected to the pin 9 of network port driving chip；
5: the pin of network port driving chip and the pin connection type of IDC10 are as follows:
The pin 1 of network port driving chip is connected to the pin 5 of IDC10；
The pin 3 of network port driving chip is connected to the pin 6 of IDC10；
The pin 6 of network port driving chip is connected to the pin 7 of IDC10；
The pin 8 of network port driving chip is connected to the pin 8 of IDC10；
The G1 and G2 of 6:RJ45 are connected to the ground wire of debugging circuit board；
The pin 10,12 of 7:RJ45 is connected to the power bus VDD of debugging circuit board, to two LED power supplies；
The pin 9,11 of 8:RJ45 is connected to the pin 9 and pin 10 of IDC10, and it is digital control to be connected to CPU by bus
System.
Above embodiment is merely illustrative of the invention's technical idea, and this does not limit the scope of protection of the present invention, all
It is any changes made on the basis of the technical scheme according to the technical idea provided by the invention, each falls within present invention protection model
Within enclosing.The technology that the present invention is not directed to can be realized by existing technology.
Claims (4)
1. one kind supports AU electricity in CPU network interface and serial communication circuit, including GSM_R digital optical fiber repeater system based on IDC
Road plate and RU circuit board, AU circuit board and RU circuit board are connected by digital fiber, it is characterised in that: in AU circuit board and RU circuit
IDC10 connector, CPU numerical control system, signal wire, the electricity of IDC10 connector and CPU numerical control system are provided on plate
Source line is connected with ground wire.
2. according to claim 1 support CPU network interface and serial communication circuit based on IDC, it is characterised in that: separately add
One individual debugging circuit board (Debug Board) realizes the network interface of external debugging device and AU circuit board and RU circuit board
And serial communication, have equipped with IDC10 connector, DB9 and RJ45 interface, network interface on the debugging circuit board (Debug Board)
Driving chip and serial port drive chip, specific connection type are as follows:
The pin 2 of DB9 interface is connected to the pin 14 of serial port drive chip；
The pin 3 of DB9 interface is connected to the pin 13 of serial port drive chip；
The specific connection type of the signal wire of serial port drive chip and IDC10 interface is as follows:
The pin 16 of serial port drive chip is connected to the power supply line of IDC10 pin 1；
The pin 11 of serial port drive chip is connected to the serial ports transmitting signal wire of IDC10 pin 2；
The serial ports that the pin 12 of serial port drive chip is connected to IDC10 pin 3 receives signal wire；
The pin 15 of serial port drive chip is connected to the debugging board of IDC10 pin 4 and the total ground wire of RU；
The connection type of RJ45 network interface interface and network port driving chip is as follows:
The pin 1 of RJ45 is connected to the pin 16 of network port driving chip；
The pin 2 of RJ45 is connected to the pin 14 of network port driving chip；
The pin 3 of RJ45 is connected to the pin 11 of network port driving chip；
The pin 6 of RJ45 is connected to the pin 9 of network port driving chip；
The pin of network port driving chip and the pin connection type of IDC10 are as follows:
The pin 1 of network port driving chip is connected to the pin 5 of IDC10；
The pin 3 of network port driving chip is connected to the pin 6 of IDC10；
The pin 6 of network port driving chip is connected to the pin 7 of IDC10；
The pin 8 of network port driving chip is connected to the pin 8 of IDC10；
The G1 and G2 of RJ45 are connected to the ground wire of debugging circuit board；
The pin 10,12 of RJ45 is connected to the power bus VDD of debugging circuit board, to two LED power supplies；
The pin 9,11 of RJ45 is connected to the pin 9 and pin 10 of IDC10, is connected to CPU numerical control system by bus.
3. according to claim 2 support CPU network interface and serial communication circuit based on IDC, it is characterised in that: RU circuit
On plate, 10 pin connection types of IDC10 connector are as follows:
The pin 1 of IDC10 is connected to the power supply line VDD of CPU numerical control system；
The pin 2 of IDC10 is connected to the serial ports transmitting signal wire CPU_TX of CPU numerical control system；
The serial ports that the pin 3 of IDC10 is connected to CPU numerical control system receives signal wire CPU_RX；
The pin 4 of IDC10 is connected to the ground wire GND of CPU numerical control system；
The pin 5 of IDC10 is connected to the network interface signal MDI0_P of CPU numerical control system；
The pin 6 of IDC10 is connected to the network interface signal MDI0_N of CPU numerical control system；
The pin 7 of IDC10 is connected to the network interface signal MDI1_P of CPU numerical control system；
The pin 8 of IDC10 is connected to the network interface signal MDI1_N of CPU numerical control system；
The pin 9 of IDC10 is connected to the LED light control signal wire LED0 of CPU numerical control system；
The pin 10 of IDC10 is connected to the LED light control signal wire LED1 of CPU numerical control system.
4. according to claim 3 support CPU network interface and serial communication circuit based on IDC, it is characterised in that: the serial ports
Driving chip is using MAX3232 chip, and the network port driving chip is using H1102NLS chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821917103.4U CN209086918U (en) | 2018-11-21 | 2018-11-21 | One kind supporting CPU network interface and serial communication circuit based on IDC |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821917103.4U CN209086918U (en) | 2018-11-21 | 2018-11-21 | One kind supporting CPU network interface and serial communication circuit based on IDC |
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| CN209086918U true CN209086918U (en) | 2019-07-09 |
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| CN201821917103.4U Active CN209086918U (en) | 2018-11-21 | 2018-11-21 | One kind supporting CPU network interface and serial communication circuit based on IDC |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113326218A (en) * | 2021-05-18 | 2021-08-31 | 中国科学院计算技术研究所 | Communication and debugging equipment circuit and embedded intelligent computing system applying same |
-
2018
- 2018-11-21 CN CN201821917103.4U patent/CN209086918U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113326218A (en) * | 2021-05-18 | 2021-08-31 | 中国科学院计算技术研究所 | Communication and debugging equipment circuit and embedded intelligent computing system applying same |
| CN113326218B (en) * | 2021-05-18 | 2023-08-18 | 中国科学院计算技术研究所 | Communication and debugging equipment circuit and embedded intelligent computing system using same |
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Legal Events
| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A Communication Circuit Based on IDC Supporting CPU Network Port and Serial Port Effective date of registration: 20221118 Granted publication date: 20190709 Pledgee: Nanjing Bank Co.,Ltd. Nanjing Financial City Branch Pledgor: NANJING DIGITGATE TECHNOLOGY Co.,Ltd. Registration number: Y2022980022303 |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20231025 Granted publication date: 20190709 Pledgee: Nanjing Bank Co.,Ltd. Nanjing Financial City Branch Pledgor: NANJING DIGITGATE TECHNOLOGY Co.,Ltd. Registration number: Y2022980022303 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A Communication Circuit Based on IDC Supporting CPU Network and Serial Ports Effective date of registration: 20231123 Granted publication date: 20190709 Pledgee: Nanjing Bank Co.,Ltd. Nanjing Financial City Branch Pledgor: NANJING DIGITGATE TECHNOLOGY Co.,Ltd. Registration number: Y2023980066973 |