CN209071320U - Semiconductor devices and packaging part - Google Patents

Abstract

The utility model technical field of semiconductors proposes a kind of semiconductor devices, which includes stacked structure and electrode；Stacked structure contains at least one chip；Electrode is located at the side surface of stacked structure, and length of the electrode in chip thickness direction is greater than or equal to the thickness of chip.The semiconductor devices avoids connecting using microprotrusion, and the thickness of stacked structure is thinned, is advantageously implemented slimming.Electrode is set to the side surface of stacked structure, it is not necessary to need not consider reserved link position when junction is arranged in wiring layer, designs circuit, not will cause the limitation of on-chip circuitry layout setting.Length of the electrode in chip thickness direction is greater than or equal to the thickness of chip, convenient for connecting the circuit on multiple chips.

Description

Semiconductor devices and packaging part

Technical field

The utility model relates to technical field of semiconductors more particularly to a kind of semiconductor devices and there is the semiconductor devices Packaging part.

Background technique

High capacity, slimming memory increasingly by market favor.

The attachment structure schematic diagram of chip stack poststack in the prior art shown in referring to Fig.1；Existing 1 heap poststack of chip is logical It crosses silicon perforation 2 and microprotrusion 3 connects, in order to have preferable welding effect and conductive capability, need to increase the ruler of microprotrusion 3 Limitation that is very little, causing circuit layout to be arranged cannot preferably realize high capacity, slimming.Existing memory is due to effectively dissipating Can not increasing for heat area, can not preferably accomplish higher capacity.And encapsulating structure is by the length and width of chip 1 due to being limited, It cannot preferably accomplish to be thinned.

Therefore, it is necessary to study a kind of semiconductor devices and with the packaging part of the semiconductor devices.

Above- mentioned information disclosed in the background technology part are only used for reinforcing the understanding to the background of the utility model, therefore It may include the information not constituted to the prior art known to persons of ordinary skill in the art.

Utility model content

The purpose of the utility model is to overcome the deficiencies for being not easy to realize high capacity, slimming of the above-mentioned prior art, mention It is easier to realize high capacity, the semiconductor devices of slimming and with the packaging part of the semiconductor devices for a kind of.

The additional aspect and advantage of the utility model will be set forth in part in the description, and partly will be from retouching It is apparent from stating, or the practice acquistion of the utility model can be passed through.

According to one aspect of the disclosure, a kind of semiconductor devices is provided, comprising:

Stacked structure contains at least one chip；

Electrode, positioned at the side surface of the stacked structure, length of the electrode in the chip thickness direction be greater than or Equal to the thickness of the chip.

In a kind of exemplary embodiment of the disclosure, the semiconductor devices further include:

Wiring layer is set on the chip, wherein the wiring layer is provided with multiple signal ends, multiple signal ends It is electrically connected by the wiring layer with the electrode.

In a kind of exemplary embodiment of the disclosure, the stacked structure includes:

First chip；

Second chip is set on first chip.

In a kind of exemplary embodiment of the disclosure, first chip is equipped with the first wiring layer, second core On piece is equipped with the second wiring layer, first wiring layer and second wiring layer and is electrically connected by silicon perforation.

In a kind of exemplary embodiment of the disclosure, the electrode is electrically connected to first wiring layer, described second One or more of wiring layer.

In a kind of exemplary embodiment of the disclosure, it is arranged jagged on the chip, the electrode is arranged described In notch.

In a kind of exemplary embodiment of the disclosure, the semiconductor devices further include: convex block, set on the electrode One side far from the chip, the convex block protrude from the notch.

In a kind of exemplary embodiment of the disclosure, the convex block covers the electrode and the electrode and the cloth The junction of line layer.

According to one aspect of the disclosure, a kind of packaging part is provided, comprising:

Semiconductor devices described in above-mentioned any one；

Package substrate is electrically connected set on the side surface of the stacked structure, and with the electrode.

In a kind of exemplary embodiment of the disclosure, the packaging part further include:

Encapsulating film, set on the surface of the not set package substrate of the stacked structure.

As shown from the above technical solution, the utility model has at least one of following advantages and good effect:

The semiconductor devices of the utility model, including the stacked structure that at least one chip is formed, electrode, which is located at, stacks knot The side surface of structure, length of the electrode in chip thickness direction are greater than or equal to the thickness of chip.On the one hand, it avoids using microprotrusion Connection is thinned the thickness of stacked structure, is advantageously implemented slimming.On the other hand, electrode is set to the side surface of stacked structure, Reserved link position need not need not be considered when junction is arranged in wiring layer, designs circuit, not will cause on-chip circuitry layout The limitation of setting.In another aspect, length of the electrode in chip thickness direction is greater than or equal to the thickness of chip, it is multiple convenient for connecting Circuit on chip.

The packaging part of the utility model, including above-mentioned semiconductor device, and the encapsulation set on the side surface of stacked structure Substrate, package substrate are electrically connected with electrode.On the one hand, the side surface of stacked structure is arranged in package substrate, can preferably do To slimming.On the other hand, the upper and lower surface of stacked structure can be used as radiating surface, increases effective heat dissipation area, is conducive to more The realization of high capacity.

Detailed description of the invention

Its example embodiment is described in detail by referring to accompanying drawing, above and other feature and advantage of the utility model will It becomes readily apparent from.

Fig. 1 is the attachment structure schematic diagram of chip stack poststack in the prior art；

Fig. 2 is the structural schematic diagram of an example embodiment of the utility model semiconductor devices；

Fig. 3 is the schematic perspective view of semiconductor devices shown in Fig. 2；

Fig. 4 is the structural schematic diagram of another example embodiment of the utility model semiconductor devices；

Fig. 5 is the flow diagram of the preparation method of the utility model semiconductor devices；

Fig. 6 is the structural schematic diagram of chip；

Fig. 7 is the structural schematic diagram in the seal area formation silicon perforation of chip；

Fig. 8 is that chip forms the structural schematic diagram after stacked structure；

Fig. 9 is the structural schematic diagram after the part seal area for removing chip；

Figure 10 is the structural schematic diagram after stacked structure forms convex block；

Figure 11 is the partial top schematic diagram of Figure 10；

Figure 12 is the structural schematic diagram of an example embodiment of the utility model packaging part；

Figure 13 is the schematic top plan view of Figure 12；

Figure 14 is the flow diagram of the preparation method of the utility model packaging part.

The reference numerals are as follows for main element in figure:

In the prior art: 1, chip；2, silicon perforation；3, microprotrusion；

In the utility model: 41, the first chip；42, the first sub- chip；43, the second sub- chip；44, the sub- chip of third；

51, the first wiring layer；52, the second wiring layer；53, third wiring layer；54, the 4th wiring layer；

6, electrode；61, first electrode；62, second electrode；63, third electrode；64, the 4th electrode；65, the 5th electrode；

7, convex block；

8, chip；81, circuit region；82, seal area；83, lead；

91, the first silicon perforation；92, the second silicon perforation；

10, package substrate；11, encapsulating film；

121, the first signal end；122, second signal end；123, third signal end；124, fourth signal end；125, the 5th Signal end.

Specific embodiment

Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that this is practical new Type will be full and complete, and the design of example embodiment is comprehensively communicated to those skilled in the art.It is identical in figure Appended drawing reference indicates same or similar structure, thus the detailed description that will omit them.

The utility model provides a kind of semiconductor devices, the semiconductor devices may include stacked structure, wiring layer with And electrode, stacked structure contain at least one chip；Electrode is located at the side surface of the stacked structure, and the electrode is in the core The length of piece thickness direction is greater than or equal to the thickness of the chip.

The semiconductor devices of the utility model, on the one hand, avoid connecting using microprotrusion, subtract the thickness of stacked structure It is thin, it is advantageously implemented slimming.On the other hand, electrode is set to the side surface of stacked structure, it is not necessary in wiring layer, junction is set, Reserved link position need not be considered when designing circuit, not will cause the limitation of on-chip circuitry layout setting.In another aspect, electrode Length in chip thickness direction is greater than or equal to the thickness of chip, convenient for connecting the circuit on multiple chips.

In this example embodiment, the side that chip is provided with wiring layer is become into "upper", opposite with "upper" is "lower", be connected to and be lower between be side surface.

Stacked structure can only include the first chip, also may include the first chip and the second chip, and the second chip can be with Include one or more layers chip.

In this example embodiment, referring to the structural representation of an example embodiment of semiconductor devices shown in Fig. 2 Figure.Stacked structure may include four layers of chip, is described below for convenience four layers of chip may be respectively referred to as from bottom to up One chip 41, the first sub- chip 42, the second sub- chip 43 and the sub- chip 44 of third, the first sub- chip 42, the second sub- chip 43 And the sub- chip 44 of third forms the second chip.Wiring layer is provided on every layer of chip.Wiring layer on first chip 41 It is properly termed as the first wiring layer 51, the wiring layer on the first sub- chip 42 is properly termed as the second wiring layer 52, the second sub- chip 43 On wiring layer be properly termed as third wiring layer 53, the wiring layer on the sub- chip 44 of third is properly termed as the 4th wiring layer 54.Separately Outside, the specific structure of stacked structure is not limited to foregoing description, for example, stacked structure can only include one layer of chip, also can wrap Include layers of chips, three layers of chip, five layers of chip or more chip.

Referring to the structural schematic diagram of an example embodiment of semiconductor devices shown in Fig. 2.First wiring layer 51, second Wiring layer 52, third wiring layer 53 and the 4th wiring layer 54 can be electrically connected by silicon perforation, or can be not connected to mutually.

In this example embodiment, jagged, electricity is set in the side of the first sub- chip 42 and the sub- chip 44 of third Pole 6 is formed in notch.The electrode 6 on the first sub- chip 42 is arranged in will be on the wiring layer and the first sub- chip on the first chip Wiring layer electrical connection, the electrode 6 on the sub- chip 44 of third is set by the wiring layer and the sub- core of third on the second sub- chip 43 Wiring layer electrical connection on piece 44.The notch and electrode 6 can be formed by removing segment chip, i.e., first needing to form electricity The position of pole 6 forms silicon perforation, and then removing segment chip makes silicon perforation exposure form electrode 6.Silicon perforation runs through one layer of chip When, length of the electrode 6 in chip thickness direction is greater than or equal to the thickness of chip, and silicon perforation runs through layers of chips or multilayer chiop When, length of the electrode 6 in chip thickness direction is greater than the thickness of chip.Certainly, in the other examples embodiment party of the utility model In formula, electrode 6 can be arranged directly on the side of chip, without being arranged in notch.

Referring to the schematic perspective view of semiconductor devices shown in Fig. 3, it is formed in the same side surface of stacked structure Five electrodes 6 may be respectively referred to as first electrode 61, second electrode 62, third electrode 63, the 4th electrode 64 and the 5th electrode 65。

First electrode 61 is electrically connected to the first signal end 121 by the first wiring layer 51.Second electrode 62 passes through the second cloth Line layer 52 is electrically connected to second signal end 122.The third letter of the third signal end 123 of first wiring layer 51, the second wiring layer 52 Number end 123, the third signal end 123 of third wiring layer 53 and the 4th wiring layer 54 third signal end 123 pass through silicon perforation Electrical connection is then attached to third electrode 63, i.e. third electrode 63 passes through the first wiring layer 51, the second wiring layer 52, third cloth Line layer 53 and the 4th wiring layer 54 are electrically connected to third signal end 123.4th electrode 64 is electrically connected by the 4th wiring layer 54 To fourth signal end 124.5th electrode 65 is electrically connected to the 5th signal end 125 by third wiring layer 53.Being arranged such can be with It realizes that the individual signal on an other chip can individually be controlled by electrode, multiple signals on multiple chips also may be implemented Individually control or collective's control are realized in collective's control according to the demand of signal.Certainly, first electrode 61 can also be electrically connected The first wiring layer 51 and the second wiring layer 52 are connect, the first wiring layer 51 can be connect with the second wiring layer 52 by silicon perforation, Then it is electrically connected to first electrode 61；First wiring layer 51 can also be respectively provided with lead with the second wiring layer 52 and then directly pass through First electrode 61 is electrically connected.

In this example embodiment, show referring to the structure of another example embodiment of semiconductor devices shown in Fig. 4 It is intended to.Semiconductor devices, which also wraps, can include convex block 7, convex block 7 be set to electrode 6 separate chip one side, and convex block 7 protrude from it is scarce Mouth, i.e. convex block 7 are covered on the position of the setting electrode 6 of chip.Convex block 7 covers the connection of electrode 6 and electrode 6 and wiring layer Place, the i.e. length of convex block 7 are greater than or equal to the length of electrode 6, and the width of convex block 7 is greater than or equal to the width of electrode 6.

Further, the utility model additionally provides a kind of preparation method of semiconductor devices, partly leading referring to Figure 5 The flow diagram of the preparation method of body device, the preparation method may comprise steps of:

Step S10, forms stacked structure, and the stacked structure contains at least one chip 8.

Step S20 forms electrode 6 in the side surface of the stacked structure, and the electrode 6 is in 8 thickness direction of chip Length be greater than or equal to the chip 8 thickness.

Each step of the preparation method of semiconductor devices is described in detail below.

It before forming stacked structure, needs to form wiring layer on each chip 8, the method for forming wiring layer can be print Brush method, vapour deposition method etc., do not elaborate herein.Referring to the structural schematic diagram of chip shown in fig. 6, chip 8 includes circuit Area 81 and seal area 82, circuit region 81 are used for potting for accommodating wiring layer, seal area 82.Wiring on each chip 8 Part outside layer needs connection can form lead 83 and lead to seal area 82.

The structural schematic diagram that silicon perforation is formed referring to the seal area 82 shown in Fig. 7 in chip 8 is forming the first silicon perforation While 91, the second silicon perforation 92 can be formed in the seal area 82 of chip.Second silicon perforation 92 is formed in seal area with above-mentioned 82 lead 83 connects.Second silicon perforation 92 is formed simultaneously with the first silicon perforation 91, saves process flow.

Step S10, forms stacked structure, and the stacked structure contains at least one chip.

In this example embodiment, it is illustrated by taking four layers of chip as an example.After formation stacked structure shown in Fig. 8 Structural schematic diagram.It is described below for convenience and four layers of chip be may be respectively referred to as into first the 41, first son of chip from bottom to up Chip 42, the second sub- chip 43 and the sub- chip 44 of third.It can be respectively in the first sub- chip 42, the second sub- chip 43 and The first silicon perforation 91 is formed on three sub- chips 44, the first silicon perforation 91 can connect wiring layer, the first son on the first chip 41 Wiring layer on chip 42, the wiring layer on the second sub- chip 43 and the wiring layer on the sub- chip 44 of third.Above-mentioned first The first sub- chip 42 is formed on chip 41, the second sub- chip 43 is formed on the first sub- chip 42, in the second sub- chip 43 On formed the sub- chip 44 of third.Certainly, the quantity of chip is also possible to one, two, three, five or more.In core In the case that piece is one, since chip does not need to connect with the chip for being located at the beneath chips, the first silicon can not be formed and worn Hole 91；The second silicon perforation 92 can be directly formed in the seal area 82 of the first chip 41.

Step S20 forms electrode 6 in the side surface of the stacked structure, and the electrode 6 is in the chip thickness direction Length is greater than or equal to the thickness of the chip.

Referring to the structural schematic diagram after the part seal area 82 shown in Fig. 9 for removing chip 8.

In this example embodiment, after forming stacked structure, the methods of grinding removal part seal area 82 can be passed through And the second silicon perforation of part 92 keeps the second silicon perforation 92 formation one of exposure rectangular until at the diameter of the second silicon perforation 92 The connection plane of shape, and the area maximum of the connection plane at this time, convenient for the formation and connection of subsequent convex block 7.Exposed Two silicon perforations 92 form electrode 6.Certainly, in the other examples embodiment of the utility model, seal area 82 can only be removed Material, without remove the second silicon perforation 92 material, can also make the second silicon perforation 92 exposure form electrode 6.Due to electrode 6 It is formed by the second silicon perforation 92, therefore, length of the electrode 6 in chip thickness direction is greater than the thickness of chip, in two chips Same position formed the second silicon perforation 92 in the case where, electrode 6 chip thickness direction length be greater than chip thickness.It is logical Electrode 6 and the joint face of wiring layer for crossing the formation of the second silicon perforation 92 are larger, it is relatively firm to connect.In addition, the formation of electrode 6 is not It is limited to the description above, electrode 6 directly can be formed by the methods of vapor deposition or printing in the side surface of stacked structure.

Electrode 6 shown in Fig. 9 is formed in a side surface of stacked structure, and certainly, electrode 6, which also can be set, to be stacked Two side surfaces of structure or multiple side surfaces, belong to the protection scope of the utility model.

In this example embodiment, after forming electrode 6, which can also include: the separate core in electrode 6 The one side of piece forms convex block 7.Structural schematic diagram after formation convex block 7 shown in 0 and Figure 11 referring to Fig.1.Convex block 7 is set as long Strip, convex block 7 be set to electrode 6 separate chip 8 one side, i.e., convex block 7 be covered on chip 8 be arranged electrode 6 position.Convex block The length that the junction of 7 covering electrodes 6 and electrode 6 and wiring layer, the i.e. length of convex block 7 are greater than or equal to electrode 6, convex block 7 Width be greater than or equal to electrode 6 width.

Further, the utility model additionally provides a kind of packaging part, referring to Fig.1 packaging part shown in 2 and Figure 13 Structural schematic diagram, the packaging part may include semiconductor devices, package substrate 10 and encapsulating film 11.Package substrate 10 is set to heap The side surface of stack structure, and be electrically connected with electrode 6.Encapsulating film 11 is set to the surface of the not set package substrate 10 of stacked structure.

The specific structure of semiconductor devices is above-mentioned to have been carried out detailed description, therefore details are not described herein again.

In this example embodiment, package substrate 10 is set as one, and stacked structure is arranged in is provided with electrode 6 one Side.Certainly, in the case where multiple side surfaces of stacked structure are provided with electrode 6, package substrate 10 can be set to it is multiple, It is arranged at stacked structure side surface, and encapsulating film 11 is arranged in the biggish upper and lower surface of the area of stacked structure, to increase envelope The heat dissipation area of piece installing.The upper and lower surface of stacked structure can be used as radiating surface, increase effective heat dissipation area, be conducive to more Gao Rong The realization of amount.Moreover, the side surface of stacked structure is arranged in package substrate 10, can preferably accomplish to be thinned.

Further, the utility model additionally provides a kind of preparation method of packaging part, referring to Fig.1 packaging part shown in 4 Preparation method flow diagram, the preparation method of packaging part may include step:

Step S60 forms above-mentioned semiconductor device.

Step S70 forms package substrate 10, the package substrate 10 and the electrode in the side surface of the stacked structure 6 electrical connections.

In this example embodiment, encapsulation is formed on the surface of the not formed package substrate 10 of the stacked structure Film 11.

Above-mentioned described feature, structure or characteristic can be incorporated in one or more embodiment party in any suitable manner In formula, if possible, it is characterized in discussed in each embodiment interchangeable.In the above description, it provides many specific thin Section fully understands the embodiments of the present invention to provide.It will be appreciated, however, by one skilled in the art that can be real The technical solution of the utility model is trampled without one or more in the specific detail, or others side can be used Method, component, material etc..In other cases, known features, material or operation are not shown in detail or describe to avoid fuzzy sheet The various aspects of utility model.

Although the term of relativity, such as "upper" "lower" is used to describe a component of icon for another in this specification The relativeness of one component, but these terms are in this manual merely for convenient, for example, with reference to the accompanying drawings described in show The direction of example.It is appreciated that, if making it turn upside down the device overturning of icon, the component described in "upper" will As the component in "lower".Term of other relativities, such as "high" " low " "top" "bottom" etc. also make have similar meaning.When certain Structure is at other structures "upper", it is possible to refer to that certain structural integrity is formed in other structures, or refer to that certain structure " direct " is set It sets in other structures, or refers to that certain structure is arranged in other structures by the way that another structure is " indirect ".

In this specification, term "one", " one ", "the", " described " and "at least one" indicating there are one or Multiple element/component parts/etc.；Term "comprising", " comprising " and " having " are to indicate the open meaning being included And refer to the element in addition to listing/component part/also may be present other than waiting other element/component part/etc.；Term " the One ", " second " and " third " etc. only use as label, are not the quantity limitations to its object.

It should be appreciated that the utility model be not limited in its application to this specification proposition component detailed construction and Arrangement.The utility model can have other embodiments, and can realize and execute in many ways.Aforementioned change Shape form and modification are fallen in the scope of the utility model.It should be appreciated that this reality of this disclosure and restriction It is mentioned or all alternative groups of two or more apparent independent features with the novel text and/or drawings that extend to It closes.All these different combinations constitute multiple alternative aspects of the utility model.Embodiment described in this specification is said The best mode for becoming known for realizing the utility model is illustrated, and those skilled in the art will be enable practical new using this Type.

Claims (10)

1. a kind of semiconductor devices characterized by comprising

Stacked structure contains at least one chip；

Electrode, positioned at the side surface of the stacked structure, length of the electrode in the chip thickness direction is greater than or equal to The thickness of the chip.

2. semiconductor devices according to claim 1, which is characterized in that the semiconductor devices further include:

Wiring layer is set on the chip, wherein the wiring layer is provided with multiple signal ends, and multiple signal ends pass through The wiring layer is electrically connected with the electrode.

3. semiconductor devices according to claim 1, which is characterized in that the stacked structure includes:

First chip；

Second chip is set on first chip.

4. semiconductor devices according to claim 3, which is characterized in that first chip is equipped with the first wiring layer, Second chip is equipped with the second wiring layer, first wiring layer and second wiring layer and is electrically connected by silicon perforation.

5. semiconductor devices according to claim 4, which is characterized in that the electrode is electrically connected to first wiring One or more of layer, described second wiring layer.

6. semiconductor devices according to claim 2, which is characterized in that jagged, the electrode is arranged on the chip It is arranged in the notch.

7. semiconductor devices according to claim 6, which is characterized in that the semiconductor devices further include: convex block is set to The one side far from the chip of the electrode, the convex block protrude from the notch.

8. semiconductor devices according to claim 7, which is characterized in that the convex block covers the electrode and the electricity The junction of pole and the wiring layer.

9. a kind of packaging part characterized by comprising

Semiconductor devices described in claim 1~8 any one；

Package substrate is electrically connected set on the side surface of the stacked structure, and with the electrode.

10. packaging part according to claim 9, which is characterized in that the packaging part further include:

Encapsulating film, set on the surface of the not set package substrate of the stacked structure.