CN209046251U - A kind of LDO current-limiting circuit compared based on electric current and electronic equipment - Google Patents
A kind of LDO current-limiting circuit compared based on electric current and electronic equipment Download PDFInfo
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- CN209046251U CN209046251U CN201822046304.8U CN201822046304U CN209046251U CN 209046251 U CN209046251 U CN 209046251U CN 201822046304 U CN201822046304 U CN 201822046304U CN 209046251 U CN209046251 U CN 209046251U
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Abstract
The utility model discloses a kind of LDO current-limiting circuit compared based on electric current and electronic equipment, wherein LDO current-limiting circuit, including transistor PM0, the grid end of transistor PM0 and the grid end of transistor PM1, the drain terminal of transistor PM8 is connected with the output end of amplifier AMP0, the drain terminal and voltage output end VLDO of transistor PM0, one end of resistance R1 is connected with the reference current input terminal of the first current mirror, the other end of resistance R1 is connect with the positive input of one end of resistance R2 and amplifier AMP0, the reverse input end of amplifier AMP0 is connect with reference voltage source, the drain terminal of transistor PM1 is connect with the first image current input terminal of the first current mirror, what this circuit was taken is that the mode that electric current compares carries out, the gain of feedback control loop can effectively be promoted, the essence of raising system current limliting True property.
Description
Technical field
The utility model relates to LDO current-limiting circuit field more particularly to a kind of LDO current-limiting circuit compared based on electric current and
Electronic equipment.
Background technique
LDO (low dropout regulator, linear voltage regulator) using the transistor that is run in its linear region or
Field-effect tube (FET) subtracts the voltage of excess from the input voltage of application, generates the output voltage through overregulating.So-called pressure
Voltage is dropped, refers to input voltage and output electricity needed for voltage-stablizer maintains output voltage within its rated value or more 100mV
The minimum value of pressure difference volume.
There is no the defect of LDO current-limiting protection module:
1. tradition LDO linear voltage regulator, if in the case where without current-limiting protection circuit, being easy to appear module and powering on electric current
Can be excessive, it at this moment will affect the stability of superior system power supply, to influence electronic system stability, or even cause to crash existing
As.
2. the impact of excessive current versus section load easily causes chip fever, is easy to lead when electric current is larger
The service life decline for sending a telegraph road is even failed.
Utility model content
For this reason, it may be necessary to provide a kind of LDO current-limiting circuit compared based on electric current and electronic equipment, it is excessive to solve LDO electric current
The problem of.
To achieve the above object, a kind of LDO current-limiting circuit compared based on electric current, including transistor are inventor provided
The grid end of PM0, transistor PM0 are connect with the output end of the grid end of transistor PM1, the drain terminal of transistor PM8 and amplifier AMP0, brilliant
The drain terminal of body pipe PM0 is connect with the reference current input terminal of voltage output end VLDO, one end of resistance R1 and the first current mirror, electricity
The other end of resistance R1 is connect with the positive input of one end of resistance R2 and amplifier AMP0, the reverse input end and ginseng of amplifier AMP0
Voltage source connection is examined, the drain terminal of transistor PM1 is connect with the first image current input terminal of the first current mirror, the first current mirror
The image current of second image current input terminal and the input terminal of voltage follow unit, one end of resistance R3 and the second current mirror is defeated
Outlet connection, the reference current output end of the second current mirror and the current input terminal of reference current source connect, voltage follow unit
Output end connected with the grid end of transistor PM8, the other end of resistance R3 is connect with common voltage terminal VCOM, transistor PM8's
Source, the source of transistor PM0, the source of transistor PM1, the image current input terminal of the second current mirror, the second current mirror
Reference current input terminal is connected with positive pole VDD, the other end of resistance R2, the reference current output end of the first current mirror,
First image current output end of one current mirror, the second image current output end of the first current mirror, reference current source electric current
Output end is connect with power cathode VSS.
Further, first current mirror includes transistor PM2, transistor PM3, transistor NM0, transistor NM1, crystalline substance
The source of body pipe NM2, transistor NM3, transistor NM4, transistor NM5, transistor PM3 are connect with one end of resistance R1, crystal
The grid end of pipe PM3 is connect with the drain terminal of the grid end of transistor PM2, the drain terminal of transistor PM3 and transistor NM0, transistor PM2's
Source is connect with the drain terminal of transistor PM1, the drain terminal and the drain terminal of transistor NM1, the grid end of transistor NM3, crystalline substance of transistor PM2
The grid end of body pipe NM2, the connection of the grid end of transistor NM5, the grid end of transistor NM1 and grid end, the transistor NM4 of transistor NM0
Grid end connected with voltage node VBN0, the source of transistor NM0 is connect with the drain terminal of transistor NM2, the source of transistor NM1
Connect with the drain terminal of transistor NM3, the source of transistor NM4 is connect with the drain terminal of transistor NM5, the drain terminal of transistor NM4 with
One end of resistance R3 connects, the source of transistor NM2, the source of transistor NM3, the source of transistor NM5 and power cathode VSS
Connection.
Further, second current mirror includes transistor PM4, transistor PM5, transistor PM6, transistor PM7, crystalline substance
The source of body pipe PM4 and the source of transistor PM5 are connect with positive pole VDD, and the grid end of transistor PM4 is with transistor PM5's
Grid end, transistor PM6 drain terminal connected with one end of resistance R3, the drain terminal of transistor PM4 is connect with the source of transistor PM6,
The drain terminal of transistor PM5 is connect with the source of transistor PM7, the grid end of transistor PM6 and the grid end of transistor PM7 and voltage section
Point VBP0 connection.
Further, further include capacitor CP, one end of capacitor CP is connect with one end of resistance R3, the other end of capacitor CP with
Power cathode VSS connection.
Further, the voltage follow unit includes amplifier AMP1, the reverse input end and amplifier of the amplifier AMP1
The output end of AMP1 and the grid end of PM8 connect, and the positive input of amplifier AMP1 is connect with one end of resistance R3.
The utility model provides a kind of electronic equipment, including LDO circuit, LD0 power supply, LDO are by electric unit, biased electrical
Road, VCOM voltage generation circuit, reference voltage source and reference current source, the LDO circuit are the LDO current limliting of above-mentioned any one
The positive pole of circuit, the cathode output end of LDO power supply and LDO circuit connects, the cathode output end of LDO power supply with
The power cathode of LDO circuit is connected with LDO by the power cathode of electric unit, the reference voltage source of reference voltage source and LDO circuit
The reference current source connection of connecting pin connection, reference current source and LDO circuit connects, the voltage output end and LDO of LDO circuit
It is connected by the positive pole of electric unit, voltage node VBN0, VBP0 of biasing circuit and LDO circuit connects, and VCOM voltage generates
The common voltage terminal VCOM connection of circuit and LDO circuit.
It is different from the prior art, in 1. circuits of above-mentioned technical proposal by the way of PMOS/NMOS electric current complementary mirror image,
It forces control in similar voltage level the drain-source voltage of the drain-source voltage of power tube PM0 and oversampling ratio pipe PM1, avoids
The image current error due to caused by the channel-length modulation of power tube and scale tube realizes the essence to LDO limitation electric current
Really control.2. tradition LDO linear voltage regulator is carried out in such a way that voltage compares, what this circuit was taken is the side that electric current compares
Formula carries out, and can effectively promote the gain of feedback control loop, improves the accuracy of system current limliting.3. what circuit was taken is electric current
The mode compared carries out, and the output impedance that electric current compares is very big, and increasing capacitor in this output end can be the dominant pole control of loop
System allows LDO cyclic system Stability Design to be easier on the node.
Detailed description of the invention
Fig. 1 is LDO current-limiting circuit circuit diagram described in specific embodiment；
Fig. 2 is device structure schematic diagram described in specific embodiment.
Specific embodiment
Technology contents, construction feature, the objects and the effects for detailed description technical solution, below in conjunction with specific reality
It applies example and attached drawing is cooperated to be explained in detail.
Fig. 1 to Fig. 2 is please referred to, the present embodiment provides a kind of LDO current-limiting circuits compared based on electric current, including transistor
The grid end of PM0, transistor PM0 are connect with the output end of the grid end of transistor PM1, the drain terminal of transistor PM8 and amplifier AMP0, brilliant
The drain terminal of body pipe PM0 is connect with the reference current input terminal of voltage output end VLDO, one end of resistance R1 and the first current mirror 1,
The other end of resistance R1 is connect with the positive input of one end of resistance R2 and amplifier AMP0, the reverse input end of amplifier AMP0 with
Reference voltage source connection, the drain terminal of transistor PM1 are connect with the first image current input terminal of the first current mirror, the first current mirror
The second image current input terminal and voltage follow unit input terminal, one end of resistance R3 and the image current of the second current mirror
Output end connection, the reference current output end of the second current mirror and the current input terminal of reference current source connect, voltage follow list
The output end of member is connected with the grid end of transistor PM8, and the other end of resistance R3 is connect with common voltage terminal VCOM, transistor PM8
Source, the source of transistor PM0, the source of transistor PM1, the image current input terminal of the second current mirror, the second current mirror 2
Reference current input terminal connected with positive pole VDD, the other end of resistance R2, the first current mirror reference current output end,
First image current output end of the first current mirror, the second image current output end of the first current mirror, reference current source electricity
Stream output end is connect with power cathode VSS.
Above-mentioned transistor PM0 is the power tube of LDO module, and PM1 is mirror image pipe, in order to save area and guarantee that pipe can mention
For the needs of corresponding output power, power tube PM0 and scaled mirror pipe PM1 use channel length L very little, and channel width W is very
Big design size thinking.The channel-length modulation of MOS device is it is obvious that in order to force power tube PM0 and ratio in this way
The drain terminal voltage of example mirror image pipe PM1 controls on similar voltage level, to more accurately carry out to power tube and mirror image pipe
The proportional sampling of electric current, it is necessary to assure gate source voltage and drain-source voltage must be identical, power tube PM0 and scaled mirror pipe PM1's
Both grid end and source link together, it is only necessary to guarantee that their drain terminal voltage is identical, so introducing current mirror
Loopback circuit.The utility model circuit is at work: underloading situation, when the electric current that external loading absorbs is less than reference current source
When rated current, i.e. when ISAM < IREF, at this time electric current flows to VCOM from the upper end of resistance R3, at this time NA point
Voltage become VCOM+R3* (IREF-ISAM), i.e. AMP1 output voltage become VCOM+R3* (IREF-ISAM), at this time
It is bigger by the equivalent conducting resistance of the upper trombone slide PM8 under AMP1 control, there is weak pull-up characteristic, AMP0 output impedance is relatively low
Voltage driving advantage is accounted for, for the grid end voltage of power tube PM0 by AMP0 Predominant control, reflected feedback loop effect is simultaneously unknown
It shows, that is, gain around feedback is not high, LDO major loop is dominant, and output electric current can be controlled by primary loop.
Case of heavy load, when external loading absorb electric current be greater than rated current when, that is, ISAM > IREF when, this
When electric current the upper end of R3 is flowed to from VCOM, at this time the voltage of NA point becomes VCOM-R3* (ISAM-IREF), i.e. amplifier AMP1
The voltage of output becomes VCOM-R3* (ISAM-IREF), and at this moment the equivalent conducting resistance of upper trombone slide PM8 is smaller, has on strong
Characteristic is drawn, upper trombone slide PM8 equivalent impedance is relatively low to account for voltage driving advantage, and the grid end voltage of power tube PM0 is by PM8 advantage control
System, is pulled upward to certain voltage level, and the reflected feedback loop effect of this process is obvious, that is, gain around feedback
Increase, output electric current is caused to become smaller, plays the role of limiting electric current.
In above-described embodiment, current mirror, which plays, copies to the reference current equal proportion of input on image current.It is existing
Current mirror there are many realize mode, in the present invention, first current mirror include transistor PM2, transistor PM3,
Transistor NM0, transistor NM1, transistor NM2, transistor NM3, transistor NM4, transistor NM5, the source of transistor PM3 with
One end of resistance R1 connects, grid end and the grid end of transistor PM2, the drain terminal and transistor NM0 of transistor PM3 of transistor PM3
Drain terminal connection, the source of transistor PM2 connect with the drain terminal of transistor PM1, and the drain terminal of transistor PM2 is with transistor NM1's
Drain terminal, the grid end of transistor NM3, the grid end of transistor NM2, the connection of the grid end of transistor NM5, the grid end and crystalline substance of transistor NM1
The grid end of body pipe NM0, the grid end of transistor NM4 are connected with voltage node VBN0, and the source of transistor NM0 is with transistor NM2's
Drain terminal connection, the source of transistor NM1 are connect with the drain terminal of transistor NM3, the source of transistor NM4 and the leakage of transistor NM5
End connection, the drain terminal of transistor NM4 are connect with one end of resistance R3, the source of transistor NM2, the source of transistor NM3, crystal
The source of pipe NM5 is connect with power cathode VSS.
Further, second current mirror includes transistor PM4, transistor PM5, transistor PM6, transistor PM7, crystalline substance
The source of body pipe PM4 and the source of transistor PM5 are connect with positive pole VDD, and the grid end of transistor PM4 is with transistor PM5's
Grid end, transistor PM6 drain terminal connected with one end of resistance R3, the drain terminal of transistor PM4 is connect with the source of transistor PM6,
The drain terminal of transistor PM5 is connect with the source of transistor PM7, the grid end of transistor PM6 and the grid end of transistor PM7 and voltage section
Point VBP0 connection.In this way, PM3, PM2；PM4, PM5, PM6, PM7 respectively constitute the current mirror of p-type；NM0, NM1, NM2, NM3 structure
At the current mirror of N-type；PM0, R1, R2, AMP0 constitute the major loop of LDO work；PM1,PM2,NM1,NM3,NM4,NM5,PM4,
PM5, PM6, PM7, reference current source IREF, AMP1, PM8 constitute negative-feedback measure loop, which can restrict master
The working condition of loop.
After electrifying startup, PM2, PM3, NM0, NM1, NM2, NM3 constitute the winding of a p-type and N-type current mirror composition
Circuit, wherein NM0, NM1, NM2, NM3 introduce CASCODE (string stacked type) current mirror to obtain higher ratio accuracy of repetition,
The anti-interference ability of noise to ground is improved simultaneously.Power tube PM0 and scaled mirror pipe PM1 has the proportionate relationship in size, if
Set scale coefficient is K, is ISAMPLE by the sample rate current that scaled mirror comes out, the output electric current of actual LDO is
IACT, there are IACT=ISAMPLE × K.PM2 and PM3, NM0 and NM1, NM2 and NM3, NM1 and NM4, NM3 and NM5, PM4 with
The mirroring ratios of PM5, PM6 and PM7 are 1:1；Same PM4, PM5, PM6, PM7 constitute the current mirror of CASCODE structure with
Higher ratio accuracy of repetition is obtained, while improving the anti-interference ability to power supply noise, ISAMPLE and ideal current source IREF
It is connected on the same node NA, NA connection resistance R3 to medium voltage VCOM；AMP1 constitutes voltage follow unit, it is therefore an objective to mention
For lower output impedance, the corresponding pole of NB node is allowed to shift high-frequency region onto, the output of AMP1 controls upper trombone slide PM8, PM8 control
Power tube PM0 processed and ratio replicate pipe PM1.
Bias voltage circuit provides the dc point of voltage node VBN0, VBP0, and VCOM is that the half of supply voltage is
VDD/2 can realize that external circuit provides reference voltage (VREF) and is generally 1.2V with bleeder circuit.
Node NA is the node of two current sources connection, and output impedance is very high.One capacitor CP of this place setting, will
The NA node pole is directly drawn to low-frequency range, i.e., herein, NB, NC and ND pole are set as secondary for the dominant pole setting of circuit
Point, the equivalent output resistance of impedance isolation and voltage feedback characteristics of the NB pole because of AMP1 are 1/ (1+ of open loop resistance
Av), Av is open-loop gain.The corresponding pole of NB node can be pushed to high frequency region at this time.ND pole is with external loading
Variation, pole has corresponding variation, and in order to guarantee system stability energy, this ND node cannot function as the position of dominant pole,
Therefore this circuit is easily controlled system by the introducing of CP capacitor and the isolation of amplifier AMP1 and negative voltage feedback characteristic
Stability.
The utility model provides a kind of electronic equipment, including LDO circuit, LD0 power supply, LDO are by electric unit, biased electrical
Road, VCOM voltage generation circuit, reference voltage source and reference current source, the LDO circuit are the LDO current limliting of above-mentioned any one
The positive pole of circuit, the cathode output end of LDO power supply and LDO circuit connects, the cathode output end of LDO power supply with
The power cathode of LDO circuit is connected with LDO by the power cathode of electric unit, the reference voltage source of reference voltage source and LDO circuit
The reference current source connection of connecting pin connection, reference current source and LDO circuit connects, the voltage output end and LDO of LDO circuit
It is connected by the positive pole of electric unit, voltage node VBN0, VBP0 of biasing circuit and LDO circuit connects, and VCOM voltage generates
The common voltage terminal VCOM connection of circuit and LDO circuit.Wherein, LD0 power supply is the power supply for powering to LDO circuit,
It can be external power supply, battery or primary reduction voltage circuit etc..LDO circuit is used to be depressured and provide the electricity of burning voltage
Road, the LDO circuit of 78 such as common series.LDO is the unit for using the output voltage of LDO circuit by electric unit, such as be can be
Chip, single-chip microcontroller etc..Reference voltage source or reference current source are for providing the list of stable reference voltage or stable reference electric current
Member, or referred to as reference voltage source, reference current source.It can be effective using the electronic equipment of the LDO current-limiting circuit of the utility model
The gain of feedback control loop is promoted, the accuracy of system current limliting is improved, circuit is avoided to impact.
It should be noted that being not intended to limit although the various embodiments described above have been described herein
The scope of patent protection of the utility model.Therefore, based on the innovative idea of the utility model, embodiment described herein is carried out
Change and modification or equivalent structure or equivalent flow shift made based on the specification and figures of the utility model, directly
Or above technical scheme is used in other related technical areas indirectly, it is included in the patent protection model of the utility model
Within enclosing.
Claims (6)
1. a kind of LDO current-limiting circuit compared based on electric current, it is characterised in that: including transistor PM0, the grid end of transistor PM0
It is connect with the output end of the grid end of transistor PM1, the drain terminal of transistor PM8 and amplifier AMP0, the drain terminal and voltage of transistor PM0
Output end VLDO, one end of resistance R1 are connected with the reference current input terminal of the first current mirror, the other end and resistance of resistance R1
One end of R2 is connected with the positive input of amplifier AMP0, and the reverse input end of amplifier AMP0 is connect with reference voltage source, crystal
The drain terminal of pipe PM1 is connect with the first image current input terminal of the first current mirror, the second image current input of the first current mirror
End is connect with the image current output end of the input terminal of voltage follow unit, one end of resistance R3 and the second current mirror, the second electricity
The current input terminal of the reference current output end and reference current source that flow mirror connects, the output end and transistor of voltage follow unit
The grid end of PM8 connects, and the other end of resistance R3 is connect with common voltage terminal VCOM, the source of transistor PM8, transistor PM0
Source, the source of transistor PM1, the image current input terminal of the second current mirror, the second current mirror reference current input terminal and
Positive pole VDD connection, the other end of resistance R2, the reference current output end of the first current mirror, the first current mirror the first mirror
Image current output end, the second image current output end of the first current mirror, reference current source current output terminal and power cathode
VSS connection.
2. a kind of LDO current-limiting circuit compared based on electric current according to claim 1, it is characterised in that: first electricity
Flowing mirror includes transistor PM2, transistor PM3, transistor NM0, transistor NM1, transistor NM2, transistor NM3, transistor
The source of NM4, transistor NM5, transistor PM3 are connect with one end of resistance R1, and the grid end of transistor PM3 is with transistor PM2's
Grid end, transistor PM3 drain terminal connected with the drain terminal of transistor NM0, the drain terminal of the source of transistor PM2 and transistor PM1 connect
It connects, the drain terminal and the drain terminal of transistor NM1, the grid end of transistor NM3, the grid end of transistor NM2, transistor NM5 of transistor PM2
Grid end connection, grid end, the grid end of transistor NM4 and the voltage node VBN0 of the grid end of transistor NM1 and transistor NM0 connect
It connecing, the source of transistor NM0 is connect with the drain terminal of transistor NM2, and the source of transistor NM1 is connect with the drain terminal of transistor NM3,
The source of transistor NM4 is connect with the drain terminal of transistor NM5, and the drain terminal of transistor NM4 is connect with one end of resistance R3, transistor
The source of NM2, the source of transistor NM3, the source of transistor NM5 are connect with power cathode VSS.
3. a kind of LDO current-limiting circuit compared based on electric current according to claim 1, it is characterised in that: second electricity
Stream mirror includes transistor PM4, transistor PM5, transistor PM6, transistor PM7, the source of transistor PM4 and transistor PM5's
Source is connect with positive pole VDD, grid end and the grid end of transistor PM5, the drain terminal and resistance of transistor PM6 of transistor PM4
One end of R3 connects, and the drain terminal of transistor PM4 is connect with the source of transistor PM6, the drain terminal and transistor PM7 of transistor PM5
Source connection, the grid end of transistor PM6 connect with the grid end of transistor PM7 and voltage node VBP0.
4. a kind of LDO current-limiting circuit compared based on electric current according to claim 1, it is characterised in that: further include capacitor
One end of CP, capacitor CP are connect with one end of resistance R3, and the other end of capacitor CP is connect with power cathode VSS.
5. a kind of LDO current-limiting circuit compared based on electric current according to claim 1, it is characterised in that: the voltage with
It is connected with unit comprising the grid end of amplifier AMP1, the reverse input end of the amplifier AMP1 and the output end of amplifier AMP1 and PM8,
The positive input of amplifier AMP1 is connect with one end of resistance R3.
6. a kind of electronic equipment, it is characterised in that: including LDO circuit, LD0 power supply, LDO by electric unit, biasing circuit,
VCOM voltage generation circuit, reference voltage source and reference current source, the LDO circuit are claims 1 to 5 any one
LDO current-limiting circuit, the cathode output end of LDO power supply and the positive pole of LDO circuit connect, the cathode of LDO power supply
The power cathode and LDO of output end and LDO circuit are connected by the power cathode of electric unit, the ginseng of reference voltage source and LDO circuit
It examines voltage source connection to connect, the reference current source connection of reference current source and LDO circuit connects, and the voltage of LDO circuit is defeated
Outlet and LDO are connected by the positive pole of electric unit, and voltage node VBN0, VBP0 of biasing circuit and LDO circuit connects, VCOM
The common voltage terminal VCOM connection of voltage generation circuit and LDO circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201822046304.8U CN209046251U (en) | 2018-12-07 | 2018-12-07 | A kind of LDO current-limiting circuit compared based on electric current and electronic equipment |
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| CN201822046304.8U CN209046251U (en) | 2018-12-07 | 2018-12-07 | A kind of LDO current-limiting circuit compared based on electric current and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109361201A (en) * | 2018-12-07 | 2019-02-19 | 福建超瑞创原信息技术有限公司 | A kind of LDO current-limiting circuit compared based on electric current and electronic equipment |
-
2018
- 2018-12-07 CN CN201822046304.8U patent/CN209046251U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109361201A (en) * | 2018-12-07 | 2019-02-19 | 福建超瑞创原信息技术有限公司 | A kind of LDO current-limiting circuit compared based on electric current and electronic equipment |
| CN109361201B (en) * | 2018-12-07 | 2024-02-23 | 福州码灵微电子科技有限公司 | LDO current limiting circuit based on current comparison and electronic equipment |
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Address after: Room 07, 19th Floor, Building 2, Wanfu Center, No. 10 Chuangye Road, Shangjie Town, Minhou County, Fuzhou City, Fujian Province, 350000 Patentee after: Fuzhou Maling Microelectronics Technology Co.,Ltd. Address before: No. 808, 8th Floor, Zone A, Zuohai Science and Technology Building, No. 392 Beihuan West Road, Gulou District, Fuzhou City, Fujian Province, 350000 Patentee before: FUJIAN SUPERRISC INFORMATION TECHNOLOGY CO.,LTD. |