CN2089829U - Multifunction digital multichannel question-and-answer game apparatus - Google Patents

Multifunction digital multichannel question-and-answer game apparatus Download PDF

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Publication number
CN2089829U
CN2089829U CN 90215854 CN90215854U CN2089829U CN 2089829 U CN2089829 U CN 2089829U CN 90215854 CN90215854 CN 90215854 CN 90215854 U CN90215854 U CN 90215854U CN 2089829 U CN2089829 U CN 2089829U
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question
answer
circuit
door
timing
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隆惠君
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Abstract

The utility model discloses a multifunction digital multi-channel question-and-answer game device which is an electronic device used for the various talent shows. The multifunction digital multi-channel question-and-answer game device is provided with a timing and time-limit circuit, a second timing indication adopting the acousto-optic simulating clock dial type, and a minute timing indication adopting the numeric-display accumulated reducing mode; a screen is also provided with a Chinese character displaying system displaying 'violation ', ' question-and-answer ', ' start ', ' stop ', etc. and a sound alarming system; the screen is provided with an automatic switchover circuit for alternating current and direct current; the screen has the functions of preferential displaying the question-and-answer and the self locking operation. The utility model is provided with a hundred-path input device supplying for conducting the question-and-answer contest below one hundred people (or group); the utility model can be used for testing the various reaction speeds in the physical training; the utility model can also be used for the terminal displaying operation of the alarm system of the various multi-path.

Description

Multifunction digital multichannel question-and-answer game apparatus
The utility model is for carrying out the intelligence test electronic installation, particularly a kind of intelligence test question-and-answer game apparatus.
At present, carry out the question-and-answer game apparatus that intelligence test is used, circuit when scarcely designing when needing timing, is then used the clock and watch timing by the referee, and promptly inconvenience is inaccurate again, and the visual angle is minimum.Though there is the minority question-and-answer game apparatus to establish delay switching circuit, all be with capacitance-resistance (RC) charge and discharge system, spectators and entrant can't see fixture and from time of terminal point etc.The question-and-answer game apparatus majority is not established warning circuit, and what just have directly indicates " racing to be the first to answer a question " or " stopping " with indicator lamp, and the visual angle is minimum.General various relays, the transistor of adopting of existing question-and-answer game apparatus finished preferential indication and auto-lock function, and temporal resolution is low, occur during use simultaneously by phenomenon and indicate not according to group.And existing type screen is not established the direct current hole, use the restriction that has been subjected to power supply, and input group number is few, though can be with the use in parallel of two machines, very inconvenient, particularly indication is not directly perceived.
The purpose of this utility model provides a kind of accurate timing, directly perceived, temporal resolution height, the digital question-and-answer game apparatus of contest when as follows for hundred people (group) that AC and DC is dual-purpose.
The utility model by minute timing indication, second timing indication and " faults ", " racing to be the first to answer a question ", " beginning ", " stopping " Chinese characters display screen face and input circuit, race to be the first to answer a question circuit, branch timing displaing circuit, second timing displaing circuit, warning circuit and power supply circuits and form.
Fig. 1 is the utility model profile schematic diagram; Fig. 2 is the utility model input circuit figure; Fig. 3 races to be the first to answer a question circuit diagram for the utility model; Fig. 4 divides timing displaing circuit figure for the utility model; Fig. 5 is the utility model timing displaing circuit second figure; Fig. 6 is the utility model warning circuit figure; Fig. 7 is the utility model power supply circuit.
As shown in Figure 1, the utility model panel is provided with Chinese character demonstrations such as dividing timing indication, second timing indication and " fault ", " racing to be the first to answer a question ", " beginning ", " stopping " intuitively.Divide the timing indication to adopt numeral to show the tired mode that subtracts, acousto-optic analog timepiece disc type is adopted in a second timing indication.The utility model by input circuit, race to be the first to answer a question circuit, divide timing displaing circuit, second timing displaing circuit, warning circuit and power-supplying circuit form.
As shown in Figure 2, input circuit is by diode 1D1~1D200, press button 1AN1~1AN100, and resistance 1R1~1R20, electric capacity 1C1~1C22 forms.The group number pulse that produces when by diode 1D1~1D200 group number button 1AN1~1AN100 being pressed is divided into a group number digit pulse and group number ten digit pulses, delivering to a position BCD decimal system converter 2IC1 and ten BCD decimal system converter 2IC2,1C21,1C22 of racing to be the first to answer a question circuit respectively is filter capacitor, the various interference that filtering is brought by power supply.1R1~1R20 is connected across respectively between every of a group number bit line and every ten bit line and the power supply, makes each group number line maintenance level"1" when no group number pulse.1C1~1C20 is connected in parallel on respectively between every group number line and the ground wire, is used for eliminating the various interference that group number button line brings, and assurance decimal system BCD converter is worked reliably.
As shown in Figure 3, race to be the first to answer a question circuit by triode 2BG1~2BG14, resistance 2R1~2R15, press button 2AN1, electric capacity 2C1 and integrated package 2IC1~2IC11 forms.Before racing to be the first to answer a question beginning or race to be the first to answer a question at every turn finish in, press the 2AN1 reset button earlier, 2IC5,2,IC6 four R-S latch are resetted, eight inputs of 2,IC7 eight input nor gates are connected on each output " Q " end of 2IC5,2,IC6 four R-S latch, therefore 2IC7 " J " (non-) output is exported level"1", this level"1" is given each input of 2IC3,2,IC4 four-dual input and door, and each all is opened with door to make 2IC3,2IC4, waits for the arrival of group number pulse.When someone (group) presses group number press button on the own platform, this group number pulse just is divided into ten of group numbers and a group number digit pulse by input circuit, deliver to BCD decimal system converter 2IC1 respectively, 2IC2,2IC1, the four-dual input and a door 2IC3 of ten of 2IC2 output and a position BCD code through having opened, 2IC4 delivers to four-RS latch 2IC5, on each " S " end of 2IC6, make 2IC5,2IC6 exports ten of corresponding group numbers and a group number position BCD code, this BCD code is added on each input of 8 input nor gate 2IC7 on the one hand, 2IC7 " J " end output " 0 ", make 2IC3,2IC4 closes each with door, also all that promptly press after this group are raced to be the first to answer a question the group number inefficacy.The level"1" of 2IC7 " K " end output is delivered to warning circuit by the G line.Group number BCD code is delivered on each input of BCD seven-segment decoder 2IC10,2IC11 after anti-phase by hex inverter 2IC8,2IC9 on the other hand.Seven piece of digital coded signals of 2IC10,2IC11 output promote corresponding triode, connect corresponding bulb, demonstrate this group group number.
Branch timing displaing circuit is as shown in Figure 4 put and is pressed 3AN3 when several earlier, adds and make counter O reset by quenching pulse for 3IC1,3IC2 zero clearing " Cr " end.Divide ten, put branch position button 3AN1,3AN2 by underlying respectively again, give ten of branches, divide digit counter 3IC1, a 3IC2 to add the CP pulse, the number of times that 3IC1,3IC2 just press 3AN1,3AN2 becomes corresponding binary-coded decimal output, and this binary-coded decimal is remained in counter 3IC1, the 3IC2.When racing to be the first to answer a question the circuit zero clearing, the C line obtains level"1" from warning circuit, and this level"1" is delivered to respectively by 3D1: 1. be added to " Cr " end of 3IC7,3IC8 by 3C4, make it to reset.2. deliver to the numerical control system of the putting LD end of 3IC7 by the 3IC4 paraphase; Deliver to the numerical control system of the putting LD end of 3IC8 by the 3IC6 paraphase.3. open four-dual input and door 3IC3,3IC5, the binary-coded decimal in BCD counter 3IC1, the 3IC2 is just delivered in 3IC7, the 3IC8.The output of 3IC7,3IC8 is given respectively: 1.BCD seven-segment decoder 3IC10,3IC11 decipher, decoding output divides ten, individual signal to give triode 3BG1~3BG14 base stage, make corresponding triode conducting, connect corresponding bulb, demonstrate the answer time (score value) that this topic allows.2. deliver on each input of branch testing circuit 8 input nor gate 3IC9.When racing to be the first to answer a question when beginning, the C line be " 0 " among Fig. 3, because the effect of 3R4,3IC3,3IC5 close, and phase inverter 3IC4,3IC6 exports " 1 ", is " 1 " so the LD of 3IC7,3IC8 holds, and makes to preset mark BCD code and can't deliver to 3IC7,3IC8 again; Because " L " line of warning circuit is a level"1", also be " the CP of 3IC7,3IC8 again +" hold to " 1 has satisfied 3IC7, the 3IC8 condition as down counter.At this moment, as long as " the CP of 3IC7,3IC8 -" bringing out existing " 1 " pulse, 3IC8 just subtracts " 1 " counting.When timing second was finished 60 seconds, D line acquisition pulsewidth was " 1 " pulse of 1 second, is somebody's turn to do 3IC8 is delivered in " 1 " pulse by the D line " CP -" end, make the former time score value of 3IC6 deduct 1, when a branch position down counter meter finished ten branch pulses, " OB " end of 3IC8 was exported " a 1 " pulse, delivers to " the CP of 3IC7 -" end, make the former ten minutes value in the 3IC7 deduct 1.Form the branch testing circuit by eight input nor gate 3IC9, have only after the time that is provided with, branch subtracted, just export level"1", go to control the work of termination prewired circuit second in second timing displaing circuit by the B line.Resistance 3R1~3R4 is zero inclined to one side resistance, and 3R6~3R19 is the biasing current-limiting resistance of 3BG1~3BG14, and electric capacity 3C1~3C3 is used for eliminating the various interference that 3AN1~3AN3 lead-in wire brings.
Timing second indicating circuit as shown in Figure 5 partly is made up of 60 seconds circulation timing indicating circuits, whole 5 seconds prewired circuits two.Wherein 60 seconds circulation timing indicating circuits by second a position counting circuit, seconds ten counting circuits, detected indicating circuit three parts in 1~60 second and form.
1. a second position counting circuit is finished by decimal system counting/pulsqe distributor 4IC1.It is to CP step-by-step counting second, and the result is assigned on each output of Q0~Q9, make Q0~Q9 by second the CP pulse number increase and export high level successively, and during intact ten the second CP pulses of every meter, carry " OC " end output one positive jump pulse is as the CP pulse of ten counting circuits second.
2. second ten counting circuits are made up of with door 4IC4, two inputs or door 4IC3 decimal system counting/pulsqe distributor 4IC2, R-S latch 4IC5, two inputs, it is counted the carry pulse that second, the position counting circuit was sent here, and is assigned on each output of Q0~Q5; R-S latch 4IC5, two inputs and a door 4IC4, two inputs or door 4IC3 form the clear circuit of 4IC2; When racing to be the first to answer a question the circuit zero clearing, the C line obtains level"1", this level"1" by or door 4IC3 " Cr " end of being added to 4IC2 make the 4IC2 zero clearing; When pulse per second (PPS) in the 59 second of per minute arrived, the level"1" that two inputs and door 4IC6 send here was given " S " end of R-S latch 4IC5, makes 4IC5 set, and the Q end is exported " 1 ", and two inputs are opened with door 4IC4; When last second of per minute arrived, the level"1" of the Q0 output of 4IC1 can make it zero clearing by " Cr " end that opened and door 4IC4 or door 4IC3 are added to 4IC2, thereby has finished timing, the pulse distribution of each second in one minute.When first pulse per second (PPS) of next branch arrived, the negative jumping of " Q0 " end of 4IC1 was " 0 ", and " Q1 " just jumping and be " 1 ", and the level"1" of Q1 also is added to " R " end of R-S latch 4IC5,4IC5 is resetted, for the zero clearing next time of 4IC2 is got ready.
3.1-60 detect indicating circuit by 4IC7~4IC12 second, 4IC21~4IC27, and triode 4BG1~4BG12, light emitting diode 4LED1~4LED48 bulb 4ZD1~4ZD12, resistance 4R1~4R18 forms.The Q0 of 4IC1~Q9 exports by being added on the shared negative pole that respectively is listed as LED after 4IC11, the power amplification of 4IC12 inverter buffer.The Q0 of 4IC2~Q5 output is by on the shared positive pole that is added to each row LED after the buffer 4IC10 power amplification.Have only as the 4IC1 corresponding with LED, LED was just luminous when the 4IC2 two ends level"1" occurred simultaneously.4R1~4R6 is the current-limiting resistance of LED.Two inputs are formed whole five seconds testing circuits with door 4IC7, a 4IC8,4IC9, and the whole five seconds signals of its output remove to control corresponding triode (Darlington multiple tube) and connect corresponding whole five seconds pilot bulbs by two inputs or door 4IC21,4IC22,4IC23.4R7~4R18 is the current limliting biasing resistor of each triode.
Whole five seconds prewired circuits are by four-dual input and door 4IC16~4IC20, R-S latch 4IC13, decimal system counting/pulsqe distributor 4IC14, resistance 4R2~4R3, electric capacity 4C1~4C3, and press button 4AN1~4AN2 forms.Its effect be whole five second second stop value insert timing circuit in advance and can continue with or change and put.Its operation principle is: press 4AN1 earlier to the 4IC14 zero clearing of decimal system counting/pulsqe distributor with R-S latch 4IC13 is resetted before putting number, Q end output level "0", this level "0" has been closed door 1, the door 2 of 4IC16 on the one hand, on the other hand by opened after the phase inverter 4IC15 paraphase 4IC16 the door 3, the door 4, make 4IC14 as yet not Q0, the Q2 during carry, Q1 output can be added to door 3, the door 4 of 4IC18, the door 1 of 4IC19.Put when several, pressing 4AN2 adds count pulse for the CP end of 4IC14, along with the increase of pressing 4AN2 number, the Q0 of 4IC14~Q9 end is exported level"1" successively, these level"1"s are added to each of four-dual input or door 4IC21,4IC22,4IC23 respectively through door 3, door 4 and each of 4IC19,4IC20 of four-dual input and door 4IC18, trigger triode 4BG3~4BG12 connects bulb 4ZD3~4ZD12 successively successively.When pressing the tenth time, the carry of 4IC14 " OC " output will be exported level"1", and this level"1" is added on the S end of 4IC13 through 4C1, makes the set of R-S latch, and the Q end is " 1 ", thereby open door 1, the door 2 of a 4IC16.Because the effect of phase inverter 4IC15, the door 3 of 4IC16, door 4 and 4IC17 are closed, and make the Q0 output of 4IC14 can only be added to the door 1 of 4IC18 and the door 1 of four-dual input or door 4IC21 by the door 1 of 4IC16, trigger 4BG1, connect bulb 4ZD1.Q1 output can only be added to the door 2 of 4IC18 by the door 2 of 4IC16 and the door 2 of four-dual input or door 4IC21 removes to trigger 4BG2, connects bulb 4ZD2; The output of Q2 is sent and is not gone out and do not have and stop second, also both last stop second be several whole five seconds then 4AN2 press several times.If in unlimited time, 4AN2 is got final product by 13 times.Four-dual input and door 4IC25,4IC26, each of 4IC27 is subjected to the branch timing to detect output line B control with door, have only when the mark that branch mark or setting are not set has subtracted, the B line is " 1 ", each of 4IC18~4IC20 all is opened, preset whole five second second value just by among opened 4IC18~4IC20 with preset corresponding of second value, each that open 4IC25~4IC27 with preset second corresponding door and by in each of four-dual input or door 4IC21~4IC23 with preset corresponding of second value, the trigger triode conducting, connect corresponding bulb, indicate and stop a second point.When second the counting circuit meter when presetting second point, opened with preset that second point is corresponding just exports level"1" with door, this level"1" by phase inverter 4IC24 anti-phase after, by the A line deliver to warning circuit carry out acousto-optic stop to report to the police and close the 1Hz oscillating circuit, each timing circuit stops timing, it is luminous continuously to stop second some bulb.
Warning circuit is as shown in Figure 6 formed the 1Hz oscillating circuit by 5IC13,5IC15,5R2,5C2, because the clamping action of 5D2, it whether vibrate by 5IC6 control, has only that it just vibrates when 5IC6 exports " 1 ".1Hz vibration output is leaded up to a 5IC24 and is given a second counting circuit by the E line, as the CP count pulse; The input of two inputs and door 5IC12 is delivered on another road.5IC14,5IC16,5IC17,5R3,5C3 form the 1KHz audio oscillator circuit, because the clamping action of 5D1, whether its vibration is by two inputs or door 5IC8 control, have only that it just vibrates when 5IC8 output level"1".Audio oscillation output is closed to Darlington multiple tube 5BG1 by the 5C4 lotus root and is amplified, and promotes loudspeaker and sends chimes of doom.
When racing to be the first to answer a question the circuit zero clearing, the M line obtains level"1", R-S latch 5IC3 set, and Q end output level"1", this level"1" divides three the tunnel: 1. making the C line is level"1"; 2. two inputs and door 5IC10 are opened; By phase inverter 5IC1 anti-phase after, obtain level "0" and supply with the L line and close two inputs and door 5IC6, a 5IC24, the 1Hz oscillating circuit is subjected to pincers and does not work.At this moment pressing the group number button as if certain group breaks rules exactly.During fault, it is level"1" that group number detects the G line, and this level"1" is closed two inputs and a door 5IC4 on the one hand by behind the phase inverter 5IC11 phase inverter, makes to begin to race to be the first to answer a question button 5AN1 and locked inefficacy; On the other hand, give respectively by opened door 5IC10: 1. opened 5IC21(is because the input of phase inverter 5IC19 is zero " 0 " by resistance 5R4 ground connection, 5IC19 exports " 1 ", so door 5IC20,5IC21,5IC22 are opened), promote the 5BG2 conducting, connect the fault indicator lamp; 2. pass through or the work of door 5IC8, a 5IC9 triggering 1KHz audio frequency oscillator.Audio signal promotes 5BG5 work through 5C4 after isolating paraphase by not gate 5IC17, sends the chimes of doom of 1KHz; 3. give or door 5IC7, make 5IC7 output level"1", this level"1" is given and door 5IC2, because another input of 5IC7 is connected on the output of 5IC19, so 5IC7 exports level"1", 5IC2 exports " 1 ", and the F line is a level"1", thereby closed BGD seven-segment decoder 2IC10,2IC11, the fault group number can't be shown on screen.If will show the fault group number, only need press and force the Show Button 5AN2, " fault " indication simultaneously is forced to extinguish.If will remove fault, need press once more and race to be the first to answer a question reset button 2AN1.
After racing to be the first to answer a question the circuit zero clearing, if no fault phenomenon, press 5AN1 and be and race to be the first to answer a question beginning.Press " 1 " pulse that 5AN1 produces by an opened 5IC4(because of no fault phenomenon, the G line is " 0 ", 5IC11 is output as " 1 "), R-S latch 5IC3 is resetted, Q line output level "0", this level "0" divides close 5IC10 at three the tunnel: the one tunnel, and the fault indicator lamp is not again worked; The second the tunnel to make " C " line be zero " 0 ", and timing is put and counted up to completely, prepares timing; Another road is by the anti-phase output level"1" of phase inverter 5IC1, and this level"1" divides three the tunnel again: 1. make the L line be " 1 "; 2. trigger the work of 1Hz oscillating circuit by opened door 5IC6; 3. open a 5IC24, make the 1Hz signal can deliver to the E line, give a second timing displaing circuit, as the CP sprocket pulse by opened 5IC24.1HZ vibration output is also sent respectively by an opened door 5IC12: 1. or door 5IC9,5IC8 trigger the 1KHz circuit working through 5D1, send and race to be the first to answer a question chimes of doom; 2. trigger the 5BG3 conducting through 5IC22, " beginning " indicator lamp is shinny, two inputs are connected on respectively on the output of phase inverter 5IC18,5IC11 with the input of door 5IC23, therefore it exports " 1 " between the negative half-cycle of 1Hz oscillator signal, trigger the 5BG4 conducting, it is shinny " to race to be the first to answer a question " indicator lamp, makes and races to be the first to answer a question chimes of doom and beginning, races to be the first to answer a question indicator lamp and send interrupted warning with the 1Hz oscillator signal, alternately shinny.If at this moment press the group number button for a certain group, then demonstrate this group group number on the curtain screen, simultaneously, " G " line is " 1 ", this level"1" becomes " 0 " by phase inverter 5IC9 is anti-phase and closes a 5IC13, the 1Hz signal can't be passed through, and 5IC13 goes to trigger and races to be the first to answer a question sound, light warning indicating circuit, races to be the first to answer a question acousto-optic and stops thereby making.At this moment, race to be the first to answer a question group and can begin answer.
When arriving preset time, A line output level "0", this level "0" is closed 5IC6 on the one hand, and the 1Hz oscillating circuit is quit work; Being inverted into level"1" by phase inverter 5IC5 on the other hand delivers to respectively: 1. opened door 5IC20 triggers 5BG1 and connects " stopping " indicator lamp; By or door 5IC7, make the F line for " 1 " with a door 5IC2, thereby extinguish the group number of positive answer group; 3. trigger the work of 1KHz audio oscillator circuit by nor gate 5IC8,5IC9, send 1KHz continuous alarm sound.If press 5AN2, the group number of positive answer group can be forced to show that " stopping " being forced to extinguish that chimes of doom does not stop.Race to be the first to answer a question the circuit reset switch if want circuit to recover to press 2AN1.5K1 is a change-over switch of racing to be the first to answer a question timing and other timing, and set place is put " 2 " and located to be other timing for racing to be the first to answer a question.5AN2 when other timework as pause button.Resistance 5R4 guarantees to be late for making the 5IC19 input reliably to be " 0 " at 5AN2.5C5 is for eliminating the various interference that the 5AN2 lead-in wire brings.5R1 makes an input of being late for 5IC4 at 5AN1 reliably be " 0 ", and 5C1 is for eliminating the various interferences that the 5AN1 lead-in wire brings.
Power supply circuits as shown in Figure 7,220 volts of civil powers are supplied with various pilot bulb power amplifiers by obtaining 12 volts of direct currents behind 6D1,6D2, the 6C1 rectifying and wave-filtering after the transformer step-down; 12 volts of direct currents obtain 8 volts of direct currents supplies all circuit except that bulb and audio frequency power amplifier after three-terminal regulator block 6IC1 voltage stabilizing, 6C2 filtering.6K1 races to be the first to answer a question selector switch for charging, puts " 2 " and locates to be charging that set place is for racing to be the first to answer a question.Battery automatic power diode when 6D3 is power failure.

Claims (8)

1, a kind of multifunction digital hundred road question-and-answer game apparatus, it is characterized in that it by minute timing indication, second timing indication and " faults ", " racing to be the first to answer a question ", " beginning ", " stopping " Chinese characters display screen face and input circuit, race to be the first to answer a question circuit, branch timing displaing circuit, second timing displaing circuit, warning circuit, power supply circuits and form.
2, question-and-answer game apparatus according to claim 1 is characterized in that branch timing indication employing numeral shows the tired mode that subtracts, and second timing is indicated and adopted acousto-optic analog timepiece disc type.
3, question-and-answer game apparatus according to claim 1 is characterized in that input circuit is made up of diode 1D1~1D200, press button 1AN1~1AN100, resistance 1R1~1R20, electric capacity 1C1~1C22.
4, question-and-answer game apparatus according to claim 1, it is characterized in that racing to be the first to answer a question circuit by triode 2BG1~2BG14, resistance 2R1~2R15, press button 2AN1, electric capacity 2C1, BCD decimal system converter 2IC1~2IC2, four-dual input are formed with door 2IC3~2IC4, four-RS latch 2IC5~2IC6, input nor gate 2IC7, phase inverter 2IC8~2IC9, BCD seven-segment decoder 2IC10~2IC11.
5, question-and-answer game apparatus according to claim 1 and 2 is characterized in that the branch timing displaing circuit by BCD counter 3IC1,3IC2, four-dual input and door 3IC3,3IC5, phase inverter 3IC4,3IC6, down counter 3IC7,3IC8, input nor gate 3IC9, BCD seven-segment decoder 3IC10,3IC11, resistance 3R1~3R18, electric capacity 3C1~3C3, button 3AN1~3AN3, diode 3D1, triode 3BG1~3BG14, bulb 3ZD1~3ZD14 forms.
6, question-and-answer game apparatus according to claim 1 and 2, it is characterized in that second timing displaing circuit is by decimal system counting/pulsqe distributor 4IC1,4IC2,4IC14, two inputs or door 4IC3, two inputs and door 4IC4,4IC6,4IC7,4IC8,4IC9, R-S latch 4IC5,4IC13, buffer 4IC10, inverter buffer 4IC11,4IC12, phase inverter 4IC15,4IC24, four-dual input and door 4IC25~4IC27, resistance 4R1~4R20, triode 4BG1~4BG12, light emitting diode 4LED1~4LED48, bulb 4ZD1~4ZD12, electric capacity 4C1~4C3, button 4AN1,4AN2 forms.
7, question-and-answer game apparatus according to claim 1, it is characterized in that warning circuit is by phase inverter 5IC1,5IC5,5IC11,5IC13~5IC19, two inputs and door 5IC2,5IC4,5IC6,5IC10,5IC12,5IC20~5IC24, two inputs or door 5IC7~5IC9, R-S latch 5IC3, resistance 5R1~5R8, electric capacity 5C1~5C5, diode 5D1,5D2, triode 5BG1~5BG5, bulb 5ZD1~5ZD4, press button 5AN1,5AN2 and loudspeaker Y form.
8, question-and-answer game apparatus according to claim 1 is characterized in that power supply circuits by three-terminal regulator block 6IC1, electrochemical capacitor 6C1,6C2, and diode 6D1,6D2,6D3, switch 6K1 forms.
CN 90215854 1990-09-12 1990-09-12 Multifunction digital multichannel question-and-answer game apparatus Pending CN2089829U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 90215854 CN2089829U (en) 1990-09-12 1990-09-12 Multifunction digital multichannel question-and-answer game apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 90215854 CN2089829U (en) 1990-09-12 1990-09-12 Multifunction digital multichannel question-and-answer game apparatus

Publications (1)

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CN2089829U true CN2089829U (en) 1991-12-04

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Application Number Title Priority Date Filing Date
CN 90215854 Pending CN2089829U (en) 1990-09-12 1990-09-12 Multifunction digital multichannel question-and-answer game apparatus

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CN (1) CN2089829U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102427859A (en) * 2009-05-18 2012-04-25 戴维·内维奥克斯 Electronic Board Game Using Reaction Time

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102427859A (en) * 2009-05-18 2012-04-25 戴维·内维奥克斯 Electronic Board Game Using Reaction Time
CN102427859B (en) * 2009-05-18 2014-09-10 戴维·内维奥克斯 Electronic Board Game Using Reaction Time

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