CN208861670U - Duty-ratio calibrating circuit and memory - Google Patents
Duty-ratio calibrating circuit and memory Download PDFInfo
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- CN208861670U CN208861670U CN201821837184.7U CN201821837184U CN208861670U CN 208861670 U CN208861670 U CN 208861670U CN 201821837184 U CN201821837184 U CN 201821837184U CN 208861670 U CN208861670 U CN 208861670U
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Abstract
The utility model relates to technical field of integrated circuits, in particular to a kind of duty-ratio calibrating circuit and memory.The duty-ratio calibrating circuit includes: signal adjustment circuit, for receiving and adjusting the first clock signal to generate second clock signal；Duty detection circuit connects the signal adjustment circuit, feeds back to the signal adjustment circuit for detecting the duty ratio of the second clock signal and will test result, the duty detection circuit includes adjustable condenser；Process corner detection unit is connect with the adjustable condenser, for detecting the technique angular dimensions of memory and adjusting the capacitance of the adjustable condenser according to the technique angular dimensions.The program can choose capacitance appropriate for different technique angular dimensions, so as to improve the reliability and accuracy of duty detection circuit.
Description
Technical field
The utility model relates to technical field of integrated circuits, in particular to a kind of duty-ratio calibrating circuit and storage
Device.
Background technique
In memory, duty ratio, which reaches 50%, to improve the utilization efficiency of clock level to the maximum extent, to protect
The normal operation of barrier system and the best performance of efficiency.However clock circuit duty ratio often deviates 50% in real work,
Clock duty cycle calibration circuit is exactly a kind of circuit for the design of this problem.
Currently, duty detection circuit has been fixed due to setting timer capacitor in duty-ratio calibrating circuit, it is different
Technique angular dimensions will have different charge/discharge speeds, and it is too fast too early or too late to will lead in duty detection circuit capacity cell
Slow-motion row discharge operation is crossed, the reliability and accuracy of duty detection circuit can be reduced in this way, seriously affected duty ratio inspection
It surveys as a result, to be unable to reach the requirement of duty ratio (50 ± 1) %.
It should be noted that information is only used for reinforcing the background to the utility model disclosed in above-mentioned background technology part
Understanding, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Utility model content
The purpose of this utility model is to provide a kind of duty-ratio calibrating circuit and memories, can be directed to different process corners
Parameter chooses capacitance appropriate can then guarantee so as to improve the reliability and accuracy of duty detection circuit
The duty ratio of memory meets 50% requirement.
The utility model provides a kind of duty-ratio calibrating circuit comprising:
Signal adjustment circuit, for receiving and adjusting the first clock signal to generate second clock signal；
Duty detection circuit connects the signal adjustment circuit, for detecting the duty ratio of the second clock signal
And will test result and feed back to the signal adjustment circuit, the duty detection circuit includes adjustable condenser；
Process corner detection unit is connect with the adjustable condenser, for detecting the technique angular dimensions and basis of memory
The technique angular dimensions adjusts the capacitance of the adjustable condenser.
In a kind of illustrative embodiments of the utility model, the process corner detection unit includes:
Process corner detection circuit, for detecting the technique angular dimensions of the memory；
Coding circuit, and the process corner detection circuit connection, for being encoded to the technique angular dimensions, to generate
Encoded signal；
Decoding circuit connects the coding circuit and the duty detection circuit, for converting the encoded signal
The capacitance of the adjustable condenser is adjusted for output signal and according to the output signal.
In a kind of illustrative embodiments of the utility model, the signal adjustment circuit includes:
Time delay chain, the time delay chain have the first delay receiving end, the second delay receiving end and a delay output end, and described the
For receiving first clock signal, the time delay chain can be delayed to first clock signal for one delay receiving end
Clock signal is adjusted to generate, the delay output end is for exporting the adjustment clock signal, second delay receiving end
It is connect with the clock signal output terminal of the duty detection circuit；
Clock generator, the clock generator have the first clock receiving end, second clock receiving end and clock output
End, for receiving first clock signal, the second clock receiving end and the delay are defeated for first clock receiving end
Outlet connects and is used to receive the adjustment clock signal, and the clock generator can be according to first clock signal and institute
It states adjustment clock signal and generates the second clock signal, the output terminal of clock is used to export the second clock signal, and
The output terminal of clock is connect with the clock signal receiving end of the duty detection circuit.
It further include counter in a kind of illustrative embodiments of the utility model, the duty detection circuit
Clock signal output terminal is connect by the counter with second delay receiving end.
In a kind of illustrative embodiments of the utility model, the adjustable condenser include it is multiple be connected in parallel can
Adjust condenser network, each tunable capacitor circuit include capacity cell and with the concatenated switch element of the capacity cell, each institute
Switch element is stated to connect with the decoding circuit；
The decoding circuit is used to convert the encoded signal to output signal and is adjusted according to the output signal each
The on off operating mode of the switch element, to adjust the capacitance of the adjustable condenser.
In a kind of illustrative embodiments of the utility model, the capacitor of capacity cell in each tunable capacitor circuit
It is worth identical or different.
In a kind of illustrative embodiments of the utility model, the capacity cell is metal-oxide-semiconductor, the grid of the metal-oxide-semiconductor
Pole connects the switch element.
In a kind of illustrative embodiments of the utility model, the switch element include the PMOS tube that is connected in parallel and
NMOS tube, the PMOS tube and the NMOS tube are connect with the decoding circuit respectively, and the PMOS tube and the NMOS tube are used
In the reception output signal.
The utility model additionally provides a kind of memory comprising duty-ratio calibrating circuit described in any of the above embodiments.
Technical solution provided by the utility model can achieve it is following the utility model has the advantages that
Duty-ratio calibrating circuit and memory provided by the utility model, duty detection circuit include tunable capacitor
Device, and this adjustable condenser is connect with process corner detection unit, which is able to detect the process corner of memory
Parameter and the capacitance that adjustable condenser is adjusted according to technique angular dimensions.In the present embodiment, by using adjustable condenser and work
Skill angle detection unit matches, and the capacitance in duty detection circuit can be adjusted to appropriate for different technique angular dimensions
Range, it is too fast too early or too late cross slow-motion row to alleviate capacitor element when process corner changes in duty detection circuit
The case where discharge operation, can then guarantee memory to improve the reliability and accuracy of duty detection circuit
The requirement of duty ratio satisfaction (50 ± 1) %.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The utility model can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows and meets the utility model
Embodiment, and be used to explain the principles of the present invention together with specification.It should be evident that the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the circuit diagram of duty-ratio calibrating circuit described in the utility model embodiment；
Fig. 2 is the circuit diagram of duty detection circuit shown in Fig. 1；
Fig. 3 is the timing diagram of duty detection circuit shown in Fig. 1；
Fig. 4 is the schematic diagram of adjustable condenser in duty detection circuit shown in Fig. 1.
Description of symbols:
In Fig. 1:
1, time delay chain；2, clock generator；3, duty detection circuit；4, counter；5, process corner detection circuit；6, it compiles
Code circuit；7, decoding circuit.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that this is practical new
Type will be full and complete, and the design of example embodiment is comprehensively communicated to those skilled in the art.It is identical in figure
Appended drawing reference indicates same or similar structure, thus the detailed description that will omit them.
Although the term of relativity, such as "upper" "lower" is used to describe a component of icon for another in this specification
The relativeness of one component, but these terms are in this manual merely for convenient, for example, with reference to the accompanying drawings described in show
The direction of example.It is appreciated that, if making it turn upside down the device overturning of icon, the component described in "upper" will
As the component in "lower".When certain structure is at other structures "upper", it is possible to refer to that certain structural integrity is formed in other structures
On, or refer to that certain structure is " direct " and be arranged in other structures, or refer to that certain structure is arranged by the way that another structure is " indirect " in other knots
On structure.
Term "one", " one ", "the", " described " to indicate there are one or more elements/component part/etc.；With
Language " comprising " and " having " is to indicate the open meaning being included and refer to element/composition portion in addition to listing
Also may be present except divide/waiting other element/component part/etc.；Term " first " and " second " etc. are only used as label, no
It is the quantity limitation to its object.
In memory, duty ratio, which reaches 50%, to improve the utilization efficiency of clock level to the maximum extent, to protect
The normal operation of barrier system and the best performance of efficiency.However clock circuit duty ratio often deviates 50% in real work,
Clock duty cycle calibration circuit is exactly a kind of circuit for the design of this problem.
In the related technology, in duty-ratio calibrating circuit, duty detection circuit has been fixed due to setting timer capacitor,
Different technique angular dimensions will have different charge/discharge speeds, and it is too fast too early to will lead to capacity cell in duty detection circuit
Or slow-motion row discharge operation is crossed too late, the reliability and accuracy of duty detection circuit can be reduced in this way, have been seriously affected and have been accounted for
Sky is than testing result, to be unable to reach the requirement of duty ratio (50 ± 1) %.
In order to solve the above technical problems, the utility model embodiment provides a kind of duty-ratio calibrating circuit, can be applied to
In memory, which can be random access memories.
As shown in Figure 1, this duty-ratio calibrating circuit may include signal adjustment circuit, duty detection circuit 3 and process corner
Detection unit.Wherein, signal adjustment circuit generates second clock letter for receiving and adjusting the first clock signal of memory
Number；Duty detection circuit 3 can connection signal adjustment circuit, for detecting the duty ratio of second clock signal and will test result
Signal adjustment circuit is fed back to, and duty detection circuit 3 includes adjustable condenser；And process corner detection unit can be with adjustable electric
Container connection, for detecting the technique angular dimensions of memory and according to the capacitance of technique angular dimensions adjustment adjustable condenser.
Specifically, since the process corner of memory is when being in different situations, parameter is different, such as: threshold voltage Vth
Difference, therefore electric current I can be made different, wherein threshold voltage VthWith electric current I between inversely proportional relationship, it may be assumed that threshold voltage
Vth is bigger, and electric current I is smaller；Threshold voltage VthSmaller, electric current I is bigger.In addition, by Q (quantity of electric charge)=I (electric current) × T (time)
=C (capacitor) × U (voltage) is proportional relation between electric current I and capacitor C it is found that in the case where time T and voltage U constant,
That is: electric current I is bigger, and capacitor C is bigger；Electric current I is smaller, and capacitor C is smaller.Therefore, pass through process corner detection unit characterization processes angle
Parameter, such as threshold voltage Vth, learning threshold voltage VthWhen, it can be according to threshold voltage VthIt will be in duty detection circuit 3
Adjustable condenser be adjusted to required capacitance, to guarantee the reliability and accuracy of duty detection circuit 3, then can
Enough guarantee the requirement of duty ratio satisfaction-(50 ± 1) % of memory.
It in the present embodiment, is matched by using adjustable condenser with process corner detection unit, different technique can be directed to
Capacitance in duty detection circuit 3 is adjusted to proper range by angular dimensions, is detected with alleviating in different process angle duty ratio
The case where capacitor element in circuit 3 is too fast too early or crosses slow-motion row discharge operation too late, to improve duty ratio detection electricity
The reliability and accuracy on road 3 can then guarantee that the duty ratio of memory meets the requirement of (50 ± 1) %.
The duty-ratio calibrating circuit of the utility model embodiment is described in detail below:
Process corner detection unit in present embodiment includes process corner detection circuit 5, coding circuit 6 and decoding circuit 7.
The process corner detection circuit 5 is used to detect the technique angular dimensions of memory, which can be threshold voltage VthOr electronics
Mobility u or grid oxygen capacitor Cox；Coding circuit 6 is connect with process corner detection circuit 5, for being encoded to technique angular dimensions,
To generate encoded signal；Decoding circuit 7 connects coding circuit 6 and duty detection circuit 3, defeated for converting encoded signal to
Out signal and according to output signal adjust adjustable condenser capacitance.Signal adjustment circuit may include time delay chain 1 and clock hair
Raw device 2.Wherein, the initial value of the time delay chain 1 can be T/2.There is this time delay chain 1 first delay receiving end, the second delay to receive
End and delay output end, first delay receiving end for receive the first clock signal, time delay chain 1 can to the first clock signal into
For line delay to generate adjustment clock signal, delay output end is used for output adjustment clock signal, the second delay receiving end and duty
Clock signal output terminal than detection circuit 3 connects；Clock generator 2 has the first clock receiving end, second clock receiving end
And output terminal of clock, the first clock receiving end connect for receiving the first clock signal, second clock receiving end and delay output end
Adjustment clock signal is connect and is used to receive, clock generator 2 can generate the according to the first clock signal and adjustment clock signal
Two clock signals, output terminal of clock is for exporting second clock signal, and the clock of output terminal of clock and duty detection circuit 3
Signal receiving end connection.
Wherein, duty-ratio calibrating circuit further includes counter 4, and the clock signal output terminal of duty detection circuit 3 passes through
Counter 4 is connect with the second delay receiving end.
For example, duty detection circuit 3 can there are many form, 3 figure of duty detection circuit and timing diagram difference
As shown in Figures 2 and 3, the circuit of this generally mirror settings of duty detection circuit 3.Specifically, duty detection circuit 3 wraps
Include clock signal receiving end, main circuit, detection signal receiving end, latch cicuit and clock signal output terminal.Wherein, clock signal
Receiving end connects the output terminal of clock of clock generator 2, for receiving complementary signal MCLK to be detected and/MCLK, the signal
The second clock signal generated by clock generator 2 is transformed.Main circuit is used for by charging and discharging to capacitor,
The duty ratio of second clock signal is detected, the capacitor of main circuit is adjustable condenser, and the size of this adjustable condenser can basis
The adjustment of process corner detection unit.It detects signal receiving end and receives detection enable signal EN, to control the unlatching of duty detection circuit 3
Or shutdown, it may be assumed that it is in detecting state or idle state that EN signal, which mainly controls duty detection circuit,.When EN is 1, duty
It is in detecting state than detection circuit 3, when EN is 0, duty detection circuit 3 is in idle condition.Latch cicuit passes through clock
Signal output end linkage counter 4, the latch cicuit is for receiving MCLK and/MCLK signal in main circuit, to control capacitor member
The charging and discharging of part, MCLK and the/respective duty ratio of MCLK form plus-minus instruction INC and DEC, and export UP and DN signal to
Connect counter 4.Counter 4 carries out it to count and gives count results to time delay chain 1, so that time delay chain 1 determines access circuit
Delay unit number.
Each signal of above-mentioned duty detection circuit 3 can be transmitted by metal-oxide-semiconductor, when operation level variation, phase
Induction signal can access or disconnect the circuit.For example, as shown in Fig. 2, clock signal receiving end includes NMOS tube, in height
Clock signal MCLK and/MCLK are conducted to main circuit when level, detection signal receiving end includes PMOS tube, in high level
When will test enable signal EN and be conducted to main circuit.
In one embodiment, adjustable condenser may include multiple tunable capacitor circuits being connected in parallel, each tunable capacitor electricity
Road may include capacity cell and with the concatenated switch element of capacity cell, the capacitance of this capacity cell can be fixed value；Wherein,
Each switch element can be connect with decoding circuit 7, and decoding circuit 7 is used to convert output signal for the encoded signal and according to defeated
Signal adjusts the on off operating mode of each switch element out, so that the number of capacity cell in access duty detection circuit 3 is controlled, with
Adjust the capacitance of adjustable condenser.
In another embodiment, adjustable condenser can include nonadjustable condenser network and multiple above-mentioned adjustable electrics simultaneously
Capacitive circuit reduces complex circuit degree under the premise of meeting adjustment demand, reduces Setup Cost.
In the present embodiment, by directly designing multiple tunable capacitor circuits at the beginning of circuit design, according to process corner detection
The technique angular dimensions adjustment of unit detection is incorporated to the number of circuit, the adjustment of capacitance not only may be implemented, but also can satisfy
Wider or more accurate adjustment demand.Even if some capacity cell breaks down, there can also be other capacity cells work
For substitution, no replacement is required entire circuit structure reduces cost.
For example, in Fig. 4, the adjustable condenser of duty detection circuit 3 includes a fixed capacity M0 and three
Capacity cell M1, M2 and M3 (A and B in A and B corresponding diagram 3 in Fig. 2) in parallel with fixed capacity, M1, M2 and M3 respectively go here and there
It is associated with a switch element.Fixed capacity M0 provides basic capacitance, and three capacity cells M1, M2, M3 are for being adjusted, and four
The adjustment of total capacitance value is realized in capacitor collocation.
The embodiment joined three tunable capacitor circuits, and in other example embodiments, it can be added more
Tunable capacitor circuit can also include capacitor in each tunable capacitor circuit with only one or two tunable capacitor circuits
Element and switch element connected in series.Multiple tunable capacitor circuits can adjust duty detection circuit 3 in a wider context
Capacitor, to adapt to different process angular dimensions.Each capacity cell may be implemented not by respective switch element independent control
Same capacitance requirements, more accurately to calibrate duty ratio.
Wherein, the capacitance of each capacity cell may be the same or different, and those skilled in the art can be according to adjustment
The demand of precision and range carries out multiple combinations, and the utility model does not carry out particular determination to this.The utility model does not limit electricity
Hold the size and number of element.
In one embodiment, capacity cell can be metal-oxide-semiconductor, the grid connection switch element of metal-oxide-semiconductor.Pass through switch element control
The access of metal-oxide-semiconductor processed accesses metal-oxide-semiconductor charge or discharge under grid voltage of duty detection circuit 3, to realize duty ratio
Detection.
In this illustrative embodiments, metal-oxide-semiconductor can be PMOS tube or NMOS tube, as long as matching i.e. with circuit polarities
It can.As shown in 4 figures, in the duty detection circuit 3 of the present embodiment, the capacity cell in fixed capacity and tunable capacitor circuit is equal
For PMOS tube, the source electrode and drain electrode of each capacitor is connected to power end, and grid is connected to main circuit.Certainly, capacity cell can also be with
It is conventional capacitive.
In this illustrative embodiments, the switch element of tunable capacitor circuit may include the PMOS tube that is connected in parallel and
NMOS tube, PMOS tube and NMOS tube are connect with decoding circuit 7 respectively, and PMOS tube and NMOS tube are for receiving the sending of decoding circuit 7
Output signal.Wherein, two control terminals of metal-oxide-semiconductor and NMOS tube receive complementary output signal Ctl1 and/Ctl1 respectively,
PMOS tube connects tunable capacitor element with wherein one end of NMOS tube parallel connection, and the other end accesses main circuit, to realize varying level
To the charge or discharge of capacity cell when signal conduction.The output letter that Ctl1 and/Ctl1 signal are issued from decoding circuit 7
Number, the conducting and shutdown of this Ctl1 and/Ctl1 signal for control switch element, to adjust access duty detection circuit 3
Capacitance.
The utility model embodiment also provides a kind of memory, including any of the above duty-ratio calibrating circuit.This is deposited
The clock of reservoir can be always ensured that duty ratio in (50 ± 1) %, therefore the correctness for reading data is higher.
The utility model embodiment additionally provides a kind of method of adjustment of duty-ratio calibrating circuit, as shown in Figure 1, this duty
It include signal adjustment circuit and duty detection circuit 3 than calibration circuit, signal adjustment circuit is for receiving and adjusting memory
The first clock signal to generate second clock signal；3 connection signal adjustment circuit of duty detection circuit, for detecting second
The duty ratio of clock signal simultaneously will test result and feed back to signal adjustment circuit, and duty detection circuit 3 includes adjustable condenser；
The method of adjustment includes:
Step S10 detects the technique angular dimensions of memory；
Step S12 adjusts the capacitance of adjustable condenser according to technique angular dimensions.
In the present embodiment, the capacitance in duty detection circuit 3 can be adjusted to suitable for different technique angular dimensions
Work as range, it is too fast or excessively slow too late too early with capacitor element of the alleviation when process corner changes in duty detection circuit 3
The case where carrying out discharge operation, to improve the reliability and accuracy of duty detection circuit 3, can then guarantee to store
The duty ratio of device meets the requirement of (50 ± 1) %.
Wherein, in step S12 can include:
Step S120 encodes technique angular dimensions, to generate encoded signal；
Encoded signal is converted output signal by step S122；
Step S124 adjusts the capacitance of adjustable condenser according to output signal.
For example, this technique angular dimensions can be threshold voltage.
For example, this technique angular dimensions can be threshold voltage.Those skilled in the art are considering specification and are practicing this
In after disclosed utility model, will readily occur to other embodiments of the utility model.The utility model is intended to cover this reality
With novel any variations, uses, or adaptations, these variations, uses, or adaptations follow the utility model
General principle and including the undocumented common knowledge or conventional techniques in the art of the utility model.Explanation
Book and embodiment are considered only as illustratively, and the true scope and spirit of the utility model are pointed out by the attached claims.
Claims (9)
1. a kind of duty-ratio calibrating circuit characterized by comprising
Signal adjustment circuit, for receiving and adjusting the first clock signal to generate second clock signal；
Duty detection circuit connects the signal adjustment circuit, for detecting the duty ratio of the second clock signal and inciting somebody to action
Testing result feeds back to the signal adjustment circuit, and the duty detection circuit includes adjustable condenser；
Process corner detection unit is connect with the adjustable condenser, for detecting the technique angular dimensions of memory and according to described
Technique angular dimensions adjusts the capacitance of the adjustable condenser.
2. duty-ratio calibrating circuit according to claim 1, which is characterized in that the process corner detection unit includes:
Process corner detection circuit, for detecting the technique angular dimensions of the memory；
Coding circuit is encoded with the process corner detection circuit connection for encoding to the technique angular dimensions with generating
Signal；
Decoding circuit connects the coding circuit and the duty detection circuit, defeated for converting the encoded signal to
Signal and the capacitance of the adjustable condenser is adjusted according to the output signal out.
3. duty-ratio calibrating circuit according to claim 1, which is characterized in that the signal adjustment circuit includes:
Time delay chain, the time delay chain have the first delay receiving end, the second delay receiving end and delay output end, and described first prolongs
When receiving end for receiving first clock signal, the time delay chain can be delayed with life to first clock signal
At adjustment clock signal, the delay output end is for exporting the adjustment clock signal, the second delay receiving end and institute
State the clock signal output terminal connection of duty detection circuit；
Clock generator, the clock generator have the first clock receiving end, second clock receiving end and output terminal of clock, institute
It states the first clock receiving end and connects for receiving first clock signal, the second clock receiving end and the delay output end
The adjustment clock signal is connect and is used to receive, the clock generator can be according to first clock signal and the adjustment
Clock signal generates the second clock signal, the output terminal of clock for exporting the second clock signal, and it is described when
Clock output end is connect with the clock signal receiving end of the duty detection circuit.
4. duty-ratio calibrating circuit according to claim 3, which is characterized in that it further include counter, the duty ratio inspection
The clock signal output terminal of slowdown monitoring circuit is connect by the counter with second delay receiving end.
5. duty-ratio calibrating circuit according to claim 2, which is characterized in that
The adjustable condenser includes multiple tunable capacitor circuits being connected in parallel, and each tunable capacitor circuit includes capacitor member
Part and with the concatenated switch element of the capacity cell, each switch element connect with the decoding circuit；
The decoding circuit is used to convert the encoded signal to output signal and is adjusted according to the output signal each described
The on off operating mode of switch element, to adjust the capacitance of the adjustable condenser.
6. duty-ratio calibrating circuit according to claim 5, which is characterized in that capacitor member in each tunable capacitor circuit
The capacitance of part is identical or different.
7. duty-ratio calibrating circuit according to claim 5, which is characterized in that the capacity cell is metal-oxide-semiconductor, described
The grid of metal-oxide-semiconductor connects the switch element.
8. duty-ratio calibrating circuit according to claim 5, which is characterized in that the switch element includes being connected in parallel
PMOS tube and NMOS tube, the PMOS tube and the NMOS tube are connect with the decoding circuit respectively, the PMOS tube and described
NMOS tube is for receiving the output signal.
9. a kind of memory, which is characterized in that including duty-ratio calibrating circuit described in any item of the claim 1 to 8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821837184.7U CN208861670U (en) | 2018-11-08 | 2018-11-08 | Duty-ratio calibrating circuit and memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821837184.7U CN208861670U (en) | 2018-11-08 | 2018-11-08 | Duty-ratio calibrating circuit and memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995217A (en) * | 2019-12-03 | 2020-04-10 | 芯创智（北京）微电子有限公司 | Duty ratio adjusting circuit |
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2018
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995217A (en) * | 2019-12-03 | 2020-04-10 | 芯创智（北京）微电子有限公司 | Duty ratio adjusting circuit |
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