CN208834135U - A kind of intelligence weighing data acquisition device - Google Patents
A kind of intelligence weighing data acquisition device Download PDFInfo
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- CN208834135U CN208834135U CN201821255292.3U CN201821255292U CN208834135U CN 208834135 U CN208834135 U CN 208834135U CN 201821255292 U CN201821255292 U CN 201821255292U CN 208834135 U CN208834135 U CN 208834135U
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- high speed
- data acquisition
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Abstract
The utility model discloses a kind of intelligent weighing data acquisition devices, including weighing data Acquisition Circuit and small signal deteching circuit, the input terminal of the weighing data Acquisition Circuit receives the sensor signal of small signal deteching circuit, the input terminal of the small signal deteching circuit is connected with sensor signal input circuit, the weighing data Acquisition Circuit includes the first high speed amplifier, second high speed amplifier and digital analog converter, the output end of first high speed amplifier is connected by second resistance with the reverse side of the second high speed amplifier, the output end of second high speed amplifier is connected by the 4th resistance with digital analog converter, the output end of the digital analog converter is connected with FPGA controller, whole device optimizes circuit design and timing Design, small signal detection module can be calibrated, and high-ranking officers on time obtain It adjusts mark coefficient to be stored in storage chip, improves sampling precision, realize the function of weighing data acquisition.
Description
Technical field
The utility model relates to data acquisition device technical field, in particular to a kind of intelligent weighing data acquisition device.
Background technique
The today to deepen continuously with digitizing technique, data acquisition technology have become important in signal processing
Link, it is all that data acquisition technology has been widely used for radar, sonar, transient signal test, intelligence weighing, Aeronautics and Astronautics etc.
It is multi-field, with data acquisition technology apply continuous intensification, not only to the acquisition precision of data acquisition device, acquisition speed and
Data volume has higher requirement, also requires data acquisition device that can reliably work under various environmental conditions.
Existing intelligence meausring apparatus is applied in all trades and professions, still, when intelligent meausring apparatus is weighing some volumes
When small, light weight article, since the intensity of weight signal is weaker, the measurement accuracy of data acquisition device is easy to be affected,
So that intelligent meausring apparatus error when weighing the object of light weight is larger, practicability weakens.
Utility model content
The technical problem to be solved by the present invention is to provide a kind of intelligent weighing data acquisition devices, have measurement, control
The functions such as system, monitoring, improve sampling precision, realize the function of weighing data acquisition, can effectively solve background skill in this way
The problems in art.
In order to solve the above-mentioned technical problem, the technical solution of the utility model are as follows: a kind of intelligence weighing data acquisition device,
Including weighing data Acquisition Circuit and small signal deteching circuit, the input terminal of the weighing data Acquisition Circuit receives small signal inspection
The sensor signal of slowdown monitoring circuit, the input terminal of the small signal deteching circuit are connected with sensor signal input circuit, the title
Measuring data acquisition circuit includes the first high speed amplifier, the second high speed amplifier and digital analog converter, and first high speed is amplified
The positive terminal of device is connected with input signal cable by first resistor, the reverse side feedback link of first high speed amplifier to
The output end of the output end of one high speed amplifier, first high speed amplifier passes through second resistance and the second high speed amplifier
Reverse side is connected, and the reverse side of second high speed amplifier also passes through 3rd resistor and is connected with its output end, and described
The output end of two high speed amplifiers is connected by the 4th resistance with digital analog converter, the oppisite phase data end of the digital analog converter
It is also directly grounded by first capacitor, the reverse phase reference end of the digital analog converter is connected with the 5th resistance, the 5th resistance
The positive terminal for being connected separately with the 6th resistance and the second high speed amplifier, the other end and digital analog converter of the 6th resistance
In-phase data end be connected, the in-phase data end of the digital analog converter also passes through the second capacitor and is directly grounded, the digital-to-analogue
The same phase reference end of converter also passes through the 7th resistance and is connected with its in-phase data end, and the output end of the digital analog converter connects
It is connected to FPGA controller；
The small signal deteching circuit includes the first operational amplifier and second operational amplifier, first operation amplifier
The output end of device is connected with second operational amplifier, and the output end of the second operational amplifier is connected with by the 8th resistance
Third capacitor, the other end of the 8th resistance are also connected with output signal line, and the other end of the third capacitor is directly grounded.
As the utility model a preferred technical solution, the non-inverting input terminal of first operational amplifier connects respectively
It is connected to the first filter capacitor and the first divider resistance, the first filter capacitor other end is directly grounded, the first partial pressure electricity
The other end of resistance is connected separately with the second filter capacitor and the second divider resistance, and the other end of second filter capacitor, which is fed back, to be connected
It is connected to the output end of the first operational amplifier, the other end of second divider resistance is connected separately with third filter capacitor and
The other end of three divider resistances, the third filter capacitor is directly grounded, and the other end of the third divider resistance is connected with defeated
Enter signal wire.
As the utility model a preferred technical solution, the in-phase end of first operational amplifier is connected with relay
The other end of device, the relay is directly grounded by the 9th resistance, and the in-phase end of first operational amplifier also passes through
Ten resistance feedbacks are connected to the output end of the first operational amplifier, and the 8th pin of first operational amplifier is connected with electricity
Source, the 8th pin of first operational amplifier also pass through the 4th capacitor and are directly grounded, and the of first operational amplifier
Four pins are directly grounded by the 5th capacitor.
As the utility model a preferred technical solution, the backward voltage end of the second operational amplifier passes through the
Six capacitors are directly grounded, and the in-phase voltage end of the second operational amplifier is directly grounded by the 7th capacitor.
As the utility model a preferred technical solution, the data terminal of the FPGA controller is also connected with storage battle array
Column, the peripheral port of the FPGA controller are connected with FIFO drive module, and the bus port of the FPGA controller passes through interior
Portion's bus is connected with power management chip, and the output end of the power management chip is connected with sensor signal input circuit.
By adopting the above technical scheme, by reasonably choose high speed, high-precision, wide temperature range analog-digital converter, it is excellent
Change the circuit design and timing Design of data acquisition device, and constitutes Butterworth using small signal deteching circuit internal element
Filter, retaining 50 subharmonic, that is, filter by frequency is 50KHz, can be calibrated to small signal detection module, and
The tune mark coefficient that high-ranking officers obtain on time is stored in storage chip, improves sampling precision, realizes the function of weighing data acquisition
Energy.
Detailed description of the invention
Fig. 1 is the utility model modular structure schematic diagram；
Fig. 2 is the small signal deteching circuit figure of the utility model；
Fig. 3 is the utility model weighing data Acquisition Circuit figure；
In figure, 1- weighing data Acquisition Circuit；The small signal deteching circuit of 2-；3- sensor signal input circuit；4-FPGA
Controller；5-FIFO drive module；6- storage array；7- power management chip.
Specific embodiment
Specific embodiment of the present utility model is described further with reference to the accompanying drawing.It should be noted that
The explanation of these embodiments is used to help to understand the utility model, but does not constitute the restriction to the utility model.This
Outside, technical characteristic involved in the various embodiments of the present invention described below is as long as they do not conflict with each other
It can be combined with each other.
It please refers to Fig.1 to Fig.3, the utility model provides a kind of technical solution: a kind of intelligence weighing data acquisition device, packet
Weighing data Acquisition Circuit 1 and small signal deteching circuit 2 are included, the input terminal of the weighing data Acquisition Circuit 1 receives small signal
The input terminal of the sensor signal of detection circuit 2, the small signal deteching circuit 2 is connected with sensor signal input circuit 3, institute
Stating weighing data Acquisition Circuit 1 includes the first high speed amplifier A1, the second high speed amplifier A2 and digital analog converter ADC, described
The positive terminal of first high speed amplifier A1 is connected with input signal cable, the first high speed amplifier A1 by first resistor R1
Reverse side feedback link to the output end of the first high speed amplifier A1, the output end of the first high speed amplifier A1 passes through the
Two resistance R2 are connected with the reverse side of the second high speed amplifier A2, and the reverse side of the second high speed amplifier A2 also passes through
Three resistance R3 are connected with its output end, and the output end of the second high speed amplifier A2 passes through the 4th resistance R4 and digital-to-analogue conversion
Device ADC is connected, and the oppisite phase data end of the digital analog converter ADC also passes through first capacitor C1 and is directly grounded GND, the number
The reverse phase reference end of mode converter ADC is connected with the 5th resistance R5, and the 5th resistance R5's is connected separately with the 6th resistance R6
With the positive terminal of the second high speed amplifier A2, the other end of the 6th resistance R6 and the in-phase data end of digital analog converter ADC
It is connected, the in-phase data end of the digital analog converter ADC also passes through the second capacitor C2 and is directly grounded GND, the digital-to-analogue conversion
The same phase reference end of device ADC also passes through the 7th resistance R7 and is connected with its in-phase data end, the output of the digital analog converter ADC
End is connected with FPGA controller 4, and the data terminal of the FPGA controller 4 is also connected with storage array 6, the FPGA controller 4
Peripheral port be connected with FIFO drive module 5, the bus port of the FPGA controller 4 is connected with power supply by internal bus
The output end of managing chip 7, the power management chip 7 is connected with sensor signal input circuit 3.
The small signal deteching circuit 2 includes the first operational amplifier S1 and second operational amplifier S2, first fortune
The output end for calculating amplifier S1 is connected with second operational amplifier S2, and the output end of the second operational amplifier S2 passes through the
Eight resistance R8 are connected with third capacitor C3, and the other end of the 8th resistance R8 is also connected with output signal line, the third electricity
The other end for holding C3 is directly grounded GND, and the non-inverting input terminal of the first operational amplifier S1 is connected separately with the first filtered electrical
Hold C11 and the first divider resistance R11, the first filter capacitor C11 other end are directly grounded GND, first divider resistance
The other end of R11 is connected separately with the second filter capacitor C12 and the second divider resistance R12, the second filter capacitor C12's
To the output end of the first operational amplifier S1, the other end of the second divider resistance R12 is separately connected other end feedback link
There are third filter capacitor C13 and third divider resistance R13, the other end of the third filter capacitor C13 is directly grounded GND, institute
The other end for stating third divider resistance R13 is connected with input signal cable, and the reverse side of the first operational amplifier S1 is connected with
The other end of relay D1, the relay D1 are directly grounded GND by the 9th resistance R9, the first operational amplifier S1's
Reverse side also passes through the tenth resistance R10 feedback link to the output end of the first operational amplifier S1, first operational amplifier
The 8th pin of S1 is connected with power supply VCC, and it is direct that the 8th pin of the first operational amplifier S1 also passes through the 4th capacitor C4
It is grounded GND, the 4th pin of the first operational amplifier S1 is directly grounded GND, second operation by the 5th capacitor C5
The backward voltage end of amplifier S2 is directly grounded GND, the in-phase voltage of the second operational amplifier S2 by the 6th capacitor C6
End is directly grounded GND by the 7th capacitor C7.
In the present embodiment, Acquisition Circuit is weighed by signal conditioning circuit, single-ended transfer difference circuit and analog to digital conversion circuit structure
At the function of signal conditioning circuit is to carry out amplifier to input signal to follow conditioning and interface protection, and first resistor R1 is to connect
Input signal is switched to differential signal, meets the digital analog converter of THS1408 model by mouth protective resistance, single-ended transfer difference circuit
The input request signal of ADC conversion, analog to digital conversion circuit are as follows: fpga chip controls THS1408 and completes analog-to-digital conversion part.
In the present embodiment, small signal deteching circuit 2 uses quasi-synchro sampling mode, utilizes the first filter capacitor C11, first
Divider resistance R11, the second filter capacitor C12, the second divider resistance R12, third filter capacitor C13, third divider resistance R13,
Constitute Butterworth filter；Retain the i.e. filter of 50 subharmonic by frequency be 50KHz, can be to small signal detection module
It is calibrated, and the tune mark coefficient that high-ranking officers obtain on time is stored in flash storage chip, improves sampling precision.
Working principle of the utility model is: the weighing signal of input is the electricity converted by sensor when specifically used
It presses analog signal (0~5V), voltage signal enters small signal deteching circuit 2 by sensor signal input interface, after conditioning
Input signal is converted to differential signal, weighing data acquisition after the single-ended transfer difference circuit before weighing data Acquisition Circuit 1
Circuit 1 carries out analog-to-digital conversion under the logic control of FPGA chip, by differential signal, in the digital quantity process after analog-to-digital conversion
Portion's program buffers into external FIFO after carrying out data processing, then the valid data in FIFO are compiled frame, are stored in 16Gflash
In storage array, weighing data acquisition device by bus interface carry out communication between plates, receive host computer instruction, upload data and
Unit state, entire Acquisition Circuit is easy to accomplish, and power consumption is lower, can satisfy sampling precision requirement.
The embodiments of the present invention is explained in detail in conjunction with attached drawing above, but the utility model is not limited to be retouched
The embodiment stated.For a person skilled in the art, right in the case where not departing from the utility model principle and spirit
These embodiments carry out a variety of change, modification, replacement and modification, still fall in the protection scope of the utility model.
Claims (5)
1. a kind of intelligence weighing data acquisition device, including weighing data Acquisition Circuit (1) and small signal deteching circuit (2),
Be characterized in that: the input terminal of the weighing data Acquisition Circuit (1) receives the sensor signal of small signal deteching circuit (2), institute
The input terminal for stating small signal deteching circuit (2) is connected with sensor signal input circuit (3), the weighing data Acquisition Circuit
It (1) include the first high speed amplifier A1, the second high speed amplifier A2 and digital analog converter ADC, the first high speed amplifier A1
Positive terminal input signal cable is connected with by first resistor R1, the reverse side feedback link of the first high speed amplifier A1 arrives
The output end of the output end of first high speed amplifier A1, the first high speed amplifier A1 passes through the high speed of second resistance R2 and second
The reverse side of amplifier A2 is connected, and the reverse side of the second high speed amplifier A2 also passes through 3rd resistor R3 and its output end
It is connected, the output end of the second high speed amplifier A2 is connected by the 4th resistance R4 with digital analog converter ADC, the number
The oppisite phase data end of mode converter ADC also passes through first capacitor C1 and is directly grounded GND, the reverse phase ginseng of the digital analog converter ADC
It examines end and is connected with the 5th resistance R5, the 5th resistance R5's is connected separately with the 6th resistance R6's and the second high speed amplifier A2
The other end of positive terminal, the 6th resistance R6 is connected with the in-phase data end of digital analog converter ADC, the digital analog converter
The in-phase data end of ADC also passes through the second capacitor C2 and is directly grounded GND, and the same phase reference end of the digital analog converter ADC is also logical
It crosses the 7th resistance R7 to be connected with its in-phase data end, the output end of the digital analog converter ADC is connected with FPGA controller
(4)；
The small signal deteching circuit (2) includes the first operational amplifier S1 and second operational amplifier S2, first operation
The output end of amplifier S1 is connected with second operational amplifier S2, and the output end of the second operational amplifier S2 passes through the 8th
Resistance R8 is connected with third capacitor C3, and the other end of the 8th resistance R8 is also connected with output signal line, the third capacitor
The other end of C3 is directly grounded GND.
2. a kind of intelligent weighing data acquisition device according to claim 1, it is characterised in that: first operation amplifier
The non-inverting input terminal of device S1 is connected separately with the first filter capacitor C11 and the first divider resistance R11, first filter capacitor
The C11 other end is directly grounded GND, and the other end of the first divider resistance R11 is connected separately with the second filter capacitor C12 and
The other end feedback link of two divider resistance R12, the second filter capacitor C12 to the first operational amplifier S1 output end,
The other end of the second divider resistance R12 is connected separately with third filter capacitor C13 and third divider resistance R13, and described
The other end of three filter capacitor C13 is directly grounded GND, and the other end of the third divider resistance R13 is connected with input signal cable.
3. a kind of intelligent weighing data acquisition device according to claim 1, it is characterised in that: first operation amplifier
The reverse side of device S1 is connected with relay D1, and the other end of the relay D1 is directly grounded GND by the 9th resistance R9, described
The reverse side of first operational amplifier S1 also passes through the output end of the tenth resistance R10 feedback link to the first operational amplifier S1,
The 8th pin of the first operational amplifier S1 is connected with power supply VCC, and the 8th pin of the first operational amplifier S1 is also
It is directly grounded GND by the 4th capacitor C4, the 4th pin of the first operational amplifier S1 is directly connect by the 5th capacitor C5
Ground GND.
4. a kind of intelligent weighing data acquisition device according to claim 1, it is characterised in that: second operation amplifier
The backward voltage end of device S2 is directly grounded GND by the 6th capacitor C6, and the in-phase voltage end of the second operational amplifier S2 is logical
It crosses the 7th capacitor C7 and is directly grounded GND.
5. a kind of intelligent weighing data acquisition device according to claim 1, it is characterised in that: the FPGA controller
(4) data terminal is also connected with storage array (6), and the peripheral port of the FPGA controller (4) is connected with FIFO drive module
(5), the bus port of the FPGA controller (4) is connected with power management chip (7), the power management by internal bus
The output end of chip (7) is connected with sensor signal input circuit (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821255292.3U CN208834135U (en) | 2018-08-06 | 2018-08-06 | A kind of intelligence weighing data acquisition device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821255292.3U CN208834135U (en) | 2018-08-06 | 2018-08-06 | A kind of intelligence weighing data acquisition device |
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| Publication Number | Publication Date |
|---|---|
| CN208834135U true CN208834135U (en) | 2019-05-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821255292.3U Expired - Fee Related CN208834135U (en) | 2018-08-06 | 2018-08-06 | A kind of intelligence weighing data acquisition device |
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| Country | Link |
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| CN (1) | CN208834135U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110349353A (en) * | 2019-05-31 | 2019-10-18 | 浙江省人民医院 | A kind of harmful influence Intelligent management cabinet, management system and management method |
-
2018
- 2018-08-06 CN CN201821255292.3U patent/CN208834135U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110349353A (en) * | 2019-05-31 | 2019-10-18 | 浙江省人民医院 | A kind of harmful influence Intelligent management cabinet, management system and management method |
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| CF01 | Termination of patent right due to non-payment of annual fee |