CN2088256U

CN2088256U - Multifunctional digital velocimeter for locomotive

Info

Publication number: CN2088256U
Application number: CN 91214107
Authority: CN
Inventors: 郭忠义
Original assignee: Individual
Current assignee: Individual
Priority date: 1991-01-31
Filing date: 1991-01-31
Publication date: 1991-11-06

Abstract

The utility model relates to a digital locomotive speedometer which can carry out the display of speed and overspeed. The utility model is mainly composed of a sensing signal inputting interface, a pulse shaping circuit, a pulse generation circuit, a time control circuit, a timing device, a latch device, a decoding circuit and a displaying mechanism. Besides that a speed displaying mechanism is arranged in the displaying mechanism, an overspeed displaying mechanism controlled by an overspeed discrimination circuit can also be arranged, and accordingly, the utility model is characterized in that the digital locomotive speedometer can be used for many purposes.

Description

Multifunctional digital velocimeter for locomotive

The utility model relates to a kind of velocity measuring device, especially a kind of digital locomotive speedmeter.

A kind of velometer that uses on the existing locomotive constitutes by transducing signal input interface, three-phase bridge rectification, bleeder circuit and pointer magnetoelectricity series voltage table (dial plate mark velocity amplitude) are common.This velometer utilization be installed in locomotive wheel to the small-sized three-phase tech-generator on the axle as sensor, by the transducing signal input interface of showing to be provided with the winding of tech-generator is connected with the input end of three-phase bridge rectification, bleeder circuit.During locomotive operation, the voltage of three phase generator output, i.e. transducing signal, after bridge rectifier, bleeder circuit are handled, input magnetoelectricity series voltage table, and reading speed value thus.Because above-mentioned existing locomotive speedmeter adopts pointer machinery instrument reading, exist the error that the sum of errors that caused by machinery causes operation of analog quantity and conversion, so measuring accuracy is relatively poor.

The purpose of this utility model provides the multifunction digital locomotive speedmeter that a kind of measuring accuracy is higher, can realize exceeding the speed limit and show.

Velometer of the present utility model by transducing signal input interface, pulse shaping circuit, pulse combiner circuit, time control circuit, count, latch, decoding scheme and indication mechanism constitute.The input of pulse shaping circuit, output terminal connect the input end of transducing signal input interface and pulse combiner circuit respectively, the output termination of pulse combiner circuit is counted, is latched, the counting input end of decoding scheme, time control circuit connects counting, latchs, the counting of decoding scheme, latch, the zero clearing control end, count, latch, the input end of the output termination indication mechanism of decoding scheme.

In velometer of the present utility model, be connected with three phase winding extension lines as the three-phase synchronous tachometer generator of sensor by the transducing signal input interface.Behind the three-phase alternating voltage input speed table of tech-generator output, after the pulse shaping circuit shaping, form the three-phase pulse signal, by the pulse combiner circuit three-phase pulse signal is synthesized the monophasic pulses if signal again.Under the control of time control circuit, above-mentioned monophasic pulses if signal by some cycles input count, latch, decoding scheme, count, latch and decipher and drive indication mechanism work by this circuit pulse signals.In the utility model, indication mechanism may simply be the speed indication mechanism, promptly adopts the charactron display that velocity amplitude is carried out numeral and shows.Simultaneously, indication mechanism also can comprise the hypervelocity indication mechanism, promptly by count, latch, the output terminal that latchs of decoding scheme is provided with the hypervelocity judging circuit and by the hypervelocity display circuit of hypervelocity judging circuit control, realizes that further hypervelocities such as overspeed alarming, hypervelocity record show.The circuit that the hypervelocity judging circuit can adopt existing microcomputer chip to constitute, the comparison judging circuit that also can adopt the separate type integrated circuit to constitute.

Locomotive speedmeter of the present utility model and existing uniform machines vehicle speed epiphase ratio, because the error that does not exist sum of errors that machinery causes that operation of analog quantity and conversion are caused, so measuring accuracy is higher.In addition, owing to can further handle and utilization, realize hypervelocity demonstrations such as overspeed alarming, hypervelocity record, thereby have the characteristics of a-table-multi-purpose the speed metering signal.

Content of the present utility model is further described with the following Examples, but the content that the content that the utility model comprised is not limited among the embodiment to be comprised.

Fig. 1 is the circuit block diagram of locomotive speedmeter among the

embodiment

1,2.

Fig. 2 and Fig. 3 are the electrical schematic diagrams of embodiment 1.

Fig. 4 is the electrical schematic diagram of hypervelocity judging circuit among the embodiment 2.

Embodiment 1:

As shown in Figure 1, the locomotive speedmeter among the embodiment 1 by transducing signal input interface I, pulse shaping circuit II, pulse combiner circuit III, time control circuit IV, count, latch, decoding scheme V and indication mechanism constitute.In the present embodiment, indication mechanism comprises speed indication mechanism VI, hypervelocity judging circuit VII, hypervelocity record display circuit VIII, hypervelocity light warning display circuit IX and hypervelocity audible alarm display circuit X.Shown in Fig. 2-3, specifically being constructed as follows of each circuit stated in the present embodiment:

Among the embodiment 1, the pulse shaping circuit II mainly is made up of input current-limiting resistance R1, R2, R3, diode D1, D2, D3, triode BG1, BG2, BG3, phase inverter M1-1, the M1-2 of band application schmitt trigger, M1-3, differentiating circuit resistance R 7, R8, R9, capacitor C 1, C2, C3 etc.No. three pulse shaping circuits are separate in work, three phase inverter M1-1, M1-2, M1-3 are driven by transistor BG1, BG2, BG3, the output terminal of three phase inverters connects the input end of three RC differentiating circuit respectively, and the output terminal of three RC differentiating circuit is the output terminal of pulse shaping circuit.

Pulse combiner circuit III is made of three inputs or door integrated circuit M2-1, M2-2, the output terminal of its input termination pulse shaping circuit, and its output terminal is 11 ends of M2-2.Pulse combiner circuit in the present embodiment also can be made up of other circuit of identical function, as being made up of RC differentiating circuit and three input nand gate integrated circuit.

Time control circuit IV among the embodiment mainly is made of crystal oscillator, frequency divider and controller.Frequency divider and controller are made up of combination CMOS time control integrated circuit IC5, and crystal oscillator is made up of 148.24KHz crystal oscillator, resistance R 11 and capacitor C 4, C5.The input end 5,6 of the output termination IC5 of crystal oscillator, the

output terminal

11,15,10 of IC5 is the output terminal of time controller.In addition, the time control circuit among the embodiment also can be made of the controller that frequency dividing circuit and gate circuit are formed.

In the present embodiment, count, latch, decoding scheme V and shared four the CMOS-LED hybrid integrated circuit IC1 of velocity display circuit VI, IC2, IC3, IC4, with finish behind the radix point first and a position, ten, hundred counting, latch, decipher and show.Counting, latching, be provided with and a door integrated circuit M3-1 in the decoding scheme, connect in the pulse combiner circuit respectively with the

input end

1,2 of door M3-1 or the output terminal 11 of door M2-2 and time controller circuit in the output terminal 10 of IC5, connect the counting end 14 of IC1 with the output terminal 3 of door M3-1.Counting circuit adopts the multidigit cascade circuit, and promptly the carry end 13 of previous stage connects the counting end 15 of next stage, and be connected in series a lifting resistance R 10 between 14 ends of IC1 and power supply.The counting clear terminal 1 of IC1, IC2, IC3, IC4 and latch signal control end 2 connect the output terminal 11 and 15 of time controller IC5 respectively.Radix point control end 6 ground connection of IC1, IC3, IC4, the radix point control end 6 of IC2 connects power supply.CMOS-LED hybrid integrated circuit among the embodiment also can be counted by the corresponding separate type decimal system, latchs, decoder ic and charactron display circuit replace.

Among the embodiment 1, the hypervelocity judging circuit VII that is used to control the hypervelocity display circuit mainly is made of TTL code translator IC7, IC8, gate circuit M4-M7 and selector switch K60-K150, K05.The input end of TTL code translator IC8 connects counting respectively, latchs, the output terminal of ten Puzzle lock storage IC3 in the decoding scheme V.The output terminal of code translator IC8 is divided into two groups, respectively with each fixed contact 4 corresponding connections of two groups of plug-in type selector switch.7,9,10,11 output terminals that are IC8 correspond respectively to the K60-K90 switches set, and 1,2,3,4,5,6 output terminals of IC8 correspond respectively to the K100-K150 switches set.The purpose that grouping is provided with selector switch is to be convenient to ten and hundred signals are carried out juggling.The fixed contact 4 of each selector switch all can be connected with selecting contact 1 or 3 respectively by movable plug connector.When movable plug connector was plugged in unsettled contact 2 and select between the contact 3, fixed contact 4 was in vacant state.Each unsettled contact 2 all connects high level, to avoid interference.In the present embodiment, connect the input end of phase inverter M7-1 in the K60-K90 switches set behind selection contact 1 short circuit of each switch together, connect the input end of another phase inverter M7-2 in the K100-K150 switches set behind selection contact 1 short circuit of each switch together.The selection contact 3 of each switch connects the input end of Sheffer stroke gate M4-2 respectively in the K60-K90 switches set, and the selection contact 3 of each switch connects the input end of Sheffer stroke gate M5 respectively in the K100-K150 switches set.The output terminal of phase inverter M7-1, M7-2 and Sheffer stroke gate M5 connects the input end with door M6-2, M6-4, M6-3 respectively, with the output termination of door M6-2, M6-4, M6-3 or the input end of door M6-1.The output terminal of Sheffer stroke gate M4-2 directly connect or the door M6-1 input end.Or the output terminal of door M6-1 is the output terminal of hypervelocity judging circuit VII.The output terminal of phase inverter M7-1, M7-2 and Sheffer stroke gate M5 and or the input end of door M6-1 between the purpose that is provided with respectively with the door integrated circuit be further to differentiate the requirement whether output signal satisfies a place value or hundred place values.When not needing when only needing to judge ten place values individual place value or hundred place values are done further to judge, can with the output terminal of above-mentioned phase inverter and Sheffer stroke gate directly with or the input end of door M6-1 join.In the present embodiment,, be provided with a position judgment signal circuit that constitutes by TTL code translator IC7, Sheffer stroke gate M4-1 and selector switch K05 for whether individual place value is differentiated greater than 0 or 5.The output terminal of this position judgment signal circuit (fixed contact 3 of K switch 05) connects the input end with door M6-2, M6-4 respectively, by exporting a position judgment signal, controls the gating with door M6-2, M6-4.Simultaneously, count, latch, the output terminals A 4 of hundred Puzzle lock storage IC4 of decoding scheme is directly with being connected with the input end of door M6-3 and M6-4, by exporting hundred count signals, the gating of control M6-3, M6-4.

In embodiment 1, hypervelocity numeration display circuit VIII is mainly by forming with door integrated circuit M3-2, non-heavy triggering monostalbe trigger IC6, pulse-width regulated resistance R ext and capacitor C ext, transistor BG4, message register DJ15-5 and diode D4.Hypervelocity light warning display circuit IX is made up of current-limiting resistance R13, transistor BG5 and pilot lamp.Hypervelocity audible alarm display circuit X is mainly by multivibrator IC9, form with a door integrated circuit M3-3, transistor BG6, diode D5 and loudspeaker.

In the velometer of present embodiment, after the three-phase alternating voltage that tech-generator sends is delivered to the pulse shaping circuit II by transducing signal input interface I, the transistor switching circuit by pulse shaping circuit and the phase inverter of band application schmitt trigger are finished the pulse shaping to alternating voltage, and realize level conversion.After this, will be adjusted into narrow pulse signal corresponding to the wide pulse signal of different locomotive speeds through the RC differentiating circuit again, be sent to pulse combiner circuit III.

Be provided with in a pulse combiner circuit III or door integrated circuit M2 superposes to the three-phase narrow pulse signal, merges the monophasic pulses if signal that becomes standard, by the output terminal 11 of M2 deliver to counting, latch, the decoding scheme V.

Count, latch, the work of decoding scheme V is controlled by the time control circuit IV.Under the control of time control circuit, speed pulse signal is by delivering to the counting clock input end 14 of CMOS-LED integrated circuit (IC) 1 with the output terminal 3 of door M3-1, and count, latch, decipher by the cascade circuit that IC1, IC2, IC3, IC4 constitute, actuating speed shows.

The frequency of time control circuit IV is determined by crystal oscillating circuit.The frequency size of its crystal oscillating circuit can be chosen the right ratio of gear of diameter and tech-generator and wheel according to locomotive wheel.Crystal oscillator frequency is behind the internal circuit frequency division of IC5, by its

output terminal

10,15 and 11 output control pulses.In the present embodiment, the frequency of crystal oscillator is selected 148.24KHz for use.But selecting for use of crystal oscillator frequency is not limited in present embodiment, also can select the crystal oscillator of existing other frequency for use, and corresponding the carrying out of its output frequency used behind the frequency division.

In the present embodiment, the present speed value that IC2, IC3, IC4 latch is differentiated, shown with further realization hypervelocity by hypervelocity judging circuit VII.In embodiment 1, the fixed contact 4 of plug-in type selector switch K60, K70 is unsettled, and the fixed contact 4 of K80 is connected with selecting contact 1 by movable plug-in unit, and the fixed contact 4 of other selector switch K90-K150 is connected with selecting contact 3.At this moment, ten hypervelocity discriminant values determining are 80.When velocity amplitude was 0-59, " 0 " signal of being exported by IC8 passed through one of K110-K150 to Sheffer stroke gate M5, and produced " 1 " signals at its output terminal 8.After should " 1 " signal transporting to the input end 1 with door M6-3 because velocity amplitude is " 0 " less than 100, hundred signal output part A4, with the input end 2 of door M6-3 be " 0 ", with door M6-3 gating not, signal no longer forwards.When velocity amplitude is 60-79, deliver to the fixed contact 4 of K60, K70 by " 0 " signal of IC8 output, because of fixed contact 4 unsettled no longer outputs.When velocity amplitude was 80-89, " 0 " signal of IC8 output became " 1 " signal and transports to input end 11 with door M6-2 through K switch 80, phase inverter M7-1.If contact 1 is selected in fixed contact 3 selectings of K switch 05 in the places judging circuits, then when individual place value greater than 0 the time, will receive " 1 " signal with the input end 10 of door M6-2; If contact 2 is selected in fixed contact 3 selectings of K switch 05, then when individual place value greater than 5 the time, receive " 1 " signal with the input end 10 of door M6-2.Also that is to say,, will receive " 1 " signal, and make the M6-2 gating jointly with " 1 " signal that 11 ends are received with 10 ends of door M6-2 if velocity amplitude satisfies a condition that the position is differentiated, so by or the output terminal output overspeed signal " 1 " of door M6-1.When speed was 90-99, " 0 " signal by IC8 output became " 1 " signal through K90, Sheffer stroke gate M4-2, again warp or door M6-1 output overspeed signal " 1 ".When velocity amplitude is 100-159, " 0 " signal of IC8 output is identical when the transmittance process of K switch 100-K150, Sheffer stroke gate M5 is 0-59 with velocity amplitude, but this moment is because hundred count signal output terminals A 4 will be to importing " 1 " signals with the input end 2 of door M6-3, thereby make the M6-3 gating, again warp or door M6-1 output overspeed signal " 1 ".The inserting mode of plug-in type selector switch can be done conversion among the embodiment, thus the conversion speed limit.

By the overspeed signal (high level " 1 ") of M6-1 output deliver to hypervelocity record display circuit VIII with input end 5 door integrated circuit M3-2 after, when another input end 4 of M3-2 is received " 1 " pulse that 11 ends of time controller IC5 send, the output terminal 6 of M3-2 promptly applies a trigger pip to the input end of non-heavy triggering monostalbe trigger IC6, and drive the message register numeration thus, finish the hypervelocity record.Simultaneously, the overspeed signal of M6-1 output also will cause the transistor BG5 saturation conduction of hypervelocity light warning display circuit IX, and the hypervelocity pilot lamp is bright.Also will opening because of the input of overspeed signal with the integrated road M3-3 of door of hypervelocity audible alarm display circuit X, the sound signal that multivibrator IC9 produces is applied to the base stage of transistor BG6, drives loudspeaker and reports to the police.

Embodiment 2:

Present embodiment adopts the electrical schematic diagram shown in Figure 4 except that hypervelocity judging circuit VII, and the electrical schematic diagram of remaining circuit part all adopts the form shown in the embodiment 1.

As shown in Figure 4, in the present embodiment, hypervelocity judging circuit VII mainly is made of CMOS code translator IC10, IC11, gate circuit M8-M11 and selector switch K ' 60-K ' 130, K ' 05.The principle of work of circuit is similar to embodiment 1, and only the effective electric signal because of the output of CMOS code translator is " 1 " (effective electric signal of TTL code translator output is " 0 "), so the gate circuit in the circuit has been done corresponding change.In the present embodiment, the binary-coded decimal of CMOS code translator IC11 input termination count, latch, the output terminal of ten Puzzle lock storage IC3 in the decoding scheme.The output terminal of code translator IC11 is divided into two groups, respectively with two group selection K switch ' each fixed contact 4 of 60-K ' 90 and K ' 100-K ' 130 is connected.In K ' 60-K ' 90 switches set behind selection contact 1 short circuit of each switch with connect with the door M10-1 input end 2, in K ' 100-K ' 130 switches set behind selection contact 1 short circuit of each switch with connect with the door M10-3 input end 12.In K ' 60-K ' 90 switches set selection contact 3 of each switch connect respectively or the door M8-2 input end, in K ' 100-K ' 130 switches set selection contact 3 of each switch connect respectively or the door M9-1 input end.Or the output terminal of door M8-2 directly links to each other with the input end of another or door M9-2, or the input end of the output termination of door M9-1 and M10-2.With the output termination of door M10-1, M10-2, M10-3 or the input end of door M9-2, the output terminal of M9-2 is the overspeed signal output terminal of hypervelocity judging circuit.When velocity amplitude satisfies, during criterions such as ten, hundred, with one of door M10-1, M10-2, M10-3 can be by gating.Individual places judging circuits part in the present embodiment is by CMOS code translator IC10 or door M8-1, phase inverter M11 and K switch ' 05 formation, and it is to similar to embodiment 1 to the control principle of door 10-1, M10-3.

Claims

1, a kind of digital locomotive speedmeter, it is characterized in that this velometer is by transducing signal input interface (I), pulse shaping circuit (II), pulse combiner circuit (III), time control circuit (IV), counting, latch, decoding scheme (V) and indication mechanism constitute, the input of pulse shaping circuit (II), output terminal connects the input end of transducing signal input interface (I) and pulse combiner circuit (III) respectively, the output termination counting of pulse combiner circuit (III), latch, the counting input end of decoding scheme (V), time control circuit (IV) connects counting, latch, the counting of decoding scheme (V), latch, the zero clearing control end, counting, latch, the input end of the output termination indication mechanism of decoding scheme (V).

2, velometer as claimed in claim 1 is characterized in that the velocity display circuit (VI) that indication mechanism constitutes for the charactron display.

3, velometer as claimed in claim 1, it is characterized in that indication mechanism serve as reasons the hypervelocity judging circuit (VII) control hypervelocity display circuit (VIII, IX, X).

4, velometer as claimed in claim 3, it is characterized in that exceeding the speed limit judging circuit (VII) mainly by the TTL code translator, the selector switch group, phase inverter, the Sheffer stroke gate integrated circuit and or the door integrated circuit constitute, TTL code translator binary-coded decimal input termination counting, latch, counting latch output terminal in the decoding scheme, each end of at least one group of output terminal of TTL code translator respectively with a group selection switch in the corresponding connection of fixed contact (4) of each switch, the fixed contact of each selector switch (4) can by active connection respectively with select contact (1), one of (3) be connected or unsettled, connect the input end of a phase inverter on the same group behind the mutual short circuit of the selection contact (1) of interior selector switch together, the selection contact (3) of each selector switch connects the input end of a Sheffer stroke gate integrated circuit respectively on the same group, the output terminal of described phase inverter and Sheffer stroke gate integrated circuit directly or through the input end same with the door integrated circuit or the door integrated circuit of gating interlinks respectively, should or the control end of the output termination hypervelocity display circuit of door integrated circuit.

5, velometer as claimed in claim 3, it is characterized in that exceeding the speed limit judging circuit (VII) mainly by the CMOS code translator, the selector switch group and or the door integrated circuit constitute, the binary-coded decimal input termination counting of CMOS code translator, latch, the output terminal of counting latch in the decoding scheme, each end of at least one group of output terminal of CMOS code translator respectively with a group selection switch in the corresponding connection of fixed contact (4) of each switch, the fixed contact of each selector switch (4) all can by active connection respectively with select contact (1), one of (3) be connected or unsettled, the selection contact (3) of each selector switch connects one or the input end of door integrated circuit respectively on the same group, mutual the interlinking directly or behind gating behind the short circuit of the selection contact (1) of each selector switch on the same group with the input end of door integrated circuit with another or door integrated circuit, the output terminal of aforementioned or door integrated circuit also therewith or the input end of door integrated circuit join the control end of the output termination hypervelocity display circuit of this or door integrated circuit.