CN208767296U - Through silicon via detection circuit and IC chip - Google Patents
Through silicon via detection circuit and IC chip Download PDFInfo
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- CN208767296U CN208767296U CN201821451279.5U CN201821451279U CN208767296U CN 208767296 U CN208767296 U CN 208767296U CN 201821451279 U CN201821451279 U CN 201821451279U CN 208767296 U CN208767296 U CN 208767296U
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Abstract
The utility model discloses a kind of through silicon via detection circuit and IC chips, are related to technical field of integrated circuits.The through silicon via detection circuit includes the first through silicon via, the second through silicon via and phase discriminator；The first end of first through silicon via is connect with prearranged signals output end, and the second end of the first through silicon via is connect with the first end of the second through silicon via；The second end of second through silicon via and the first input end of phase discriminator connect；Second input terminal of phase discriminator is connect with prearranged signals output end；Wherein, phase discriminator is used to determine the phase difference between the signal of first input end of phase discriminator and the signal of the second input terminal.The disclosure can detecte out the through silicon via that fails, so that the mode based on through silicon via redundancy shields failure through silicon via, and then facilitate effective transmission of each signal in IC chip.
Description
Technical field
This disclosure relates to technical field of integrated circuits, in particular to a kind of through silicon via detection circuit and integrated circuit
Chip.
Background technique
With the extensive use of integrated circuit technique, the electronic equipments such as mobile phone, TV, plate, precision instrument have obtained height
Speed development.However, serious restriction of the integrated circuit technique by component size, function enhancing, cost-effectiveness etc..At this
In the case of kind, the appearance of three dimensional integrated circuits (3D IC) can be solved these problems preferably.
Three dimensional integrated circuits (3D IC) based on through silicon via (Through Silicon Via, TSV) will by through silicon via
Multilayer chiop is stacked, and due to using very short through silicon via instead of the long interconnection line in planar integrated circuit, makes its tool
Have many advantages, such as, such as low latency, low-power consumption, high-performance etc., so that it is wide to have the three dimensional integrated circuits based on through silicon via
Application prospect.
However, during through silicon via manufacturing process and through silicon via are bonded, due to the limitation of current process and material,
It is likely to result in the defect or failure of through silicon via.In entire integrated circuit, the failure of single through silicon via is normally resulted in entirely
The failure of three dimensional integrated circuits chip.Currently, preferable detection through silicon via whether there is the scheme of problem not yet.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Utility model content
The disclosure is designed to provide a kind of through silicon via detection circuit and IC chip, and then at least in certain journey
It solves the problems, such as to detect whether through silicon via fails currently without preferable scheme on degree.
According to one aspect of the disclosure, a kind of through silicon via detection circuit is provided, comprising: the first through silicon via, the second silicon are logical
Hole and phase discriminator；The first end of first through silicon via is connect with prearranged signals output end, the second end of the first through silicon via and the second silicon
The first end of through-hole connects；The second end of second through silicon via and the first input end of phase discriminator connect；Second input of phase discriminator
End is connect with prearranged signals output end；Wherein, phase discriminator is used to determine signal and the second input of the first input end of phase discriminator
Phase difference between the signal at end.
Optionally, the first through silicon via is connected to two or more stack layers with the second through silicon via.
Optionally, through silicon via detection circuit further includes first selector and the first distributor；Wherein, first selector has
First input end, the second input terminal, control terminal and output end, the first distributor have input terminal, control terminal, the first output end and
Second output terminal；The first input end of first selector is used to receive the first working signal of the first through silicon via to be entered, and first
Second input terminal of selector is connect with prearranged signals output end, and the control terminal of first selector is for receiving the first detection control
Signal, the output end of first selector are connect with the first end of the first through silicon via；The input terminal of first distributor and the first silicon are logical
The second end in hole connects, and for the control terminal of the first distributor for receiving the first detection control signal, the first of the first distributor is defeated
Outlet is connect with the first end of the second through silicon via, the second output terminal of the first distributor work member corresponding with the first working signal
Part connection.
Optionally, through silicon via detection circuit further includes third through silicon via；Wherein, the first end of third through silicon via and predetermined letter
The connection of number output end, the second end of third through silicon via are connect with the first end of the second through silicon via.
Optionally, through silicon via detection circuit further includes second selector and the second distributor；Wherein, second selector has
First input end, the second input terminal, control terminal and output end, the second distributor have input terminal, control terminal, the first output end and
Second output terminal；The first input end of second selector is used to receive the second working signal of third through silicon via to be entered, and second
Second input terminal of selector is connect with prearranged signals output end, and the control terminal of second selector is for receiving the second detection control
The output end of signal, second selector is connect with the first end of third through silicon via；The input terminal and third silicon of second distributor are logical
The second end in hole connects, and for the control terminal of the second distributor for receiving the second detection control signal, the first of the second distributor is defeated
Outlet is connect with the first end of the second through silicon via, the second output terminal of the second distributor work member corresponding with the second working signal
Part connection.
Optionally, through silicon via detection circuit further includes third selector and the 4th selector；Wherein, third selector and
Four selectors all have first input end, the second input terminal, control terminal and output end；The first input end of third selector and
The output end of one selector connects, and the second input terminal of third selector and the output end of second selector connect, third selection
The control terminal of device connects for receiving third detection control signal, the output end of third selector and the second input terminal of phase discriminator
It connects；The first input end of 4th selector is connect with the first output end of the first distributor, the second input terminal of the 4th selector
It being connect with the first output end of the second distributor, the control terminal of the 4th selector is detected for reception the 4th controls signal, and the 4th
The output end of selector is connect with the first end of the second through silicon via.
Optionally, through silicon via detection circuit further includes one in addition to the first through silicon via, the second through silicon via, third through silicon via
A or multiple through silicon vias；Wherein, the first end of each through silicon via and prearranged signals output end in one or more of through silicon vias
It connects, the second end of each through silicon via is connect with the first end of the second through silicon via in one or more of through silicon vias.
Optionally, stack layer belonging to the second end of the first through silicon via has delay phase-locked loop；Wherein, delay phase-locked loop is used
Delay compensation is carried out in working signal of the phase difference exported based on phase discriminator to the second end output of the first through silicon via.
Optionally, stack layer belonging to the second end of the first through silicon via has phase calibrator；Wherein, phase calibrator is used
Delay compensation is carried out in working signal of the phase difference exported based on phase discriminator to the second end output of the first through silicon via.
According to one aspect of the disclosure, a kind of IC chip is provided, the through silicon via inspection including above-mentioned any one
Slowdown monitoring circuit.
In the technical solution provided by some embodiments of the present disclosure, the through silicon via detection circuit of the disclosure can be applied
In the IC chip for including the first through silicon via and the second through silicon via, the first end and prearranged signals of the first through silicon via are exported
End connection, the second end of the first through silicon via are connect with the first end of the second through silicon via；Wherein, through silicon via detection circuit includes phase demodulation
Device, the first input end of the phase discriminator are connect with the second end of the second through silicon via, the second input terminal and prearranged signals of phase discriminator
Output end connection, the output end of phase discriminator are used to export the phase between the signal of first input end and the signal of the second input terminal
Difference.Through silicon via detection circuit described in the disclosure can by phase discriminator to prearranged signals and by the prearranged signals of through silicon via it
Between phase detected, to determine whether through silicon via fails.The disclosure can detecte out the through silicon via that fails as a result, to shield
It covers failure through silicon via and the failure through silicon via, Huo Zhetong is substituted using for example spare through silicon via based on the mode of through silicon via redundancy
It crosses to the delay phase-locked loop or phase calibrator of corresponding stack layer and sends instruction, to prolong to the signal via failure through silicon via
Compensation late to achieve the purpose that handle failure through silicon via, and then facilitates the effective of each signal in IC chip
Transmission.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure
Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.In the accompanying drawings:
Fig. 1 diagrammatically illustrates the circuit diagram of the through silicon via fault-tolerant networks of some technologies；
Fig. 2 shows the schematic diagrames according to the through silicon via detection circuits of the first illustrative embodiments of the disclosure；
Fig. 3 shows the schematic diagram of the through silicon via detection circuit of the second illustrative embodiments according to the disclosure；
Fig. 4 shows the schematic diagram of the through silicon via detection circuit of the third illustrative embodiments according to the disclosure；
Fig. 5 shows the schematic diagram of the through silicon via detection circuit of the 4th illustrative embodiments according to the disclosure；
Fig. 6 shows the schematic diagram of the through silicon via detection circuit of the 5th illustrative embodiments according to the disclosure；
Fig. 7 show according to an exemplary embodiment of the present disclosure after detecting through silicon via exception using delay phase-locked loop
To the schematic diagram for the scheme that phase compensates.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.In the following description, it provides perhaps
More details fully understand embodiment of the present disclosure to provide.It will be appreciated, however, by one skilled in the art that can
Omitted with technical solution of the disclosure it is one or more in the specific detail, or can be using other groups
Member, device etc..In other cases, known solution is not shown in detail or describes to avoid a presumptuous guest usurps the role of the host and makes the disclosure
Various aspects thicken.
In addition, attached drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale.Identical attached drawing mark in figure
Note indicates same or similar part, thus will omit repetition thereof.It should be understood that art described in the disclosure
Language " first ", " second ", " third ", " the 4th " are merely to the purpose distinguished, should not become the limitation of the disclosure.
Fig. 1 diagrammatically illustrates the circuit diagram of the through silicon via fault-tolerant networks of some technologies.From figure 1 it appears that working as
When any of TSV0 to TSV3 TSV fails, fault-tolerant purpose can be realized by spare through silicon via TSV8 or TSV9.So
And for how detecting through silicon via, current some technologies, which are conceived to, detects through-silicon via structure, to determine through silicon via
With the presence or absence of problem.And it is often more complicated for the detection process of through silicon via practical structures, and higher cost.
In consideration of it, present disclose provides a kind of through silicon via detection circuits.
The through silicon via detection circuit of first illustrative embodiments of the disclosure can be applied to include the first through silicon via and
In the IC chip of second through silicon via, wherein the first through silicon via and the second through silicon via all have first end and second end.?
In some embodiments, the first through silicon via and the second through silicon via may each be work when chip works normally for the transmission of interlayer signal
Make through silicon via.In further embodiments, the first through silicon via can be work through silicon via, and the second through silicon via can be logical based on silicon
The spare through silicon via of hole redundancy scheme can pass through when chip works normally in spare through silicon via without any signal.
In the following description, unless specifically indicated, otherwise it is considered that the second through silicon via is normal through silicon via, with right
The first through silicon via that may be failed is detected.
The first end of first through silicon via can be connect with prearranged signals output end, for receiving prearranged signals.Wherein, this is pre-
Determine signal can be one known to signal, for example, prearranged signals can be period and the determining square-wave signal of amplitude.So
And prearranged signals can also be other signals for test of such as sinusoidal signal, it is special that the disclosure does not do prearranged signals
It limits.In addition, the second end of the first through silicon via can be connect with the first end of the second through silicon via.
Specifically, the through silicon via detection circuit of the first illustrative embodiments of the disclosure may include phase discriminator (Phase
Detector, PD), phase discriminator is determined for being input to the phase difference between the signal of phase discriminator.Wherein, phase discriminator can be with
Including first input end, the second input terminal and output end.
The first input end of phase discriminator can be connect with the second end of the second through silicon via, and the second input terminal of phase discriminator can be with
It is connect with prearranged signals output end, the output end of phase discriminator is used to export the signal of first input end and the signal of the second input terminal
Between phase difference.
Below with reference to Fig. 2, the through silicon via detection circuit of the first illustrative embodiments of the disclosure is illustrated.
The first end of first through silicon via TSV1 can be connect with the output end (not shown) of prearranged signals IN0, for receiving
Prearranged signals IN0.The second end of first through silicon via TSV1 can be connect with the first end of the second through silicon via TSV2, for will be from the
The prearranged signals IN0 of one through silicon via TSV1 output is sent to the first end of the second through silicon via TSV2.
Prearranged signals IN0 can be sent to the first input end of phase discriminator PD by the second through silicon via TSV2.In addition, predetermined
Signal IN0 can be input to the second end of phase discriminator PD.In this case, phase discriminator PD can determine the letter of first input end
Phase difference number between the signal of the second input terminal, and the phase difference is exported by the output end of phase discriminator PD.
In some embodiments, if the phase difference that phase discriminator PD is determined is greater than a threshold value, first can be determined
Through silicon via is abnormal.The threshold value can voluntarily be configured according to the application scenarios of IC chip.Determining that the first through silicon via is different
In the case where often, it can compensate for example, by using signal phase or be entangled in such a way that other through silicon vias replace the first through silicon via
The problem of positive first through silicon via may cause extremely.
Using the through silicon via detection circuit of the disclosure, the through silicon via that fails can detecte out, to shield failure through silicon via simultaneously
The failure through silicon via is substituted using for example spare through silicon via based on the mode of through silicon via redundancy, or by corresponding stack layer
Delay phase-locked loop or phase calibrator send instruction, with to via failure through silicon via signal carry out delay compensation, to reach
To the purpose that failure through silicon via is handled, and then facilitate effective transmission of each signal in IC chip.
Embodiment shown in Fig. 2 is construed as only describing the scene of detection, that is to say, that discribed in Fig. 2
In circuit, there is not working signal when work to pass through the first through silicon via.Below with reference to Fig. 3 to the sheet that may exist operating mode
The circuit for disclosing the second illustrative embodiments is illustrated.Likewise, in the second illustrative embodiments of the disclosure, second
Through silicon via TSV2 is normal through silicon via.
With reference to Fig. 3, compared to circuit shown in Fig. 2, circuit shown in Fig. 3 is except may include the first through silicon via TSV1, the
It can also include first selector S1 and the first distributor F1 outside two through silicon via TSV2 and phase discriminator PD.Wherein, first selector
S1 have first input end, the second input terminal, control terminal and output end, the first distributor F1 can have input terminal, control terminal,
First output end and second output terminal.
Specifically, the first input end of first selector S1 can be used for receiving the first of the first through silicon via TSV1 to be entered
Working signal IN1；The second input terminal of first selector S1 can be connect with prearranged signals output end, for receiving prearranged signals
IN0；The control terminal of first selector S1 can be used for receiving the first detection control signal T1, and the first detection control signal T1 can
It is issued with being based on detection demand by a control circuit (not shown)；The output end of first selector S1 can be with the first through silicon via
The first end of TSV1 connects.
The input terminal of first distributor F1 is connect with the second end of the first through silicon via TSV1；The control terminal of first distributor F1
For receiving the control signal C1 for acting on the first distributor F1, in some instances, control signal C1 can be above-mentioned the
One detection control signal T1；The first output end of first distributor F1 is connect with the first end of the second through silicon via TSV2；First point
The operation element connection corresponding with the first working signal IN1 of the second output terminal of orchestration F1, sends output letter to the operation element
Number OUT1.Wherein, operation element can for example refer to storage unit (bank) in corresponding stack layer, have signal processing function
Logic unit etc..
As shown in figure 3, come control circuit be in detection pattern by the first detection control signal T1
Operating mode.In a detection mode, first selector S1 can control signal T1 to the first through silicon via TSV1 based on the first detection
Prearranged signals IN0 is exported, in this case, the control signal C1 of the first distributor F1 can be with the first of first selector S1
Detection control signal T1 is identical, so that the first through silicon via TSV1 output signal can be sent to the second through silicon via TSV2, with
Just phase discriminator PD can determine the phase difference between the signal of prearranged signals IN0 and the second through silicon via TSV2 output.
In addition, in the operational mode, first selector S1 can control signal T1 to the first through silicon via based on the first detection
TSV1 exports the first working signal IN1, in this case, can will be via the based on control signal C1, the first distributor F1
The first working signal IN1 of one through silicon via TSV1 is exported to corresponding operation element.
By circuit shown in Fig. 3, the switching of detection pattern and operating mode can be realized based on control signal.
In the through silicon via detection circuit of the third illustrative embodiments of the disclosure, corresponding through silicon via detection circuit is also
It may include third through silicon via.The first end of third through silicon via can be connect with prearranged signals output end, and the of third through silicon via
Two ends can be connect with the first end of the second through silicon via.Likewise, the second silicon is logical in disclosure third illustrative embodiments
Hole is normal through silicon via.
Existing first through silicon via in the third illustrative embodiments of the disclosure has the scene of third through silicon via again under,
Can use signaling control unit control prearranged signals flows through path.Specifically, as shown in figure 4, to the first through silicon via
In the case where being detected, signaling control unit (not shown) can be the case where controlling prearranged signals IN0 input phase discriminator PD
Under, it only controls prearranged signals IN0 and exports to the first through silicon via TSV1 without exporting to third through silicon via TSV3；Logical to third silicon
In the case that hole is detected, signaling control unit can only be controlled in the case where controlling prearranged signals IN0 input phase discriminator PD
Prearranged signals IN0 processed is exported to third through silicon via TSV3 without exporting to the first through silicon via TSV1.Thus, it is possible to realize not
With the effect for testing different through silicon vias in situation.
In the through silicon via detection circuit of the 4th illustrative embodiments of the disclosure, through silicon via detection circuit can also be wrapped
Include second selector and the second distributor；Wherein, second selector has first input end, the second input terminal, control terminal and defeated
Outlet, the second distributor have input terminal, control terminal, the first output end and second output terminal.Likewise, showing in the disclosure the 4th
In example property embodiment, the second through silicon via is normal through silicon via.
Specifically, the first input end of second selector S2 can be used for receiving third through silicon via to be entered with reference to Fig. 5
The second input terminal of the second working signal IN3 of TSV3, second selector S2 can be connect with prearranged signals output end, the second choosing
The control terminal for selecting device S2 can be used for receiving the second detection control signal T2, and the output end of second selector S2 can be with third silicon
The first end of through-hole TSV3 connects.
The input terminal of second distributor F2 can be connect with the second end of third through silicon via TSV3, the control of the second distributor F2
End processed can be used for receiving the second detection control signal C2, and the first output end of the second distributor F2 can be with the second through silicon via
The first end of TSV2 connects, and the second output terminal of the second distributor F2 can work corresponding with the second working signal IN3
Element connection.
It is similar with third illustrative embodiments shown in Fig. 4, the through silicon via of the 4th illustrative embodiments of the disclosure
Detection circuit can use signaling control unit control prearranged signals and flow through path, and details are not described herein again.
In the through silicon via detection circuit of the 5th illustrative embodiments of the disclosure, it is logical to exist concurrently with above-mentioned first silicon
In the case where hole and third through silicon via, can be controlled by control device the connection status of the first through silicon via and the second through silicon via with
And the connection status of third through silicon via and the second through silicon via.Likewise, in the 5th illustrative embodiments of the disclosure, the second silicon
Through-hole is normal through silicon via.
Specifically, through silicon via detection circuit can also include third selector and the 4th selector, wherein third selector
First input end, the second input terminal, control terminal and output end are all had with the 4th selector.
It is illustrated below with reference to through silicon via detection circuit of the Fig. 6 to the 5th illustrative embodiments of the disclosure.
The first input end of third selector S3 can be connect with the output end of first selector S1；Third selector S3's
Second input terminal can be connect with the output end of second selector S2；The output end of third selector S3 can be with phase discriminator PD's
The connection of second input terminal；The control terminal of third selector S3 can be used for receiving third detection control signal T3, work as determination
Before be the first through silicon via TSV1 is carried out detect or third through silicon via TSV3 is detected.
The first input end of 4th selector S4 can be connect with the first output end of the first distributor F1；4th selector
The second input terminal of S4 can be connect with the first output end of the second distributor F2；The output end of 4th selector S4 can be with
The first end of two through silicon via TSV2 connects；The control terminal of 4th selector S4 can be used for receiving the 4th detection control signal T4,
It is currently to carry out detecting or detecting third through silicon via TSV3 to the first through silicon via TSV1 for determination.
It should be understood that the same time can only detect a through silicon via in circuit shown in Fig. 6.?
That is in some scenes, when first selector S1 sends prearranged signals IN0 to the first through silicon via TSV1, the second selection
Device S2 sends third working signal IN3 to third through silicon via TSV3；Under other scenes, in first selector S1 to the first silicon
When through-hole TSV1 sends the first working signal IN1, second selector S2 sends prearranged signals IN0 to third through silicon via TSV3.
In addition, being the first through silicon via TSV1 or third through silicon via TSV3 according to the target of detection, first selector S1 connects
Control signal T1, the received control signal C1 of the first distributor F1, the received control signal T2 of second selector S2, second of receipts
The received control signal C2 of distributor F2, the received control signal T3 of third selector S3 and the 4th received control of selector S4
There are corresponding relationships by signal T4 processed.
For example, first selector S1 can be by controlling signal in the example detected to the first through silicon via TSV1
T1 exports prearranged signals IN0；First distributor F1 can pass through the first silicon to the 4th selector S4 input by control signal C1
The prearranged signals IN0 of through-hole TSV1；Second selector S2 can export third working signal IN3 to third by control signal T2
Through silicon via TSV3；Second distributor F2 can be worked by the third of control signal C2 output experience third through silicon via TSV3 to be believed
Number IN3, is denoted as OUT3；The prearranged signals that third selector S3 can will be exported by controlling signal T3 from first selector S1
IN0 is sent to phase discriminator PD；The signal that 4th selector S4 can will be inputted by controlling signal T4 via the first distributor F1
It is sent to the second through silicon via TSV2, and then is input to phase discriminator PD.
For another example, in the example detected to third through silicon via TSV3, first selector S1 can be by controlling signal
T1 exports the first working signal IN1；First distributor F1 can pass through the first through silicon via TSV1's of control signal C1 output experience
First working signal IN1, is denoted as OUT1；Second selector S2 can export prearranged signals IN0 by control signal T2；Second point
Orchestration F2 can pass through the prearranged signals IN0 of third through silicon via TSV3 by control signal C2 to the 4th selector S4 input；The
The prearranged signals IN0 exported from second selector S2 can be sent to phase discriminator PD by control signal T3 by three selector S3；
The signal inputted via the second distributor F2 can be sent to the second through silicon via by control signal T4 by the 4th selector S4
TSV2, and then it is input to phase discriminator PD.
Circuit shown in fig. 6 describes the case where there are third through silicon vias in addition to the first through silicon via and the second through silicon via.
It is easily understood that through silicon via detection circuit can also include except the first through silicon via, the second silicon are logical according to other embodiment
One or more through silicon vias except hole, third through silicon via.Wherein, in one or more of through silicon vias each through silicon via
One end can be connect with prearranged signals output end, and the second end of each through silicon via can be in one or more of through silicon vias
The first end of two through silicon vias connects.Specifically, can be controlled by multiple selectors and distributor, it is currently with determination
Which through silicon via is detected, detailed process is similar to above, and those skilled in the art can be according to above-mentioned design come really
The scheme of multiple through silicon vias to be detected is made, details are not described herein.
It should be noted that the second through silicon via is the through silicon via of normal non-fault in above embodiment.In addition,
In the case that second through silicon via fails, can also judge whether are the first through silicon via or third through silicon via using the design of the disclosure
Failure.For example, one end of the first through silicon via can be connected phase discriminator, separately in the case where determining the normal situation of the first through silicon via
Whether one end is connected to one end of third through silicon via output signal, normal to detect third through silicon via；Determining that third silicon is logical
In the normal situation in hole, one end of third through silicon via can be connected to phase discriminator, the other end is connected to the output of the first through silicon via
One end of signal, it is whether normal to detect the first through silicon via.Specific connection relationship is similar with above example, no longer superfluous herein
It states.
According to some embodiments of the present disclosure, the signal of the first input end of phase discriminator and second defeated is determined in phase discriminator
After entering the phase difference between the signal at end, the phase difference can be exported.
Fig. 7 shows the example of an application scenarios after determining phase difference.With reference to Fig. 7, IC chip can be with
Including silicon intermediary layer, the first stack layer, the second stack layer and third stack layer.Wherein, each stack layer may each comprise several
A (for example, 4) storage unit (bank).For example, the memory capacity of the first stack layer be 8GB, then it includes four storage
The capacity of unit can be 2GB.
First stack layer, the second stack layer, third stack layer can carry out the transmitting of information by through silicon via between any two.
By taking the first stack layer and the second stack layer carry out information transmitting as an example, after phase discriminator (being not shown in Fig. 7) determines phase difference,
In the available phase difference that is based on of the delay phase-locked loop (Delay Lock Loop, DLL) of the second stack layer configuration to transmission
Signal to the second stack layer carries out delay compensation.For example, delay phase-locked loop can be used for the phase difference exported based on phase discriminator
Delay compensation is carried out to the working signal of the second end output of above-mentioned first through silicon via.
In addition, phase difference can be sent to silicon intermediary layer by the phase discriminator in IC chip, silicon intermediary layer can be with base
Processing is adjusted to phase difference to integrate in the logic of itself, and sends compensation control to the delay phase-locked loop of each stack layer
Signal carries out delay compensation with the signal received to each stack layer.
In addition, the disclosure in addition to it delay phase-locked loop can be used to compensate delay, can also use phase calibrator
Signal to receive to each stack layer carries out delay compensation.For example, what phase calibrator can be used for exporting based on phase discriminator
Phase difference carries out delay compensation to the working signal of the second end output of above-mentioned first through silicon via.The mode specifically compensated with it is existing
The mode of delay compensation is similar, and it will not be described herein.
In conclusion it is logical to can detecte out failure silicon using the through silicon via detection circuit of disclosure illustrative embodiments
Hole, it is logical to shield failure through silicon via and to substitute the failure silicon using for example spare through silicon via based on the mode of through silicon via redundancy
Hole, or by sending instruction to the delay phase-locked loop or phase calibrator that correspond to stack layer, to via failure through silicon via
Signal carries out delay compensation, to achieve the purpose that handle failure through silicon via, and then facilitates each in IC chip
Effective transmission of signal.
Further, a kind of IC chip is additionally provided in this example embodiment, which can be with
Including through silicon via detection circuit described in any one of the above illustrative embodiments.
The IC chip that the disclosure provides is it is possible to prevente effectively from may cause integrated electricity since signal has delay
The problem of decline of road chip performance or failure.
Those skilled in the art will readily occur to the disclosure after considering specification and practicing utility model disclosed herein
Other embodiments.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes
Or adaptive change follow the general principles of this disclosure and including the disclosure it is undocumented in the art known in often
Knowledge or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are by right
It is required that pointing out.
It should be understood that the present disclosure is not limited to the precise structures that have been described above and shown in the drawings, and
And various modifications and changes may be made without departing from the scope thereof.The scope of the present disclosure is only limited by the attached claims.
Claims (10)
1. a kind of through silicon via detection circuit characterized by comprising the first through silicon via, the second through silicon via and phase discriminator；
The first end of first through silicon via is connect with prearranged signals output end, the second end of first through silicon via and described the
The first end of two through silicon vias connects；
The second end of second through silicon via is connect with the first input end of the phase discriminator；
Second input terminal of the phase discriminator is connect with the prearranged signals output end；
Wherein, the phase discriminator is for determining between the signal of first input end of the phase discriminator and the signal of the second input terminal
Phase difference.
2. through silicon via detection circuit according to claim 1, which is characterized in that first through silicon via and second silicon
Through-hole is connected to two or more stack layers.
3. through silicon via detection circuit according to claim 1, which is characterized in that the through silicon via detection circuit further includes
One selector and the first distributor；Wherein, first selector has first input end, the second input terminal, control terminal and output end,
First distributor has input terminal, control terminal, the first output end and second output terminal；
The first input end of the first selector is used to receive the first working signal of first through silicon via to be entered, described
Second input terminal of first selector is connect with the prearranged signals output end, and the control terminal of the first selector is for receiving
First detection control signal, the output end of the first selector are connect with the first end of first through silicon via；
The input terminal of first distributor is connect with the second end of first through silicon via, the control terminal of first distributor
For receiving the first detection control signal, the first output end of first distributor and the first of second through silicon via
End connection, the operation element connection corresponding with first working signal of the second output terminal of first distributor.
4. through silicon via detection circuit according to claim 3, which is characterized in that the through silicon via detection circuit further includes
Three through silicon vias；
Wherein, the first end of third through silicon via is connect with the prearranged signals output end, the second end of the third through silicon via with
The first end of second through silicon via connects.
5. through silicon via detection circuit according to claim 4, which is characterized in that the through silicon via detection circuit further includes
Two selectors and the second distributor；Wherein, second selector has first input end, the second input terminal, control terminal and output end,
Second distributor has input terminal, control terminal, the first output end and second output terminal；
The first input end of the second selector is used to receive the second working signal of the third through silicon via to be entered, described
Second input terminal of second selector is connect with the prearranged signals output end, and the control terminal of the second selector is for receiving
Second detection control signal, the output end of the second selector are connect with the first end of the third through silicon via；
The input terminal of second distributor is connect with the second end of the third through silicon via, the control terminal of second distributor
For receiving the second detection control signal, the first output end of second distributor and the first of second through silicon via
End connection, the operation element connection corresponding with second working signal of the second output terminal of second distributor.
6. through silicon via detection circuit according to claim 5, which is characterized in that the through silicon via detection circuit further includes
Three selectors and the 4th selector；Wherein, the third selector and the 4th selector all have first input end, second
Input terminal, control terminal and output end；
The first input end of third selector is connect with the output end of the first selector, and the second of the third selector is defeated
Enter end to connect with the output end of the second selector, the control terminal of the third selector is for receiving third detection control letter
Number, the output end of the third selector is connect with the second input terminal of the phase discriminator；
The first input end of 4th selector is connect with the first output end of first distributor, and the of the 4th selector
Two input terminals are connect with the first output end of second distributor, and the control terminal of the 4th selector is for receiving the 4th inspection
The output end of observing and controlling signal, the 4th selector is connect with the first end of second through silicon via.
7. through silicon via detection circuit according to claim 4, which is characterized in that the through silicon via detection circuit further includes removing
One or more through silicon vias except first through silicon via, second through silicon via, the third through silicon via；
Wherein, the first end of each through silicon via is connect with the prearranged signals output end in one or more of through silicon vias, institute
The second end of each through silicon via in one or more through silicon vias is stated to connect with the first end of second through silicon via.
8. through silicon via detection circuit according to claim 1, which is characterized in that belonging to the second end of first through silicon via
Stack layer have delay phase-locked loop；
Wherein, second end of the phase difference that the delay phase-locked loop is used to export based on the phase discriminator to first through silicon via
The working signal of output carries out delay compensation.
9. through silicon via detection circuit according to claim 1, which is characterized in that belonging to the second end of first through silicon via
Stack layer have phase calibrator；
Wherein, second end of the phase difference that the phase calibrator is used to export based on the phase discriminator to first through silicon via
The working signal of output carries out delay compensation.
10. a kind of IC chip, which is characterized in that detect electricity including through silicon via described in any one of claims 1 to 9
Road.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821451279.5U CN208767296U (en) | 2018-09-05 | 2018-09-05 | Through silicon via detection circuit and IC chip |
| PCT/CN2019/101884 WO2020048319A1 (en) | 2018-09-05 | 2019-08-22 | Through-silicon via (tsv) test circuit, tsv test method and integrated circuits (ic) chip |
| US16/950,020 US11114417B2 (en) | 2018-09-05 | 2020-11-17 | Through-silicon via (TSV) test circuit, TSV test method and integrated circuits (IC) chip |
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| CN201821451279.5U CN208767296U (en) | 2018-09-05 | 2018-09-05 | Through silicon via detection circuit and IC chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020048319A1 (en) * | 2018-09-05 | 2020-03-12 | Changxin Memory Technologies, Inc. | Through-silicon via (tsv) test circuit, tsv test method and integrated circuits (ic) chip |
| US11114417B2 (en) | 2018-09-05 | 2021-09-07 | Changxin Memory Technologies, Inc. | Through-silicon via (TSV) test circuit, TSV test method and integrated circuits (IC) chip |
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2018
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020048319A1 (en) * | 2018-09-05 | 2020-03-12 | Changxin Memory Technologies, Inc. | Through-silicon via (tsv) test circuit, tsv test method and integrated circuits (ic) chip |
| US11114417B2 (en) | 2018-09-05 | 2021-09-07 | Changxin Memory Technologies, Inc. | Through-silicon via (TSV) test circuit, TSV test method and integrated circuits (IC) chip |
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